Note: Descriptions are shown in the official language in which they were submitted.
TI-6890 tCa.)
~8~
sACKGROUND OF THE INVENTION
This invention relates to the generation of complex
waveforms using digital signals and more specifically to the
synthesis of speech by digital circuits using linear prediction
methods. Disclosed is a digital filter having an array multi-
plier for use in speech synthesis or waveform generation circuits.
The disclosed speech synthesis circuit may be integrated on a
single integrated circuit, thereby facilitating its use in
various applications in the communication handling industry,
including such applications as: teaching machines, communication
equipment (i.e., telephones, voice cryptographic equipment,
radios, televisions, etc.), and other equipment which generate
the sound of a human's voice.
Several methods are currently being used and experi-
mented with to digitize human speech. For example, pulse code
modulation, differential pulse code modulation, adaptive pre-
dictive coding, delta modulation, channel vocoders, cepstrum
vocoders, formant vocoders, voice excited vocoders, and linear
predictive coding methods of speech digitalization are known.
These methods are briefly explained in "Voice Signals: Bit by
Bit" at pages 28-34 in the October 1973 issue of IEEE Spectrum.
Computer simulations of the various speech digitaliza-
tion methods have generally shown that the linear predictive
methods of digitizing speech can produce speech having greater
voice naturalness than the previous vocoder systems (i.e.,
channel vocoders) and at a lower data rate than the pulse coded
modulation systems. As will be seen, the linear predictive
systems often make use of a multi-stage digital filter and as
the number of stages of the digital filter increases, the more
natural sounding becomes the resulting generated speech.
--1--
.~ .
TI--6890
04
An early application of linear predictive methods to
digital speech synthesis occurred in the late 1960's and early
1970's. A historical analysis of some of this early work is set
forth in Markel and Gray, "Linear Prediction of Speech" (Springer-
Verlag: New York, 1976) at pages 18-20.
TI-6890 (Ca.)
1~8~V4
The multi-stage digital filter used in linear predictive
coding is preferably an all pole filter with all roots preferably
occurring within the unit circle ¦z¦ =l when the mathematical
transfer function of the filter is expressed as a Z-transform.
The filter itself may take the form of a lattice filter of a
typical type. However, other filters including ladder filters,
normalized ladder filters and others are known, as set forth in
Chapter 5 of "Linear Prediction of Speech". As will be seen,
each stage of the lattice filter requires two addition opera-
tions, two multiplication operations and a delay operation.The filter is excited from either a periodic digital source
for voiced sounds or a random digital source for unvoiced sounds.
The filter coefficients are preferably updated every few milli-
seconds while the excitation signal is updated at a faster
rate.
In the prior art, a lattice filter network has been
implemented by appropriately programming large digital computers.
Exemplary Fortran programming of a computer for speech synthesis
purposes is set forth in the aforementioned "Linear Prediction
of Speech". Given the data rate of the excitation signal
and the large number of arithmetic operations, i.e., two multi-
plications and two additions for each stage of a multi-stage
filter and given that increasing the number of stages thereof
increases the naturalness of the generated speech, high speed
digital computers have been utilized in most speech synthesis
work done to date. However, Dr. J. G. Dunn, J. R. Cowan and
A. J. Russo of the ITT Defense Communications Division in
Nutley, New Jersey have attempted to implement a multi-stage
filter using metal oxide silicon (MOS) large scale integration
techniques. They attempted using a multi-processing approach,
wherein many arithmetic units are operated simultaneously;
~f x~
,~ .
1118104
however, this technique requires a very large number of multiplier
and adder circuits be implemented on a semiconductor chip. Some
discussion of the work done by Dr. Dunn et al is set forth in
''Progress in the Development of Digital Vocoder Employing an Itakura
Adaptive Predictor" published in "Telecommunications Conference
Records, I.E.E.E. Publ. No. 73" (1973). Replacing t~ lattice
A structure of-PICUnE 2a with various adders and multipliers results
in a complex and large size semiconductor chip.
It was one object of this invention, therefore, to implement
10 a lattice type filter for generating complex wave forms, such as
human speech, on a single semiconductor chip.
It was another object of this invention, that the filter
components be implemented with MOS devices.
It is still yet another object of this invention that the
resulting MOS filter be of smaller size than that heretofore known
in the prior art.
The foregoing objects are achieved as is now described.
The digital filter includes a multiplier, one input of which receives
the filter coefficients from a memory. The output of the multiplier
20 is applied to one input of an adder/subtractor, whose output is
applied to a short delay circuit. The output of the short delay
circuit is applied to a long delay circuit. The short and long
delay circuits preferably comprise shift registers of short and
long lengths, respectively. The output of the long delay circuit
is coupled to a latch memory via a switch. The other input to
the multiplier is selectively coupled to the output of the adder/
subtractor, the output of the short delay circuit or the output
of the latch memory. The other input to the adder/subtractor is
selectively coupled to the output of the latch memory, the output
3 of the long delay circuit or the output of the adder/subtractor.
--4--
TI-6890 (Ca.)
8~04
The multiplier is preferably an array multiplier. The output of
the filter is provided at the output of the latch memory and the
input is either coupled to the adder/subtractor or the multi-
plier in the two disclosed embodiments.
BRIEF DESCRIPTION OF THE DRAWINGS
_
The novel features believed characteristic of the
invention are set forth in the appended claims. The invention
itself, however, as well as a preferred mode of use and further
objects and features thereof, will be best understood by
reference to the following detailed description of illustrated
embodiments thereof when read in conjunction with the accom-
panying drawings, wherein:
FIGURE la is a block diagram of the basic elements of
a voice synthesizer;
FIGURE lb depicts the presence of the excitation
signal and Kn coefficients with respect to time;
FIGURES 2a and 2b show a typical lattice filter of
the type used in speech synthesis circuits;
FIGURES 3 shows a timing arrangement for the genera-
tion of intermediate results in a lattice filter having N stages;
FIGURE 4 depicts a timing arrangement for the genera-
tion of intermediate results in a lattice filter having ten
stages;
FIGURE 5 shows one embodiment of a digital filter
equivalent to a lattice filter;
FIGURE 6 lists the various intermediate results
available in the filter of FIGURE 5 at various time periods of
a cycle;
FIGURE 7 shows another embodiment of a digital
filter equivalent to a lattice filter;
--5--
11~8:~04
FIGURE 8 lists the various intermediate results available
in the filter of FIGURE 7 at various time periods of a cycle;
F~GURE 9 depicts the array multiplier used in the digital
equivalent filter;
FIGURES lOa-lOd are logic diagrams of the various elements
depicted in FIGURE 9s and
~ IrunE ll clcpicts a generalized Eorm of the digital ,~
filter.
DETAILED DESCRIPTION
Referring now to FIGURE la, there is shown, in block
diagram form, the basic elements of a voice synthesizer system.
The voice synthesis circuit comprises a multi-stage lattice filter
10, which digitally filters an excitation signal 11 using filter
coefficients Kl-Kn. Lattice filter lO outputs a digital signal 12
which is converted to analog form by a digital/analog converter 13.
The output of converter 13 is changed to audible sounds by a speaker
14 or other such sound conversion means; it is to be understood,
of course, that an amplifier may be used between converter 13 and
speaker 14 to amplify the analog output of converter 13 to levels
required by speaker 14.
The excitation signal (U) 11 is generally derived from
one of two sources, voicing source 15 or unvoicing source 16. The
particular source used is determined by a digital switch 17. Voicing
source 15 is utilized when generating those sounds for which the
human vocal cords or vocal folds vibrate during speech, such as
the sound of the first E in Eve. The rate at which the vocal folds
open and close determines the pitch of the sound generated.
Unvoicing source 16 is used when generating those sounds, such as
the F in Fish, where the vocal folds are held open and air is
30 forced past them to the vocal tract. Thus, the particular source,
15 and 16, utilized depends upon the source to be generated.
TI-6890
11:181~4
Typically, the unvoicing source 16 generates a random digital
signal while voicing source 15 generates a periodic digital signal.
The digital data supplied by voicing source 15 and unvoicing source
16 may, of course, be merely stored in one or more semiconductor
read-only-memories (ROM's). Preferably, however, such data is
stored in an encoded format, e.g., as pitch or a code actuating a
random number generator. Thus, such data is usually first decoded
before the random or periodic data (e.g., Signal V) is supplied to
filter 10. Of course, depending on how such data is stored, the
0 need for switch 17 may be eliminated. When the data is stored as
pitch or a code activating a random number generator, a amplification
factor (A) is preferably also stored in the ROM. Amplification
factor A adjusts the constant amplitude signal (V) from voicing
source 15 or unvoicing source 16 to produce the excitation signal
(V) for filter 10.
The excitation signal 11, which generally corresponds or
mimics the function of the vocal folds, is altered by lattiee
filter 10. Lattice filter 10 generally corresponds or mimics the
funetion of the voeal traek which filters the sounds generated at
20 the voeal folds. The filter coefficients, Kl-Kn, reflect the shape
(i.e.the resonances) of the vocal track during speech. Accordingly,
coefficients Kl-Kn are periodically updated to reflèct the changing
shape of the vocal track and may be stored along with the voicing/
~nvoicing source data in a read-only-memory.
Referring now to FIGURE lb, there is shown in graphical
form the outputs of unvoicing source 16 and voicing source 15
against time. Here voicing source 16 is shown as outputting an
impulse at a five millisecond period, which corresponds to a
frequency of 200Hz; this pitch corresponds to voiced sounds in
80 the vocal range of many women. Since men typically have a lower
pitch, a man's voicing source would output impulses less frequently.
~118~4
~ Joicing source ~ is shown as outputting impulses at a
period corresponding to the pitch of the person's voice; it is to
be understood, however, that the periodic impulses may be replaced
with other periodic functions, such as a decaying sine wave or the
so-called "chirp function", which restart with a pitch related
period. Unvoicing source 16 is shown as a random signal.
The coefficients for lattice filter 10 are be~ng shown
as being updated every five milliseconds in FIGURE lb. It is to
be understood, however, that the rate of which the coefficients
10 lattice filter 10 are updated is a design choice. If the
coefficients are updated more frequently, the more closely lattice
filter 10 will model the vocal track dynamics, but with a corresponding
increase in the amount of data to be stored in the aforementioned
ROM. Of course, updating the coefficients less frequently has the
opposite effect. However, it has been found that by updating the
w~\\ i s~c~v~ s
coefficients approximately every five ~iero~e~n~s or so results
in very high quality human speech being synthesized by lattice
filter 10 with reasonable data storage requirements.
The time axis of FIGURE lb is shown as being divided into
20 a hundred microsecond intervals. These intervals correspond to the
data rate from voicing source 15 and unvoicing source 16 as well
as the data rate to and from lattice filter 10. Further, while
unvoicing source 16 and voicing source 15 may appear to be analog
signals in FIGURE lb, it is to be appreciated that they are in
fact digital signals whose magnitudes are as shown and which are
updated at the intervals shown along the time axis of FIGURE lb.
For information regarding the derivation of the magnitudes of the
filter coefficients, reference should be made to the aforementioned
"Linear Prediction of Speech."
11~18~04
Thus, in this embodiment, the data rate to converter 13
would be lOKHz and the upper frequency limit of the synthesized
speech from converter 13 would be 5KHz. Of course, the data rate
may be altered, if desired, as a matter of design choice. For
, instance a 8KHz data rate would result in a synthesizer having an
upper frequency response of 4KHz.
Referring now to FIGURES 2a and 2b, there is shown a
block diagram of lattice filter 10. In FIGURE 2a lattice filter
10 is shown as comprising ten stages, Sl-S10, each of which is
IO equivalent to the stage depicted in FIGURE 2b. For ease of
illustration, only three of the stages are shown in detail in
FIGURE 2a. The input to the stage S10 is the excitation signal 11
and the output 12 from the stage Sl is applied to converter 13
(FIGURE la). It will be appreciated by those skilled in the art
that the output 27 from the S10 stage is not utilized and therefore
adder 27a and multiplier 27b in that stage may be deleted, if
desired.
Referring now to FIGURE 2b, there is shown a single stage
Sn of lattice filter 10. An input to this stage, Yn+l(i), is applied
as one :input to an adder 26 the output of which is Yn(i). The
other input to adder 26 which is applied to a subtraction input
of adder 26 is derived from the output of a multiplier 19 which
multiplies the coefficient Kn times the output from a delay circuit
22, which output is bn(i-l). The output from delay circuit 22 is
also applied to an adder 21 which also receives as an input the
output from a multiplier 20. Multiplier 20 multiplies the
coefficient Kn times the output from adder 26 which is, of course,
Yn(i). The output from àdder 21 is b +l(i). As can be seen, the
subscript of the Y and L data defines the stage in which that data
is utilized while the number appearing in the parentheses indicates
1~81~
the cycle in which that data was generated. Delay circuit 22
provides a one time cycle deIay function, such as may be supplied
by a shift register, for example. Once each time cycle a new data
point U(i) (or Yll(i)) is provided to stage S10 as the excitation
signal 11. Thus, for each stage in lattice filter 10, two
multiplications and two additions must be accomplished during each
cycle, that is, given the data rates depicted in FIGURE lb, those
four operations must be accomplished in 100 microseconds in each
stage of lattice filter 10. As a matter of design choice, lattice
filter 10 in FIGURE 2a is shown as having ten stages; however, it
will be appreciated by those skilled in the art, that the number
of stages may be varied as a design choice according to the quality
of sound desired to be synthesized by lattice filter 10. It has
been found that a ten stage lattice filter 1~ can synthesize speech
which is virtually indistinguishable from actual human speech.
It will be appreciated then that during any given time
cycle, the ten stage lattice filter 10 must accomplish twenty
multiplications and twenty addition/subtraction operations. It
should be further appreciated that those operations cannot all be
accomplished simultaneously, inasmuch as, Ylo must be calculated
befcre Yg, which must be calculated before Y8, etc., during any
given time cycle. Also during the same time cycle, the blo-b
data must be calculated and stored in the delay circuits 22 of
each stage for use during the next time cycle. The Y and ~ data
defined with respect to FIGURE 2b, is also shown for stages Sl,
Sg, and S10 in FIGURE 2a. Equations expressing the relationship
between the various Y and ~ data are set out in Table I. It should
be appreciated that Y and ~ data as well as the coefficients Kn
are multi-digit numbers; that coefficients Kl-Klo may vary between
a decimal equivalent of plus and minus one and are periodically
updated in a manner to be described.
--10--
1~18104
Referring now to FIGURE 3, there is shown, in representative
form, various intermediate results attained from the multipliers
B and adders of'lattice filter having N stagesr -t~e horizontal axis
depicts time while the vertical axis represents the various stages
, of an N stage lattice filter 10. In the N stage, for example,
the intermediate results, -K .bn and Kn.Y , which may be generated
by multipliers 19 and 20 (FIGURE 2b), respectively, and intermediate
~ \
results Yn and bn+l, which may be obtained from adders 26 and ~
(FIGURES 2b), respectively, are shown. Timewise, the intermediate
10 result -Kn.bn must be generated before Yn may be obtained; Yn must
be generated before Kn.Yn may be generated; and Kn.Yn must be
generated before bn+l may be produced. According to the depicted
time scale, addition operations are shown as taking a five
microsecond time period while the multiplication operations take
a longer time period. As to the relationship of the generation of
the intermediate results with respect to the different stages, it
can be seen that the bn output from an add operation must be
available before the -Kn.bn multiply operation is initiated, as is
depicted by arrow 25. This fact necessitates that a "no operation"
20 period 23 be inserted between the bn+l add operation and the
-Kn.bn multiply operation, if only one add operation and one multiply
operation are to be initiated during any given five microsecond time
period, as can be seen from FIGURE 3. "No operation" periods 24
are inserted after the other add operation before the following
multiply operation for symmetry purposes. Thus, it can be seen
that the operations indicated in all the stages of an N stage
lattice filter may be accomplished concurrently in the order depicted
in FIGURE 3 and appropriate intermediate results will become
available as needed. FIGURE 3 depicts the general nature and
3~ applicability of the digital implementation of a multi-stage
lattice filter to be described. It is to be appreciated that the
representation of FIGURE 3 shows those operations accomplished
during one of the aforementioned time cycles. The f ive microsecond
~118~04
time period for an add operation is selected as a design choice
because of its compatibility with P-channel MOS integrated circuits.
Of course, other time periods may be used if desired.
Referring now to FIGURE 4, there is shown a representation
similar to FIGURE 3; however, the FIGURE 4 representation is for
a digital implementation of an equivalent ten stage lattice filter
10 and the horizontal time axis has been increased to show more than
one time cycle. Further, the time cycle has been broken down into
twenty time periods, Tl-T20, each of which preferably has a duration
on the order of five microseconds; as has been previously mentioned,
other periods may be selected. Also in FIGURE 4, the time cycles,
e.g., i-l, i and i+l, are indicated for ease in comparing the
availability of intermediate results in filter 10 with the requirement
set out by the mathematical formula representation of filter 10 in
Table I.
At the first time period, Tl, the excitation data U is
applied as an input; the output of the filter, Yl, becomes available
at time period Tll. It can be seen by comparing FIGURE 4 and Table
I that the various inputs required for the multiply operations are
20 available when needed and that the various inputs for the add
operations are also available when needed. It can further be seen
from FIGURE 4 that an add operation (which preferably takes one
time period) is initiated and completed every time period and a
multiply operation is similarly initiated (and completed) every
time period although the particular multiply operation then being
initiated will not be completed for eight time periods. The
apparatus for performing these operations will be described in
detail with respect to FIGURES 5, 9 and 10a-d.
It has been mentioned that a multiply and an addition
operation are each initiated preferably each time period. In fact,
-12-
Y U
1~18104
the number of time periods in a cycle preferably equals twice the
number of stages in the equivalent lattice filter. Thus for eight
or twelve stage lattice filters, the equivalent digital filter
preferably has sixteen or twenty-four time periods per cycle,
respectively. It should be evident from examining FIGURES 3 and 4,
that the number of time periods allotted for the multiply operation
depends, in part, on the number of time periods in a cycle. Thus,
eight time periods may be used for multiply operations in a ten
stage equivalent digital filter while six time periods may be used
lû for multiply operations in an eight stage equivalent digital filter,
if the digital equivalent filter scheme of FIGURES 3 and 4 is
followed. It should be evident to those skilled in the art, however,
that the number of time periods for multiply operation tends to
dictate the number of bits which may be multiplied, i.e., tends to
limit the number of bits used to represent the Kn coefficients. In
most applications, the number of bits allotted to the K~ coefficients
by following the processing scheme of FIGURES 3 and 4 will yield
very acceptable synthesized speech. If, however, even greater
accuracy is desired in representing the Kn coefficients, a multiply
and a addition operation may not be initiated every time period of
a cycle and some delay should be inserted at some point during the
cycle. Of course, then the cycle would take a longer time to
complete, thereby lowering the data rate (and frequency response)
of the system.
As can be seen from FIGURE 4, the Klo.Ylo and bll
intermediate results are obtained or may be obtained; however, as
mentioned with respect to FIGURE 2a, these particular intermediate
results are not required for a digital implementation of the lattice
filter. It will be seen with respect to FIGURE ~, however, that
the Klo.Ylo and bll intermediate results (or some other numbers)
~118~04
are often more easy to generate (and ignore) than it is to inhibit
the apparatus from making these calculations. Further, it will be
subsequently described how the multiply operation performed by
multiplier 18 (FIGURE 1) may be accomplished in lieu of calculating
Klo-Yl~o by the apparatus.
In FIGURE S there is shown a block diagram of a digital
implementation of an equivalent lattice filter 10. The filter
includes an array multiplier 30, adder/subtractor circuit 33, one
period delay circuit 34, a shift register 35, and a latch memory 36.
The data inputted to and outputted from these various units at each
of the twenty time periods Tl-T20 (for an equivalent ten stage
lattice filter) are listed in FIGURE 6. Referring now to FIGUR~S
5 and 6, array multiplier 30 accomplishes the multiplications
performed by multipliers 19 and 20 (FIGURES 2a and 2b) in each of
the stages of the lattice filter. The array multiplier receives
the coeficients K~-KS~, which are stored in K-stack 31, via
lines 32 and either Yn or bn data via bus 40. K-stack 31
preferably comprises ten shift registers, each of which has ten
stages. The data stored in K-stack 31 i5 depicted in Table II
and transmitted to array multiplier 30 via lines 32. Array
multiplier 30 initiates a different multiplication operation every
time period (as indicated by FIGURE 4) i.e., approximately every
five microseconds. Array multiplier 30, as will be seen with
respect to FIGURE 9 preferably has eight stages; a series of
addition and shift operations accomplished as the data propagates
through these eight stages, the data is multiplied by the
appropriate Kn coefficient stored in K-stack 31. The multiply
operation takes 40 microseconds; however, since a new multiplication
operation is initiated every five microseconds, eight multiplications
are in various stages of completion at any given time. The eignt
time period computation period of array multiplier 30 can be seen
104
with respect to the multiplier inputs and outputs in FIGURE 6. For
example, the multiplier inputs at time period Tl are outputted
from multiplier eight time periods later, at T9. The coefficients
stored in K-stack 31 are stored as a nine bit number plus an
additional bit for sign information. As aforementioned, these nine
bit numbers range from -1 to +1, (decimal equivalents), which, as
will be seen, simplifies the structure of array multiplier 30.
The output of array multiplier 30 is applied to adder/
subtractor circuit 33. This output, in the preferred embodiment,
is a thirteen bit parallel channel: twelve bits of data and one
bit for sign information. It will be appreciated by those skilled
in the art, moreo~er, that the number of bits in the data channel
are a design choice. The other input to adder/subtractor circuit
is provided from (1) the exictation signal 11 at time period Tl,
the output of adder/subtractor circuit 33 during time periods
T2-T10, the output of shift register 35 during time periods Tll-Tl9
and the output of latch 36 at T20. The particular input to adder/
subtractor circuit 33 is shown, for ease of illustration, as being
controlled by various single-pole, single throw switches 37a-37d;
however, it should be appreciated that solid state switches would
preferably be used to perform these switching functions, as well
as the other depicted switching functions. The output of adder/
subtractor circuit 33 is applied to switch 37b, switch 38a and as
the input to one period delay circuit 34. The output from adder/
subtractor circuit 33 is also a thirteen bit wide parallel channel
which is delayed by one time period in circuit 34 before being
applied as the input to shift register 35 and to switch 38b. Shift
register 35 stores the data from the thirteen bit wide channel in
thirteen shift registers, each of which has eight stages. Shift
register 35 is arranged to perform shift operation only during
~18104
time periods T12-T2. The output of shift register 35 is applied
to switch 37c and switch 39. Switch 39 closes at time period T20
for clocking the output of the filter, Yl, into latch memory 36.
~ 0 c,~ ~ ~\ 0,~
B The output 12 of latch memory 36 is applied to analog t3-di-
~converter 13 (FIGU~E la) and to switches 37d and 38c.
~, Switch 37b is closed during time periods T2-T10, switch
37c is closed during time periods Tll-T19 and switch 37d is closed
at time period T20. Switch 38a is closed during time periods
T13-Tl, switch 38b is closed between time periods T3-T12 and switch
38c is closed for time period T2. The other sides of switches 38a,
3gb and 38c are connected to the input to array multiplier 30 via
bus 40.
In FIGURE 6 there is listed the various intermediate
results occurring in the circuit of FIGURE 5 during time periods
Tl-T20. Referring briefly to FIGURE 6, it can be seen that one
of the multiplier inputs is the Kn coefficient information while
the other input varies according to which switch 38a-38c is closed.
0 ~
At time ~eiro~ Tl switch 38a is closed, as aforementioned, so
that the output of the adder/subtractor 33, in this case ~
is applied as a multiplier input. At the same time the other
adder input is the excitation signal U(i). At time period T2,
the other multiplier input is bl;i-l) which, according to FIGURE
5, is being loaded from the output of latch 36 via switch 38c.
The output of latch 36 according to FIGURE 6 is then Yl(i-l), but
recalling the last entry in Table I, it is to be remembered that
bl(i-l) is set equal to a delayed Yl(i), i.e., Yl(i-l). Also at
time period T2, the other adder input is that which is being currently
outputted at the adder output, i.e., in this case, Ylo(i). At
time period T3 the multiplier inputs are Klo and Ylo(i), which is
derived from the output of one period delay circuit 34. Of course,
the results of this multiplication will not be available until
time period Tll, at which time it will be provided as one of the
.. . .
. .
-16-
1~1810~
inputs to adder/subtractor circuit 33. At time period Tll the
other input to adder/subtractor clrcuit 33 is taken from the
output of shift register 35. The first term loaded from shift
~register 35 is the hlo(i-l) term which was first outputted from
shift register 35 at time period T2 and remained at the output
thereof since shift register 35, as aforementioned, does not shift
between time periods T3 and Tll.
At time period T13 the input to array multiplier
30 is again provided from the output of adder/subtractor circuit 33
via switch 38a. At time period T20 the Yl(i) term is outputted to
latch memory 36 from shift register 35 and the current output of
latch 36, Yl(i-l) is applied to the other input ~adder/subtractor
circuit 33 via switch 37d for providing the bl(i-l) term, as
aforementioned. Latch memory 36 stores the filter output (Yl) for
one cycle.
The block diagram of FIGURE 5 has been previously
explained. The filter of FIGURE 5 may also be utilized in an
application equivalent to a N-stage filter having an M-stage
multiplier (e.g., there may be M+2 bits in the Kn coefficients),
2~ if a shift register having a delay equivalent to N-M-2 time periods
is inserted between adder~subtractor circuit 33 and one period
delay circuit 34. The connection to switch 38A is then made from
the output of the added shift register and the delay associated
with shift register 3~ should then be set equal to N+M-l.
This generalized form of the digital filter is depicted in Figure 11.
In the embodiment of Figure 5, N-M-2 is equal to zero, so no dela~ is
required in that embodiment. In the embodiment described with
reference to FIGURES 5 and 6, N+M-l equals seventeen which reflects
the number of time periods between the time data is applied to shift
register 35 and the time that data exits shift register 35. For
instance, in FIGURE 6, the b2 (i-l) data is inserted into shift
register 35 at time period T2 and exits shift register 35 at time
~8~04
period Tl9, seventeen time period~ later. Ho~ever, shift register
35 only has eight stages in this embodiment, the additional delay
occuring during the T3-Tll time periods that shift register 35 is
' not shifted. These nine time periods correspond to when the Y2-Y10
data is available at the output of one period delay circuit 34,
which data need not be inputted into shift register 35, as can be
seen in FIGURE ~. Thus, the number of stages in shift register 35
plus the number of time periods per cycle that data is not shifted
in shift register 35 (if any) equals the N+M-l time period delay
through shift register 35.
As can be seen, the equivalent ten stage lattice filter
of FIGURES 5 and 6 pèrforms the filtering operation required by the
lattice filter 10 of FIGURE la at reasonable data rates. For example,
in the preferred embodiment, excitation data 11 is applied at a
ten ~ilohertz rate (i.e. every 100 microseconds) and the basic
addition operations in adder/subtractor circuit 33 as well as in
array multiplier 30 and the shift operations in one period delay
circuit 34 and shift register 35 are accomplished in nominal five
microsecond time periods. As is well known to those skilled in
the art, such speeds are well within the speed capabilities of
P-channel MOS large scale integration devices so that the filter
of FIGURE 5 may be incorporated in a relatively inexpensive
P-channel MOS LSI speech synthesis or complex waveform generation
chip.
- 17a -
o~ ~
It should also be evident to those skilled in the art,
tn~lt the basic arrangement of the ten stage equivalent lattice
filter of FIGURE 5 is also applicable to digital filters equivalent
to lattice filters having other numbers of stages. Ten stages
were selected for the preferred embodiment of the filter, inasmuch
as ten stage lattice filters for linear predictive coding speech
synthesis circuits have been selected as the standard for use by
the Department of Defense of the United States Government. However,
should those wishing to practice this invention desire to utilize
lO a digital lattice filter having a different number of equivalent
stages, it is noted that the number of time periods into which a
B cycle is divided should at least~equal to twice the number of
equivalent stages. Thus, in the preferred embodiment, the number
of time periods (twenty) equals twice the number of equivalent stages
(ten). For example, if a twelve stage equivalent filter were
desired, the number of time periods per cycle should be at least
twenty-four and the basic design heretofore described would merely
be expanded. It is noted that for a twelve stage equivalent digital
lattice filter that the array multiplier 30 thereof could utilize
a O ten time periods to complete a multiplication if the basic scheme
heretofore described is followed i.e., one addition and one
multiplication operation is initiated each time period. This can
be seen from FIGURE 3 by setting N equal to twelve and completing
the FIGURE 3 diagram accordingly. Of course, if the five microsecond
period for each time period were maintained, the data rates which
O- C c ~w~ o ~
may be acco~dated by the twelve stage version would be less than
that for the ten stage version of the filter. It should be also
noted that by increasing the delay time through the array multiplier
30, that the number of bits in the Ki-K~ coefficients could be
80 increased from a total of ten bits to a total of twelve bits.
-18-
Similarly, if an eight stage equi~-alent digital filter were desired,
I number of time periods in a cycle would then be at least
sixteen and by setting N equal to eight in FIGURE 3 it can be seen
o ~ c~
that the propagation time thorug~ multiplier 30 would then be six
time periods. In that case, using the array multiplier, which is
subsequently described in detail, would limit the number of bits
in the coefficients from K-stack 31 to having no more than eight
bits. However, as was previously mentioned with respect to FIGURE 4,
even more time periods may be used to accomplish a multiply
10 operation in certain embodiments. This may be desired here, as a
design choice, if additional accuracy is desired in the ~n
coefficients. The additional accuracy would require more bits
in the Kn coefficients, which ~n~n, requires more delay through
array multiplier 30. The basic design of equivalent filter of
FIGURE 5 would be modified somewhat because then a multiply and
an addition operation would not be initiated every time period.
It should be evident to those skilled in the art, that in that
case, some of the intermediate results obtained within the filter
would have to be stored temporarily, thereby, requirins additional
20 storage elements to be included in the filter of FIGURE 5. While
such modifications are not spelled out here in detail, such
modification to the digital implementation of lattice filter should
be within the skill of knowledgeable digital circuit designers.
It has previously been mentioned that the K1o.Ylo(i) and
bll(i) intermediate results are generated by the digital filter of
FIGURE 5, but these intermediate results are not utilized inasmuch
as they are not required to implement lattice filter 10 of FIGURE
la. Now, recalling that the data (V) from the voicing or unvoicing
source is multiplied by an amplification factor (A) by a multiplier
30 18 in the conventional speech synthesis circuit of FIGURE la, it
--19--
has been ~ound that this multiplication may be done by array
ltiplier 30 during the time that Klo.Ylo(i) would otherwise be
generated by the array multiplier. An embodiment of the digital
filter performing this multiplication V(i).A is shown in FIGURE 7.
In FIGURE 8, there is shown the various intermediate results generated
in the circuit of FIGURE 7.
i Referring now briefly to FIGURES 7 and 8, it can be seen
that this circuit (including the intermediate results generated
thereby) is similar to the circuit of FIGURE 5, with the following
10 modifications. The identification numerals of FIGURE 7 are
generally the same as used in FIGURE 5, but have a prime added
thereto for ease of identification. The data (V) to be multiplied
~by m~Hby~b~Lo~ factor A is applied to one input of array
multiplier 30' via a switch 38d' at time period T3 in lieu of
applying the output of the one period delay circuit 34 at that time.
At time period Tll, when the multiplication has been completed to
form U(i+l), i.e., A-V(i+l), logical zeroes are inputted to the
other input of adder/subtractor circuit 33' in lieu of inputting
the blo(i-l) in data from shift register 35. Also, of course,
20 ~oth K~ coefficient data and A amplification data must be inputted
to K-stack 31'. As can be seen from FIGURES 7 and 8, this
embodiment incorporates the function performed by multiplier 18
(FIGURE la) into the digital implementation of lattice filter 10.
The data stored in K-stack 31' is depicted in Table III. The
amplification factor A is preferably updated at the same rate as
the Kn coefficients are updated in K-stack 31'.
Referring now to FIGURE 9, there is shown, in block
diagram form, array multiplier 30. Lines 32-1 through 32-9 ~ ~rrs
the least significant through most significant bits, respectively,
~0 of coefficient data from K-stack 32. On lines 32-10 is received
~118104
-20-
the sign data from K-stack 31. Another input to array multiplier
~ is received via bus 40. Lines 40-l through 40-12 of bus 40
carry the least significant through most significant bits,
~o--~ ~
g respectively, and line ~3-~ carries the sign of the data on bus 40.
In FIGURE 9, there is an array of elements having reference
letters A, B, C, or D (the elements with no reference letter are
aiso "Al' type elements, e.g., also correspond to FIGURE lOa). These
elements A-D, correspond to the circuits of FIGURES lOa-lOd,
respectively. Referring briefly to FIGURES lOa-lOd, the circuits
10 thereof are each enclosed via a dashed line with certain conductors
extending across the dashed line. The relative position of the
conductors extending across the dashed line of FIGURES lOa-lOd
correspond location-wise to the conductors contacting elements A-D
in FIGURE 9. In FIGURE 9, the elements are arranged in eight rows
and twelve columns. The eight rows correspond to the eight
previously mentioned eight stages of array multiplier 30. These
stages are identified on the right-hand side of FIGURE 9 and
include the eight shift register cells 51 coupled to line3 40-13.
The twelve columns correspond to the twelve bits of numeric data
20 (on lines 40-l through 40-12) inputted to array multiplier 30.
The data on lines 40-l through 40-13 propagate through array
multiplier 30 stage-by-stage in a shift register fashion as it
is being multiplied in array multiplier 30. Thus, the propagation
time through any given stage is on the order of the aforementioned
five microseconds or so.
~ n~32-l from K-stack 31 is coupled to one input of
twelve AND gates 52-l through 52-12, the other input of each one
being connected to lines 40-1 through 40-12, respectively. The
outputs of AND gates 52-12 through 52-1 are applied to the partial
~0 sum inputs of the type A and B elements of stage l (See FIGURES
lOa and lOb).
Lines 32-2 through 32-8 are coupled to the K-stack
inputs of the A type elements (FIGURE lOa) in stages 1-7, respectively,
~21-
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~1~81~
of array multiplier 30. Line 32-9 is coupled to the input there-
from in the C type elements of stage 8 (See FIGURE 10c). The
data on lines 40-1 through 40-12 is coupled to the "data-in"
inputs of the stage 1 elements and coupled therethrough to stage
2 through stage 8 elements by the "data-out" terminals of those
elements. The partial sum input of the stage 1 elements is
derived from the outputs of AND gates 52-1 through 52-12. In
the following stages, the partial sum input is derived from the
partial sum output from the next more significant bit of the
prior stage, with the exception of the partial sum input of
element in the most significant bit position whose partial sum
input is derived from the carry output from the most significant
bit position in the prior stage. Otherwise, the carry-out
connections from the elements are serially connected to the
carry-in connections in each stage.
Referring now briefly to FIGURE 10a, the data from
K-stack 31 determines whether the "partial sum" is to be directly
connected to the "partial sum" via a transfer gate 60 or to
the output from exclusive OR gate 62 via a transfer gate 61.
An AND gate 63 and an exclusive OR gate 64 are responsive to
the data on "data-in" and "partial sum in". Exclusive OR gate
62 is responsive to the output from exclusive OR gate 64 and to
"carry-in". An AND gate 65 is responsive to the output of
exclusive OR gate 64 and to "carry-in" and the output thereof
is provided along with the output from AND gate 63 to an OR
gate 66, whose output is "carry-out." "Data-out" corresponds
to "data-in" delayed by a shift register section 67 comprising
two inverters, for instance. As can be seen from FIGURE 10c,
a C type element is identical to an A type element with the
exception that no "data-out" connection is provided nor is a
shift register 67 provided. In FIGURE 10b, a B type element
is shown which merely provides a "data-out" connection coupled to
-22-
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~1~8~04
a shift register 67' whose input is "data-in" and a "carry-out"
connection provided by an AND gate 68 whose inputs are "data-in"
and "partial sum in". In FIGURE lOd, the D type element provides
merely a "carry-out" signal from an AND gate 68' whose inputs are
"data-in" and "partial sum in".
As can be seen, a new partial sum is calculated at each
stage, including a necessary transfer of carry information
between elements of a stage, but the "partial sum out" remains
unchanged if the data on the K-stack line is a logical zero or is
added to the data on "data-in" to provide the "partial sum out"
if the data on the line from K-stack 31 is a logical 1. The
partial sums are shifted to succeedingly less significant places
as data is shifted through the array multiplier. Of course, a
least significant bit is lost in each stage of the array multi-
plier. However the Kn coefficient data from K-stack 31 corres-
ponds to a number in the decimal range of -1 to +1; thus if
logical zeroes appear on lines 32-1 through 32 9, the output from
array multiplier 30 will be a logical zero and conversely, if the
data on lines 32-1 through 32-9 are all logical ones, the data
inputted on bus 40 will be outputted from array multiplier 30
unchanged. For the other possible data patterns on lines 32-1
through 32-9, the data on bus 40 will be scaled between zero and
the inputted value on bus 40 in 29 possible steps, according to
the magnitude of the data on lines 32-1 through 32-9.
Inasmuch as the data shifts through array multiplier
30 stage-by-stage in a shift register fashion, the data from
K-stack 31 is skewed as shown in Tables II and III, for
instance, to assure that the appropriate bit of the appropriate
coefficient arrives at the appropriate time in array multiplier
30. In FIGURES lOa-lOc the timing pulses for operating
those circuits in the aforementioned shift register
fashion are not depicted here, for, as is well known
-23-
to those skilled in the art, such timing fun_tion may be provided
~ adding clocked gates to the circuits of FIGURES lOa-lOc or by
utilizing precharge and conditional discharge type logic, and
therefore such timing considerations are not shown here in detail.
Referring again briefly to FIGURE 9, the sign data on
Ll ~i~.
~ e~ 40-13 is merely delayed during the eight stage delay or array
multiplier 30 via shift register elements 51 and then compared with
the sign data from K-stack 31 on line 32-10 at exclusive OR gate 53,
thereby providing a correct sign of the outputted data according
10 to the normal rules of multiplication.
Referring again briefly to FI~URES 5 and 7, the array
multiplier 30 (or 30') thereof has been described in detail. The
remaining elements, such as the adder/subtractor circuit 33 (or 33'),
~period delay circuit 34 (or 34'), shift register 35 (or 35')
and latch memory 36 (or 36') are not shown in such detail, since
such conventional elements are well known. The adder/subtractor
circuit 33 (or 33') receives signed data on its two inputs and
should determine whether a subtraction or addition operation is
called for based on the particular sign inputted with the data.
Hàving described the invention with respect to several
embodiments thereof, additional modification may now suggest itself
to those skilled in the art. The invention is not to be limitea
to the particular embodiments described, except as set forth in
the appended claims.
~B~04
-24-
TABLE I ~8~
EQUATION STAGE
10 (i) Yll (i) -Kloblo (i-l) 10
,j Yg (i)=Ylo (i) -K9bg (i-l) 9
blo(i)=bg(i-l)+KgYg(i) 9
8(i) Yg(i)-K8b8(i-1) 8
bg(i)~b8(i-l)+K8Y8(i)
7(i) Y8(i)-K7b~(i-1)
b8(i)=b7(i-1)+K7Y7(i) 7
6(i) Y7(i)-K6b6(i-1) 6
b7(i)=b6(i-l)+K6Y6( ) 6
.
5(i) Y6(i)-K5b5(i-1) 5
b6(i)=b5(i-l)+K5Y5(i) 5
Y (i)=Y (i)-K b4(i-1) 4
b (i)=b (i-l)+K4Y4(i) 4
3(i) Y4(i)-K3b3(i-1)
b (i)=b (i-l)+K3Y3(i) 3
2(i) Y3(i)-K2b2(i-1) 2
b3(i)=b2(i-l)+K2Y2( ) 2
Yl (i) Y2 (i) -Klbl (i-l)
b2 (i) =bl (i-l) +KlYl (i)
bl ( i) =Yl ( i )
1~8104
TABLE I I
DATA OUTPUTTED FROM K-STACX 31 BY TIME PERIODS
K-STACK
OUTPUTTIME PERIOD
Bit I Linel Tl T2 T3 T4 T5 T6 T7 T8 T9 TlO
_ _ _. TllTl2T13 Tl4 T15 T16 T17 T18 T19 TZO
LSB32-1 2 lKlo Kg K8 K7 K6 K5 K K
32-2 2KlKlo Kg K8 K7 K6 K5 K4 K3
32-3 3 2 1 Klo Kg K8 K7 K6 K5 K4
32-4 4 3 2 Kl K10 Kg K8 K7 K6 K
32-5 K K4 K3 K2 Kl KlO Kg K8 7 6
32-6 K6K5 K4 K3 K2 Kl K10 9 8 7
32-7 7 6 5 K4 K3 K2 Kl KlO Kg K8
32-8 8 7 6 K5 K4 K3 K2 Kl K10 Kg
MSB32-9 K K8 K7 K6 K5 K4 K3 K2 1 10
SIGN
BIT32-ld K K8 K7 K6 K5 K4 K3 K2 1 10
-26-
o ~ 8~ o o
E~ ~ X
a~ o
0 o
X ~4 X
.j
X ~4
~D C~
X ;~ p~;m
U~ C~
a E~ ~ X~ x~
E~ ~ ~ ~ ~ ~ X ~ ~ ~ ~
m ~ K ~ ;~ X
H ~ a ~ ~ ~ ~ ~
H O E-~ X X ~ ~ X X ~ P~; ;Y;
H ~Y; H
~ ~ ~ ~ X~
o
a
~ m u~ ~ N ~`I
O E~ ~ X
E~ ~ X ~
E~ ~ X P~ ~ X
3~ X~ X X~
E~ X ~
~ X ~ ~ ~ X
,~ ~ ~ e~l U~ ~ l` C~ C~ o
,
E~
D ~ -- 2 7
