Note: Descriptions are shown in the official language in which they were submitted.
Cross Reference to Related Subject Mattex
For a related patent see "RAM Retention Durin~ Power
Up and Power Down" United States Patent 4,145,761. See also
"RAM Address Enable Circuit" copending application serial number
324,670, both assigned to the same assignee as the present appli-
cation.
Background of the Invention
This invention relates, in general to microprocessors,
and more particularly, to those microprocessors having an on-
chip random access memory (RAM).
Microprocessors have ~ained wide acceptance and haveproven very useful in many applications. In most cases, a micro-
processor is used in conjunction with external memories which
contain instructions and op-codes. Advances in ~SI techniques
have allowed inclusion of memories on the same chip as a micro-
processor, however, the memories had limited utility since they
were mainly used for temporary storage of data. It would be
highly desirable to have a random access memory (RAM) located
on the same integrated circuit chip as the microprocessor and
2Q interconnected in a manner to allow data from the RAM to be
coupled onto the internal microprocessor data bus. In addition,
in many applications it is desirable to be able to retain some
of the information contained in the RAM when the microprocessor
power is down. q'his is particularly true of micropPocessors
used in automobiles.
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~ SC-78281
Accordingly, it is an object of the present invention
to provide circuitry to interconnect a RAM to a micro-
processor internal data bus wherein both, RAM and
microprocessor, are on the same chip to permit data from
the RAM to be inputted to the microprocessor internal data
bus.
Another object of the present invention is to provide
the capability which allows a microprocessor to read the
contents of a RAM onto an internal microprocessor data bus
and to an external data bus which is external to the
microprocessor.
Yet another object is to provide a single integrated
circuit chip having a microprocessor and a RAM wherein the
RAM contains instructions.
A further object of the present invention is to
provide a method by which the contents of a RAM can be
coupled to a microprocessor instruction register via an
internal data bus of the microprocessor.
Summary of the Invention
In carrying out the above and other objects of the
invention in one form, there is provided a microprocessor
unit (MPU) having an on-chip RAM and including circuitry to
interconnect the RAM to the internal data bus of the micro-
processor. A sense amplifier is coupled to the RAM and
provides an output for the RAM. At least one buffer is
used to couple the output of the sense amplifier to a
bilateral switch which can controllably switch the output
SC-7~281
~18~1~
of the at l~ast one ~uffer to the microprocessor bus and to
an external data ~us.
Also provid~d i~ a method for entering ~ata Erom a RAM
to a microprocessor wh~n the R~ and ~icroprocessor are
S contained on a single inte~rated circuit chip. ~Ata is
selected ~ro~ a RAM location. lh~ data is coupled from a
sense a~plifier to a bilateral switch and is then
con~rollably switched to a microprocessor bus there~y
allowin~ RAM data to b~ transferred to an instruction
1~ register of the ~icroprocessor.
More particularly, there is provided:
An integrated circuit microprocessor having an
on-chip RAM and including circuitry to interconnect the R~
to an internal data bus of the microprocessor and to an external
data bus which interfaces to the integrated circuit micro-
processor, the circuitry comprising: a sense amplifier coupled
to the on-chip RAM and having an output; at least one buffer
coupled to the output of the sense amplifier for bufering the
output of the sense amplifier thereby providing a buffered out-
put; a bilateral switch coupled between the buffered output ofthe at least one bu~fer and the internal data bus, the bilateral
switch controllably providing an interconnect between the RAM and
the internal data bus, the bilateral switch including a transis-
tor coupling the buffered output of the at least Gne buffer to
the microprocessor internal data bus; a logic gate having an out-
put and at least a first and a second input, the first inpu~ of
the logic gate being coupled to the at least one bu~Fer, the
second input of the logic gate being coupled to a switchihg
signal and the output of the logic gate being coupled to the ex-
ternal data bus so that the logic gate can logically combinesignals on the first and second inputs of the logic gate; and a
second buffer having an input and an output, the second buffer
--4--
~8~
controllably coupled between the ~xternal data bus and the inter-
nal microprocessor bus, the second buffer having an input coupled
to the external data bus and having an output coupled to the
internal microprocessor bus thereby providing buffering between
the external data bus and the internal microprocessor bus.
There is also provided:
An integrated circuit microprocessor system includ-
ing an on-chip RAM and having circuitry for interconnecting the
RAM to an external data bus, which interfaces with the integrated
circuit microprocessor, and to an internal microprocessor data
bus, the circuitry comprising: a sense amplifier coupled to the
RAM and having an output; a first buffer coupled to the output
of the sense amplifier and providing an output, the first buffer
being for buffering the output of the sense amplifier; a second
buffer for coupling the output of the first buffer to the exter-
nal data bus, the second buffer providing additional buffering
to the output of the first buffer; a bilateral switch coupled
to the output of the first buffer for controllably switching the
output of the first buffer to the internal microprocessor data
bus; and a third buffer for coupling the external data bus to the
internal microprocessor data bus thereby pro~iding buffering
between the external data bus and the internal microprocessor
bus.
There is further provided:
A method for entering data from a RA~I to a micro- -
processor wherein the RAM and microprocessor are contained on a
single integrated circuit chip, said method comprising: select-
ing data from a RAM location and temporarily placing the data in
a sense amplifier; coupling the data from the sense amplifier to
a bilateral switch; and controllably switching the data from the
bilateral switch to an internal microprocessor data bus to allow
-4a-
RAM data to be transferred to an instruction xegister of the
microprocessor thereby permitting the RAM to contain instructions
and operation codes since the data from the RAM can be transferred
to the instruction register of the microprocessor.
There is further provided:
A single integr~ted circuit chip containing a micropro-
cessor and a RAM and having circuitry for interconnecting the RAM
to an internal microprocessor data bus, the circuitry comprising:
a sense amplifier coupled to the RAM and providing an output which
is an output from the RAM; a first buffer coupled to the sense
amplifier for buffering the output of the sense amplifier and
thereby providing a buffered output; a first controllable coupler
coupled to the output of the first buffer and controlled by a
read signal for coupling the buffered output of the sense ampli-
fier; a second buffer coupled to the first buffer by the first
controllable coupler for further buffering the output of the
sense amplifier; a second controllable coupler connected to the
second buffer for coupling an output from the second buffer; and
a bilateral switch coupled to the second controllable coupler
to switch data from the RAM to the internal microprocessor data
bus whenever it is desired to transfer data from the RAM to the
internal microprocessor data bus.
The subject matter which is regarded as the invention
is set forth in the appended claims. The invention itself, how-
ever, together with further objects and advantages thereof, may
be better understood by referring to the following detailed des-
cription taken in conjunction with the accompanying drawings.
Brief Description of the Drawings
FIG. 1 is a block diagram of a microprocessor having an
on-chip RAM;
FIG. 2 is a logic diagram of a portion of the system
of FIG. l;
,~ - 4b -
8~
FIG. 3 is a block dia~xam of the RAM of FIG. 1; and
FIGs. 4A and 4B show portions of the circuitry of
FIG. 2 in block dia~ram form.
The exemplification set out herein illustrates the
preferred embodiment of the invention in one form thereof, and
such exemplification is not to be construed as limiting in any
manner.
Description of the Preferred Embodiments
Placing a RAM on the same integrated circuit chip as a
microprocessor makes greater use of the integrated circuit chip
area and advances in MOS large scale integration (LSI) techniques
have allowed such. However, being able to input data from the
RAM onto a microprocessor internal bus greatly enhances the util-
ity of the chip. A method for entering data from a RAM to a mi-
croprocessor when the RAM and microprocessor are contained on a
single integrated circuit chip includes selecting data from a RAM
location, and coupling the data from a sense amplifier to a bi-
lateral switch. The bilateral switch is then controllably switched
to permit the data from the RAM to be transferred to the micro-
processor data bus. The data is then accessible to the instruc-
tion register of the microprocessor thereby permitting the RAM
to contain instructions and operation codes. A portion of the
RAM is powered by a standby power supply which remains energized
when the microprocessor's power is removed. This permits the RAM
to retain the data stored therein. Access to the RAM during
power up and power down conditions is inhibited to ensure that
the data contained within the RAM is not destroyed nor modified.
Fig. 1 illustrates a microprocessor unit 10 along with
RAM 11 all being on the same integrated circuit chip. Associated
with RAM 11 is RAM control unit 12. A portion of the RAM, or all
of the RAM if desired can be powered by a standby voltage VsT.
Access to the RAM is controlled by a RAM enable signal supplied to
RAM control 12. The microprocessor contains clock, instruction
decode, and
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SC-78281
control circuitry 13 which is connected to an internal
microprocessor data bus 16 by way of an instruction
register 14. Instruction decoding control circuitry 13
receives several external signals which will be discussed
in greater detail hereinafter. Data is inputted and
outputted to the microprocessor by way of data buffers 17.
A condition code register 19 is coupled to arithmetic
logic unit 18 and indicates the results of arithmetic logic
unit 18. The results generated by condition code register
19 are in bit form and may be used as testable conditions,
for example, for conditional branch instructions. Program
counter 26 is a two byte (for example, 16-bits) register
that points to a current program address. Stack pointer 24
is a two byte register that contains the address of the
next available location in an external pushdown/pop-up
stack. The external stack is normally a random access
read/write memory that may have any location or address
that is convenient. The microprocessor also contains an
index register 23 which is a two byte register used to
store data or a 16 bit memory address for the inde~ed mode
of memory addressing. Microprocessor unit 10 contains two
8 bit accumulators 21 and 22 that are used to hold operands
and results from arithmetic logic unit 18. Program counter
26, stack pointer 24, index register 23, accumulators 21
and 22, and arithmetic logic unit 18 are all connected to
internal microprocessor data bus 16. Microprocessor
internal data bus 16 is also,connected to address or output
buffers 27. Sixteen output pins are used for the address
bus. Output or external data buffer 17 uses eight pins and
serves as a buffer for external data into and out of data
~8~
bus 16. Data bu~fer 17 is bidixectional! transferring data to
and from peripheral devices and external memories, if any. As
will be more apparent hereinafter data buffer 17 includes eight
individual buffers and its interface connections form an exter-
nal data bus for an external interface.
A complete schematic of microprocessor unit 10 without
RAM 11 and RAM control 12 can be found in U. S. patent 3,962,682
to Thomas H. Bennett~ U. S. patent 3,962,682 is assigned to the
same assignee as the present invention. Microprocessor unit 10
is a small computer with an 8 bit data word and 16-bit memory
addressing. Halt is an input to instruction decode and control
unit 13. When Halt is in a logical low state or "0" state all
activity in the microprocessor will be halted. Halt is level
sensitive. In the halt mode, the microprocessor will stop at
the end of an instruction, Bus Available will be in a high state,
and Valid Memory Address (VMA) will be in a low state. The
address bus which is connected to output buffers 27 will display
the address of the next instruction. ~ead/Write, (R/W), is an
output from control unit 13 and signals any peripheral units and
external memory devices as to whether the microprocessor is in
a read or write state. Read is a logic high level while write
is a logic low. The normal standby state of Read/Write is a
logical "1" or high state. Another output of control unit 13
is Valid Memory Address (VMA) which indicates to any peripheral
devices that there is a valid address on the address bus. In
normal operation, this signal should be used for enabling
SC-78281
peripheral interfaces such as a peripheral interface
adaptor (PIA) and asynchronous communications interface
aclaptor (ACIA). Another output of control unit 13 is a Bus
Available signal which is normally in a logical low state.
When the Bus Available (BA) signal is activated it will go
to a logical high state indicating that the microprocessor
has stopped and that the address bus is available. This
will occur if the Halt line is in a logical low state or
the microprocessor is in the WAIT state as a result of the
execution of a WAIT instruction. Interrupt Request (IRQ)
is a level sensitive input to control unit 13 which
requests that an interrupt sequence be generated within the
microprocessor. The processor will wait until it completes
the current instruction that is being executed before it
recognizes the request. Once the interrupt request is
recognized the microprocessor will begin an interrupt
sequence provided an interrupt mask bit in condition code
register 19 is not set. Data in index register 23, program
counter 26, accumulators 21 and 22, and condition code
register 19 are stored away in a stacked memory. The
microprocessor will then respond to the interrupt request
by setting the interrupt mask bit high so that no further
interrupts may occur. At the end of the cycle, a 15-bit
address will be loaded that points to a vectoring address
which is located in predetermined memory locations. An
address loaded at these predetermined memory locations
causes the microprocessor to branch to an interrupt routine
in memory. The Halt line must be in a logical high state
for interrupts to be recognized.
SC-78281
A Reset input to control unit 13 is used to reset and
start the microprocessor from a power down condition. When
'i the Reset input is in a logical low state the
microprocessor unit is inactive and the information in the
registers will be lost. If a logical high level is
detected on the Reset input, the microprocessor will begin
the restart sequence and all the higher order address lines
will be forced high. During the restart routine, the
interrupt mask bit is set and must be reset before the
microprocessor can be interrupted by Interrupt Request. A
Non-Maskable Interrupt (NMI~ signal is also inputted to
control unit 13. A low going edge on the Non-Maskable
Interrupt input requests that a non-mask-interrupt sequence
be generated within the microprocessor. As with the
lS Interrupt Request signal, the microprocessor will complete
the current instruction that is being executed before it
recognizes the Non-Maskable Interrupt signal. The
interrupt mask bit in condition code register 19 has no
effect on the Non-Maskable Interrupt request signal. The
Interrupt Request and Non-Maskable Interrupt inputs are
hardwire interrupt lines that are sampled when an enable
signal is in a logical high state and will start the
interrupt routine on a logical low enable signal following
the completion of an instruction. The enable signal is an
input to the control unit and supplies the clock for the
microprocessor unit and the rest of the system.
An Xtal and EXtal inputs are also provided for control
unit 13 and may be used for a parallel resonant fundamental
crystal to provide crystal control for an internal
oscillator. Control unit 13 also has a Memory ~eady input
SC-78281
signal which allows stretching of the enable signal. When
the Memory Ready signal is a logical high level, the enable
, signal will be in normal operation. When Memory Ready
signal is a logical low level the enable signal may be
stretched integral multiples of half periods thus allowing
interface to slow memories.
A RAM Enable input signal to RAM control unit 12
controls the on-chip RAM. When the RAM ~nable input signal
is a logical high state the on-chip memory is enabled to
respond to the microprocessor controls. The RAM is
disabled when the RAM Enable signal is in a logical low
state. As will be explained hereinafter the RAM Enable
signal can be used to disable reading and writing the
on-chip RAM curing a powerdown situation. The RAM Enable
signal should be in a logical low state three microseconds
before the power to the microprocessor unit goes below a
predetermined voltage level, such as 4.75 volts, during
power down. A standby power voltage, VsT, supplies the
DC voltage to the RAM as well as to the RAM control logic
12. If it is not desired or necessary for all of the
information in the RAM to be retained during a power down
condition the standby voltage need only be applied to that
portion of the RAM in which it is desired to retain data
during a power down condition.
Fig. 2 illustrates in greater detail some of the
circuitry of the system of FIG. 1. A portion of RAM 11 of
FIG. 1 is illustrated as memory 30. In an 8-bit word
system, memory 30 would contain eight columns of memory
cells 31. The eight columns would have one sense amplifier
41. Each memory cell 31 contains two inverters 32 and 33
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SC-78281
connected back-to-back. Data stored in memory cells 31 is
transferred to column sense lines such as 36 and 37 by
field effect transistor couplers 34. Couplers 34 are
enabled by signals appearing on row select lines 124 and
125. A memory array for an 8-bit word system would not
only have eight columns of memory cells 31 but would also
have a number of rows of memory cells, such as 16, and each
row would have a row select line such as 124 and 125.
Sense lines 36 and 37 are coupled to sense amplifier
41 by field effect transistors 38 and 39 respectively.
Transistors 38 and 39 are energized by a column select
signal appearing on line 40. Each column has its own
column select signal lines such as 40 and 45. The output
of cross coupled sense amplifier 41 is buffered by inverter
42. A read signal from logic NOR gate 73 enables field
effect transistor 43 which couples the output of buffer 42
to in~erter 44. The output from buffer or inverter 44 is
coupled by transistor 46 to line or conductor 47.
Transistor 46 is enabled by a synchronous timing signal
2Q from logic NOR gate 79. Line 47 is connected to one input
of logic NOR gate 48 while the other input of NOR gate 48
is connected to a timing signal. The output of NOR gate 48
goes to a control electrode of transistor 51 and to an
input of NOR gate 49. NOR gate 49 also receives the same
timing input signal as NOR gate 4B. The output of NOR gate
49 is connected to a control electrode of transistor 52.
Transistors 51 and 52 are connected in series between
voltage source VDD and reference ground. A buffered
output to the external data bus 53 is obtained from a node
formed by the series connected transistors 51 and 52. Thus
SC-78281
it can be seen that output data from the RAM can appear on
external data bus 53. Each 8-bit section of the RAM memory
'~ has its own data buffer and external data bus terminal.
The data out of the RAM carried by conductor 47 can also be
coupled to the internal microprocessor data bus 62 by
switching transistor 63 to a conductive state. Transistor
63 is controlled by an output signal from NOR gate 84.
Data bus terminal 53 can also receive input data for the
microprocessor. The input data is coupled by isolation
resistor 54, inverter buffer 57, clocked transistor 58 and
buffer/inverter 59. The input data is then controllably
switched by transistor 61 which is controlled by an output
signal from NOR gate 88. Data from internal microprocessor
data bus 62 can also be written into the R~M when
transistor 63 is enabled. When data is desired to be
written into the RAM, transistors 43 and 46, of course,
will not be enabled. Data appearing on line 47 is coupled
to a NOR gate by an inverter. The NOR gates are enabled by
a "write" signal and are coupled to the column sense lines.
The desired column sense lines can be enabled by signals on
conductors or lines such as 40 or 45. The column sense
lines are connected by pull-up transistors 126 to a voltage
line VDD so that the sense lines can be precharged.
The logic used to generate some of the read/write
commands and data buffer enabling signals will now be
discussed. A timing signal ~2' is coupled to control
electrodes of transistors 97, 98, and 99. An inverter 96
inverts the signal to transistor 98. Transistors 97 and 98
are connected in series between ground and VDD-
Transistor 97 is in parallel with transistor 99. The
-12-
output from transistors 97 and 98 i$ inverted b~v inverter 101
and connected to an input of NOR gate 102, The output also goes
to an input of AND gate 104. NOR gate 102 also receives a read
input, R, signal from NOR gate 73 and an input from AND gate 103.
Clock signal 02 and a read~write signal are supplied to the in-
puts o~ AND gate ]03. The read/write signal is also connected to
an input of AND gate 104. The output of AND gate 104 goes to
NOR gate 106. The output of NOR gate 106 is connected to an in-
put of NOR gate 84. NOR gate 84 supplies the enable signal for
switching transistor 63. Clock signal 02 appears on conductor 83
which is connected to an input of NOR gate 84. Conductor 83 also
provides the enable signal for transistor 86 and an input for
NOR gate 81. When transistor 86 is enabled it couples timing
signal BIDl to inverter 82. Inverter 82 supplies an input for
NOR gate 81 and the output of NOR gate 81 is an input for NOR
gate 79. NOR gate 79 supplies a synchronizing signal for trans-
istor 46 to enable the data out of the RAM to be coupled to the
output buffer. Timing signal BIDl is coupled to NOR gates 88
and 89 by transistors 92 and 93 respectively. Transistors 92
and 93 are enabled by clock signal or clock pulse ~2 which also
serves as an input signal for NOR gates 88 and 89. The output
of NOR gate 89 goes to NOR gate 106 and to NOR gate 78. The
output of NOR gate 88 goes to transistor 61 which couples input
data from external data bus 53 to the microprocessor internal
data bus 62. NOR gate 88 has a third input coming from NOR
gate 87, and NOR gate 89 also has a third input coming from in-
verter 77. The output of inverter 77 is coupled to inputs of
NOR gates 87 and 89 by transistors 91
3Q
- 13 -
SC-78281
and 94 respectively. Transistors 91 and 94 are enabled by
clock signal ~2.
RAM Enable signal, RE, is received into the RAM
control logic by inverter 64. The output of inverter
buffer 64 is coupled by transistor 66 to a latch having
inverters 68, 69 and transistor 71. Transistor 71 provides
feedback, from the series connected inverters 68 and 69, by
coupling the output of inverter 69 back to the input of
inverter 68. Transistor 71 is enabled by standby voltage
10 VST. An output is also taken from a node 70 formed by
inverters 68 and 69 and is used to enable transistor 114
and to provide an input to inverter 72. Clock pulse ~2 is
coupled by inverter 67 to transistor 66 to provide an
enable signal for transistor 66. It should be noted that
inverters 64, 67, 68, 69 and 72 are all powered by standby
voltage, VsT. The output of inverter 69 is the output
for the latch and goes to NOR gates 73 and 74 to be NORed
with other input signals to these NOR gates to produce the
read and write signals for the RAM. The write signal
appears at the output of NOR gate 74 and is inverted by
inverter 76. The read signal from NOR gate 73 goes to
inverter 77, NOR gate 78, and to transistor 43. The output
of the latch also goes to a control or gate electrode of
transistor 116 and to an input of NOR gate 117. Transistor
66 serves as a synchronous coupler coupling the RAM Enable
signal from buffer inverter 64 to the latch when transistor
66 is enabled by clock signal ~2. The output taken from
node 70 is coupled by inverter 72 to NOR gate 87 and to
transistors connected to row select lines of the RAM such
as transistors 122 and 123. Transistors 122 and 123 serve
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~ SC-78281
to discharge the row select lines and to hold these lines
at a low level or ground whenever the control electrodes of
the transistors are enabled by an outp~t from inverter 72.
The signal from inverter 72 is known as RAM Enable 2
(RE2).
Also illustrated in FIG. 2 is circuitry to generate an
Address Enable signal, AE. Four series connected inverters
llO, 111, 112, and 113 provide an input to NOR gate 117.
Clock signal 02 provides an input to the series of
inverters in addition to providing another input for NOR
gate 117. Clock pulse 02 is also coupled to an input of
NOR gate 118. The output of NOR gate 117 provides a second
input for NOR gate 118. Inverters llO, 111, 112, and 113
serve as a delay means for clock signal 02. The amount of
the delay provided by the inverters can be controlled to a
certain extent by varying the physical size of the
inverters. Of course, the delay can be further decreased
by decreasing the number of inverters or increased by
adding additional inverters. The clock signal 02 input to
118 is coupled through a transistor 114. Transistor 114
has its control electrode connected to the latch. The
purpose of transistor 114 is to open up the line that
carries clock signal 02 to NOR gate 118 when the RAM Enable
signal is not present. Transistor 116 is used to pull an
input of NOR gate 118, that normally carries clock pulse
~2, to ground. Transistor 116 is activated when the RAM
Enable signal is in a logic O" state. This en~ures a
logic "O~ input to NOR gate 118 when the RAM is not
enabled. The output of NOR gate 118 provides an Address
Enable signal which is connected to an address decoder
-15-
~ *~L SC-78281
depicted by NOR gates 119 and 121. It will be understood
that the address decoder represented by NOR gates 119 and
121 will have other address coded inputs besides the
Address Enable input.
When clock signal 02 is in a logic "1" state,
inverters 110, 111, 112 and 113 will provide a logic "1"
level input to NOR gate 117 since there are an even number
of inverters. Clock signal ~2 is already directly
connected to the input of NOR gate 117. This will mean
that NOR gate 117 now has two logic "1~ levels on its
input. The third input to NOR gate 117 will not have any
influence on the output of NOR gate 117 and therefore its
output will be a logic "on. This logic "0" appears on one
Gf the inputs of NOR gate 118 and the other input of NOR
gate 118 is clock pulse ~2 which was assumed to be a logic
"1" level. Transistor 114 will be in a conducting state as
long as the RAM Enable signal present at the input of
inverter 64 is a logic "ln. The inputs of gate 118 being
logic "l's" will cause a logic "0" at the output of NOR
gate 118 and therefore does not serve to inhibit the
address decoder.
At the trailing edge of clock pulse ~2 the directly
connected input to gate 117 will go to a logic "0" level
while the input coupled by the delay means will remain at a
logic "1" level for a predetermined period of time equal to
the amount of delay provided by sequential inverters 110,
111, 112 and 113. Therefore the output of NOR gate 117
which is connected to NOR gate 118 will remain at a logic
l0" level for the predetermined period of time, and the
other input to NOR gate 118 which is directly connected to
~ SC-78281
the cloc~ pulse ~2 will become a logic "0" level thereby
producing a logic "1" level at the output of NOR gate 118.
This positive or logic "1" output is connected to the
address decoder and serves to inhibit the address decoder
for a period of time equal to the delay of inverters
110-113. During the short period of time that the Address
Enable signal inhibits the address decoder the row select
lines are held in a logical low state. This helps to
alleviate the problem of charge splitting and coupling,
which is sometimes called pattern sensitivity, caused by
the address code changing at the input of the address
decoder. Otherwise, the previous signal on the sense line
could tend to change the state of the next address memory
cell. During the time that the address decoder is
inhibited, the sense lines are pulled up to a logic level
"1" by pull up devices 126. Inhibiting the address decoder
at the trailing edge of clock pulse ~2 also alleviates the
multiple select/deselect problem which is caused by the
overlapping of signals on the row select lines. Such
overlapping can cause a new cell to be selected prior to a
previously addressed sense line being completely
deselected. The multiple select/deselect problem could
also be caused should one decoder gate change outputs
faster than another decoder gate which would cause a
momentary erroneous address.
Since the RAM is on the same integrated circuit chip
where the address is generated, process variations cancel
each other out If process variations should tend to make
the addressing circuitry slower, then of course, the
sequential in~erters 110, 111, 112, and 113 will then
~ SC-78281
provide a longer delay and vice versa. The length of the
delay provided by the sequential inverters should be at
least equal to the time it takes an address signal to get
from the address registers to the RAM address decoder. The
important thing is to produce a pulse which is long enough
to block out undesired address pulses, and as indicated
hereinbefore one way of accomplishing this is by selecting
the proper number of gates or inverters.
Just prior to a power down condition the RAM Enable
signal and the clock pulse ~2 are commanded to a logic "0"
state. This causes a logic "1" level to appear at the
input of inverter 68 since synchronous coupler 66 is
enabled by the logic "1" level coming from inverter 67.
The output of inverter 69 will also be a logic "1" level
and is coupled back to the input of inverter 68 by feedback
coupling means 71. The logic "1" level from inverter 69 is
connected to the inputs of the read and write logic gates
which serves to inhibit the read and write logic circuitry.
This prevents any information from being read into or out
of the RAM in a power down condition. The output of
inverter 68, which will be a logic "0" level, disables
transistor 114 whereas transistor 116 is enabled by the
output of inverter 69 thereby causing the input to NOR
gate 118 to be a logic on. The logic "1" on the output of
inverter 69 is connected to an input of NOR gate 117
thereby causing NOR gate 117 to produce a logic "0" level
output. The two logic "0's" on the input of NOR gate 118
causes its output to be a logic "1" thereby inhibiting the
address decoder. The output of the address decoder pulls
the row select lines to a ll0" level. The output of
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SC-78281
inverter 68 is also connected to an input of inverter 72.
The output of inverter 72 produces signal RE2 which, as
stated hereinbefore, activates transistors 122 and 123
further ensuring that the row select lines remain in a "0"
state.
Fig. 3 better illustrates the action of RE2 upon the
row select lines. As shown in FIG. 3 transistors 142
perform the same function as the transistors illustrated as
122 and 123 in FIG 2. It should be noted that transistors
10 142 are located at each end of the row select lines which
therefore cause the row select lines to be pulled down to a
"0" level at each end while the address decoder 144, which
is connected to the midpoint of the row select lines, pulls
the midpoint down to a "0" level. FIG. 3 illustrates eight
15 different 8-bit groups of memory cells in the RAM. The
eight groups are 131, 132, 133, 134, 135, 136, 137, and
138. Group 131 is shown in greater detail than the other
groups. ~ plurality of memory cells 130 make up group 131.
Each cell 130 is connected to address decoder 144 by row
20 select lines 141. Row select lines 141 are coupled to a 0
volt reference or ground conductor 143 by transistors 142.
The control electrodes of transistors 142 are connected to
lines 147 and 148 which carry the RE2 signal. The sense
amplifier 146 of group 131 is coupled to selectable sense
25 lines by conunand of signals Y0 through Y7.
In FIG 4A, a single integrated circuit chip 150
contains microprocessor unit 10 and RAM 11. The RAM
read/write control and interface logic 153 and data bus
buffers 154 are shown in block diagram form. Data bus
30 buffers 154 are connected to RAM 11 by line 155. The data
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SC-78281
bus buffers are also capable of receiving and sending
information to the microprocessor internal data bus.
Various of the timing signals required for RAM read/write
control and interface logic 153 are indicated as inputs to
logic 153. FIG 4B shows a block diagram of a portion of
FIG. 4A in a little greater detail. RAM read/write control
interface logic 153 includes RAM read/write logic 158 and
read/write logic 159. Data bus buffers 154 are connected
to RAM cell sense amplifier 157.
By now it should be appreciated that there has been
provided an on-chip RAM from which data can be outputted
directly on to the internal microprocessor data bus. In
addition RAM retention is accomplished during power down
and power up conditions and an address inhibit signal is
applied to address decoder during a period of time
immediately following an addressed access to the RAM.
Consequently, while in accordance with the Patent
Statutes, there has been described what at present are
considered to be the preferred forms of the invention, it
will be obvious to those skilled in the art that numerous
changes and modifications may be made herein without
departing from the spirit and scope of the invention, and
it is therefore aimed in the following claims to cover all
such modifications.
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