Note: Descriptions are shown in the official language in which they were submitted.
16
1 P~N 8989
The invention relates to a word-organized, con-
tent-addressable memory, comprising a first input for
inputting a key word, a second input for inputting a mask
word for the selective deactivation of a part of the in-
put key word by masking, an output for outputting a dataword stored in a word location, first means for comparing
a non-masked part of a key word with a corresponding part :~
of a data word stored in a word location, and second
means for indicating, per word location, correspondence
detected by said first means and for activating said out-
put for outputting data from a word location for which
correspondence occurs. A memory of this kind is already
known from the article by J. Barlett et al, Associative
Memory Chips: fast, versatile and here, Electronics
(700817) pages 96 - 100, for example, the memory 4102 by ~;
Fairchild Semiconductor Corp. described on page 97 which :
comprises four words of four bits. For these 16 bits,
the integrated circuit of said memory comprises twenty-
four connection pins, i.e.:
a) four connections for an address, so that the data can
also be addressed in the manner of a random access
memory (RAM);
b) four connections for a descriptor word which indicates
the keyword; .
c) four connections for enable data, i.e. concerning the
2 PHN 8989
mask word; the bit locations masked by the mask word
are not taken into account for the comparison;
d) four connections for a correspondence signal, i.e.
each time one for each separate word;
e~ four connections for the parallel-wise output of the
data of a four-bit content word;
f) one connection for a so-termed inverted correspond-
ence signal;
g) one connection for a write enable signal;
h) two current connections; 50 in total 24 connections.
The number of connection pins per data bit stored is
calculated as (5n + 4) : n2 for a square matrix of n x n
bits, which is comparatively high; on a matrix compris-
ing 40 connection pins, at the most 7 x 7 bits could be
accommodated. The invention has for its object to reduce
the number of connec~ion pins required for a content-
addressable memory of the described kind, while maintain-
ing a high degree of flexibility in the use and`easy con-
trol in comparison with the known memory. The objects ~ -
~0 in accordance with the invention are realised in that
said second means comprise a validity indicator per word
location, having a position "valid" and a position
"invalid", for selectively indicating the validity of
the word stored at this location, and per word location
a correspondence indicator, having a position "corres-
pondence" and a position "non-correspondence", said val- ` -;
idity indicator acting as a bit position of the associ-
ated word location, so that when the memory is addressed ~
as regards valid word location content, said position `
"invalid" blocks the associated correspondence indicator
for the effective supply of a signal "correspondence",
each validity indicator comprising a switch input for
selectively setting the indicator, by an externally
applied switch signal, to the one or to the other posi- ;
tion. Thus, first of all a number of address pins can
be eliminated. Elimination can be understood as follows: `
the validity indicator indicates whether a word location
contains valid data. When the validity indicator is set
3 PHN 8989
to "invalid", a memory word can be quasi erased without
the physical address of the relevant memory word having
to be externally known; therefore, it need not be stored
elsewhere either. The invention in this respect is
based on the idea that the physical address of a word
per se is of no importance to a user. As a result of
the associative searching of a validity indicator which
is in the position "invalid", an available "free" word
location is found. Again external physical addressing
is not required.
Preferably, third means are provided for vac-
ating a part of the memory and for switching, under the
control of a correspondence signal from the correspond-
ence indicator of one or more word locations, the valid-
lS ity indicator of said one or more word locations to theposition "invalid". Thus, the vacating is controlled by
the data of a word rather than by the physical address
thereof. This results in simpler control, because said
physical address need not be externally known for this
purpose.
Preferably, there is provided a multiple match
-resolver for forming, in the case of the simultaneous
appearance of at least two active i'corresponding" sig-
nals, a sequence for the treatment of the associated
word locations, while for the writing of a data word in
a word location, exclusively the bit position corres-
ponding to the data of the validity indicator remains
unmasked by the mask word in order to control, in the
position "invalid", the associated correspondence indic-
30 ator so as to form a position "correspondence`', after i
which the multiple match resolver controls a write
enable signal for a single word location thus provided
with a correspondence signal. Thus, if a plurality of
word locations contain only invalid data, a sinyle word
location thereof can be readily filled with new data.The physical address again need not be externa~ly
known.
Preferably, fourth means are provided for
9(~6
4 PHN 8989
switching, under the control of a sequence signal from
said multiple match resolver, the correspondence indic-
ator for a word location indicated by said sequence sig-
nal to the position "non-correspondence" in order to
apply, when a read command signal is received, the data
of a word location to said output only once. This
results in the attractive additional function of the
sequential reading of a number of corresponding words
only once, which is performed by the already provided
correspondence indicators.
Preferably, there are provided fifth means
for writing, under the control of an operational corres-
pondence signal from a correspondence indicator, pre-
determined data for the bit positions of the relevant
word location which are not masked by the prevailing
mask word, said fifth means furthermore being adapted
to simultaneously write predetermined data, under the
control of simultaneously appearing effective corres-
pondence signal from the correspondence indicators of
at least two word locations, for the bit positions of
the relevant word locations which are not masked by the
mask word then prevailing. The data of a single word
or of a number of words (each time containing the same -
data, however) can thus be readily updated.
Preferably, there is provided a mask register
for a mask word whose non-masked data location (loca-
tions) bit-wise activate(s) said first means and whose
masking data locations bit-wise activate said output.
The mask often remains unmodified for a number of suc
30 cessive memory operations. As a result of the double ~`
use of the output signals of the register, the control
of the memory is simplified.
The memory, constructed as an integrated cir-
cuit, preferably comprises a mask register for a mask
35 word whose outputs are connected to said first means,
said first input, said second input, said output, and
an input for the input of a data word to be stored in
a word location being connected together, via pins which
X '~:!
/ I
PHN 8989
are common per bit position, to a data bus line. As a
result, a small number of connection pins suffices, as
will be described in detail hereinafter. This is part-
icularly advan~ageous for the manufacture of integratea
circuits. It will also be obvious that the number of
connection pins can be further reduced in known manner
by utilising serial data transport. This technique can
be applied separately as well as in combination with
the described steps.
Furthermore, there is preferably provided a
separate integrated circuit for the storage of n data
words of m bits plus an associated mask word of corres-
ponding length, said separate circuit comprising, in
addition to m connections to said bus, n connections
which are each associated with a separate word and which
serve for a correspondence signal per word, and also
power supply terminals as external connections, at least
three connections for receiving mode selection signals
in order to activate a decoder in the circuit, and also
a connection for receiving a clock signal. Thus, a
large number of functions can be performed within the
integrated circuit, while only a limited number of exter-
nal connections (pins) is required in comparison with the
number of n x m data bits stored in the circuit.
Furthermore, said n connections are preferably
suitable for transporting a correspondence signal from ~-
said circuit as well as a pointer signal to said circuit, ~;
said n connections comprising a unidirectional element
each, provided with a control terminal for alternatively -~
determining a conducting direction therein, the control
terminals of the n unidirectional elements all being
interconnected in order to form together a single further
external connection of said circuit. As a result of such
a singlé additional connection, double use can be made of
a single connection per word location and the integrated
circuit has many facilities while the number of external
connections is limited.
The invention will be described in detail
.. . . . . . .
6 PHN. 8989.
hereinafter with reference to the accompanying diagrammatic
drawing.
Fig. 1 shows a circuit diagram of a word-
organi~zed, content-addressable memory.
Fig. 2 shows a diagram and the necessary connec-
tions.
Fig. 3 shows the set-up of a memory word location
with Fig. 3a showing a time diagram of waveforms appearing
on the outputs of the switching elements and Fig. 3b show-
ing the forward and return transport via the interface line
for the operating mode SR.
Fig. 4 shows the electronic construction of a
memory cell.
Fig. 5 shows a control element.
Fig. 6, which is on the same sheet as Fig. 4,
shows a memory organization.
Fig. 1 gives an elementary idea of the operation
of a content-addressable memory. In this example, each of
the actual memory words in the memory 30 contains 16 bits.
These words contain a keyfield 33, in this case consisting
of ten bits, and a data field 34 which in this case con-
tains six bits. For comparison with the actual content of
the memory words, a keyword 35 of ten bits is applied, the
position thereof corresponding to that of the key field.
Finally, there is present a mask word 31 comprising ten
bits whose position corresponds to that of the key field.
The bits of the mask word have a first value (in this case
1 for the bits in the word section 32) or a second value
tin this ca9e 0). Only the bits of the key word whose
positions correspond to mask bits of the first value are
taken into account for the actual comparison. Outside this
actual key field, data of indefinite value (don't care~ in
practice are applied for comparison. If the data content
of the bits of the key word 35 which are not masked by the
mask word 31 corresponds to that of the corresponding bit
positions of a word stored in the content-addressable memory,
a correspondence or match signal is reserved for the rele-
vant. word. This correspondence signal is applied to a user
device not shown. If desired, this device can have at its ;
disposal the data of the data field of the relevant memory
word. The foregoing des-
.
. . . ~ , .
~L89~
7 PHN 8989
cription was given merely by way of example. The wordlength may be different. The data content of the mask
word is arbitrary. Furthermore, the distinction between
key field and data field may be absent, so that in the
case of correspondence all bits that were masked during
the content-addressing of the memory become available
as data bits for a user. Notably in that case, an in-
definite value may be applied for comparison for all
masked bit positions. This can be realised by way of
an output stage which is capable of supplying a logic
"1", a logic "0" as well as a high output impedance (so-
termed tri-state buffer). Furthermore, for cases of
correspondence for a plurality of word locations, the
associated data bits being required elsewhere, a device
may be provided for forming a sequence for the word loc-
ations to be addressed. Such a sequence determining
device is known per se from an article by G.A. Anderson,
Multiple match resolvers", I.E.E.E. Trans. Computers
C-23 ~7412), 1317. If only a single word location is to
be addressed in the case of multiple correspondence, a
device of this kind thus acts as a priority determining
device. If a plurality of word locations are to be
addressed, a device of this kind acts as a sequence gen-
erator (sequencer). For logic and electronic details,
reference is made to the following figures.
Fig. 2 shows a number of connections required
for a matrix 50, comprising 4 x 4 bits, to be used in a
content-addressable memory. Per bit position column
(denoted by dotted line) there are each time provided a
data input 151, 53, 55, 57), a mask bit input (52, 54
56, 58) and a data output (67, 68, 69, 70). Per word
row (denoted by dotted line) there are each time pro-
vided a signalling line (60, 62, 64, 66) and a word ~-
selection line (59, 61, 63, 65). The signalling lines
serve each time for outputting a correspondence signal
per word row. The selection lines serve each time for
selecting a predetermined word row. Furthermore, there
X
,. : .
90~
8 PHN 8989
is provided a four-bit bi-directional connection 73 to
the environment. The element 71 is a four-bit mask
register which is capable of storing mask data under
the control of an external load signal on the input 76.
The element 72 is an input/output stage which is con-
trolled by the relevant signals on the lines 74, 75.
The actual memory matrix comprises 5n connections for
this n x n organization (the connections for power sup-
ply are not shown). The embodiment of a content address-
able memory yet to be described may have the following
operating modes:
a) associative searching and reading of the content of
a word for which correspondence occurs (R);
b) reading the next word of a sequence of words for
which correspondence occurs (SR = sequential read);
c) loading the characteristic mask word in ~he mask
register (LM = load mask);
d) selective invalidating of the content of one or more
predetermined word locations (CPM = clear part of
memory);
e) writing in a free word position, i.e. one not con-
taining valid data (WFP = write free position~;
f) writing data in a selective number of bit positions ;`
of a word or number of words simultaneously if cor-
respondence occurs for this word or these words
(WP = write parallel).
These 5iX operating modes may be defined with- -
in the space of a three-bit operation code (opcode), two
free codes remaining within three bits, if necessary.
One of these two codes could be defined as "restore the
position o~ the selection indicating data", which indic-
ates the next word to be read sub b) so that, for exam-
ple, a predetermined number of words of a selection is
indicated ~CP = clear pointer).
- The number of connections of the integrated
circuit can be reduced by centralising the control and
by combining the data connections. First of all, the
circuit shown in Fig. 2 comprises a four-bit mask reg-
'~
,
':
9o~
g PHN 8989
ister 71 for this purpose. In the case of a series ofcontent addressing operations, the key word will change
in many cases, while the mask word remains the same.
The data stored may concern, for example, an identific-
ation and a number of variables per identification (forexample, a product number and quantity of stock). In
that case, a search is made each time on the basis of
an identification which usually contains the same bit
positions which comprise, for example, the field with
the product number, when the stock is successively up-
dated for a number of products. The circuit shown in
Fig. 2 furthermore comprises a data multiplexer 72. Per
bit position, this multiplexer has a first input con~
nected each time to a corresponding input of the mask
register 71, and a second output is connected to a
corresponding data input of the matrix. Finally, per
bit position the multiplexer 72 has an input connected
to a data output of the matrix, each bit position also
being connected to a bit line of the bidirectional data
BUS line 73. The multiplexer has three operating modes
and receives a two-bit control signal on the lines 74,
75 for this purpose. The mask register 71 has two oper-
ating modes (loading, not loading) and receives a one-
bit signal on line 76 for this purpose. The control
will be described in detail hereinafter.
Fig. 3 shows the logic set-up of a word loc-
ation in a content-addressable memory, and also the
control provided for one word location. The dotted line
82 represents the separation, to be discussed herein-
after, between storage circuits and control circuitswhich are to be arranged in modular form. The word loc-
ation first of all comprises the actual bit positions
36 which per bit contain a circuit, to be elaborated
hereinafter, for selectively executing the operations
reading, writing and comparison per bit. The number of
bit positions 36 does not form a restriction for the
invention. The input 37 for key/mask and data and the
output 38 for data are diagrammatically shown. When
,, . 1 -
3906
PEIN 8989
addressing according to content, in the case of correspon-
dence a signal Ml appears as a logic "1" on an output
which is connected to the word location. Furthermore, per
word location there are two additional bit positions (39,
42) which are constructed as flip-flops. Furthermore, a
part of a multiple match resolver is assigned to the rele-
vant word location as will be explained hereinafter. In
the flip-flop 39, a "validity" of "fill" bit is stored.
This bit has the value 1 if valid data are stored in the
relevant word location. In the opposite case, a logic
"0" is stored in this word location, which thus blocks the
AND-gate 45, so that the output signal thereof remains
logic "0", independent of the value of the signal Ml
transported via the interface line 82. The flip-flop 39
comprises a set input 41 and a reset input 40. The set
signal on 41 appears under the control of the signal of
the previously described operating mode WFP (write in a
free word position), which may be common to a number of
word positions, in cooperation with a pointer signal P on
the line 83 which may have the value "1" for at the most
one word position. The AND-gate 84 supplies, co-control-
led by a clock pulse on the input ~ a logic "1" only if
WFP = P = 1, the flip-flop 39 thus being set to the "1"
position. The rest position of the flip-flop 39 is ~ormed
25 by the "0" position in which the word location does not ~'
contain valid data. The pointer signal P on the line 83
is formed by the OR-gate 99 which in that case receives
a signal from AND-gate 94 (the signal WP is low, so that ~;~
the AND-gate 98 supplies a logic "0"). The AND-gate 94
forms part of the sequence generator as will be described
hereinafter. Simultaneously with the described operations, ~ ~-
the data received on the line 37 are stored in the word
position 36. To this end, the input 89 receives a low
signal whereby transmission elements 87 and 88 are con-
trolled to conduct by way of the inverters 92 and 93.Moreover, this low signal drives the data flip-flop 141
to the hold position.
During a previous operation, a search action
': : , ;, ....
, ~ : .
ll P~IN 8989
has been performed for which only the inverted value of
the validity bit has been taken into account in that said
signal WFP is combined with the signal on the zero output
of the ~lip-flop 39 in the AND-gate 95. The entire data
field is then masked, so that none of the word positions
supplies a signal Ml having the value "l". In other
cases, the inverted value of the signal WFP can also
block the AND-gate 45. Controlled by the signal WFP, the
output signal across the AND-gate 95 reaches, as the sig-
10 nal M2, the OR-gate 80 and the AND-gates 46, 49 and 96,
via the OR-gate 86. The AND-gates 49 and 96 are blocked
in that the signals SR and CPM have the value "0". The
flip-flop 42 is then in the "1" position. Thus, the AND-
gate 46 also supplies a logic "l". All word positions
without valid data thus supply the signal M = 1. Input
81 is connected to an output of the directly preceding
word. Output 140 of the OR-gate 48 forms this output for
the word considered, so it is connected to the relevant
"81" input of the directly subsequent word. The sequence
of the woxds is determined, for example, by the geometry
of the circuit. The first word of the sequence receives
a logic "0" on its "81" input. For the one word position
for which the input 81 receives a logic "0" and for which,
moreover, the signal M=l, the AND-gate 94 supplies a logic
"1". The latter "1" acts as a pointer signal which remains
valid for a sufficient period of time, i.e. as long as
is required for the signal on the input 89 to change from
the value "0" to the value "1". The output of the gate
94, or on the other side of the OR-gate 99, may comprise
a monostable multivibrator (not shown) having an astable
period of, for example, one clock pulse period, when the
signal on the line 89 changes to the other value after
one clock pulse period (or slightly sooner). Fig. 3A
shows a time diagram of these occurrences, the waveforms
shown being those appearing on the outputs of the switch-
ing elements. The arrows indicate the causal connections.
On the other side, the reset signal appears on ~-
the line 40 of the flip-flop 39 under the control of the
.~
390~i
12 P~N 8989
said operating mode CPM tin the case of correspondence
with a predetermined non-masked, key word, sets part of
the memory to "free"~, in cooperation with the output
signal M2 of the OR-gate 86 and a clock pulse on input
~. The signal of the gate 86 originates from the gate
45, because the signals WFP and CPM do not both have the
value "1". By combination of the three said signals,
the AND-gate 96 then supplies a reset signal for the
flip-flop 39. Contrary to the already described situa~
tion in the operating mode WFP, the data of all word
locations for which correspondence exists can now be
"invalidated" together. This is effected for all word
locations which supply a signal M1 = 1 upon comparison
with a non-masked key field. When the signal on the line
89 has a high value, the transmission elements 90 and 91
conduct, and the transmission element 87 and 88 are block-
ed. The data flip-flop 141 then also acts as a trans-
mission element. The elements 91 and 141 may be joined
into a single data flip-flop. When suitable steps are
taken, for examplè, by introduction of suitable thres-
hold values for the control inputs of the transmission
elements, it is ensured that the signals to be conducted
by the elements 87, 91 originate exclusively from the
elements 88 and 90, respectively. For the remainder, the
position of the flip-flop 39 remains the same. Even
though this is not shown as such in Fig. 3A, the signal -`
on the terminal 89 may be tri valent (O, 1), terminated by
a high impedance), none of the elements 87, 88, 90, 91
conducting in the case of the third value.
A correspondence or match bit is to be stored
in the bit location 42. This bit has the value 1 if a
correspondence signal is permissible in the relevant word `
location; it is only in that case that the AND-gate 46
is conductive for the output signal M2 conducted by the
element 86. The signal M is thus formed on the output
47, with the result that the memory functions to be -
effected in the case of correspondence are released. The
flip-flop 42 is normally in the "1" position, which indi-
'
X ':
,
,
9~
13 PHN 8989
cates that, when correspondence is detected (signal M2),
the content of the relevant word location may be used. If
this flip-flop 42 is in the "0" position, the re]evant
word location is out of use, notably because the relevant
word location has already been read out during the read-
ing of a series of words. The flip-flop 42 comprises a
set input 44 and a reset input 43. The reset signal on
the line 43 appears, co-controlled by a synchronizing
clock signal on the terminal ~, if all three following
conditions are satisfied:
1) a signal prevails which controls the reading of a next
word of a sequence of (at least one) words for which
correspondence occurs (SR);
2) no correspondence signal M of a word of higher rank
is present, so that the input 81 receives a logic -
"0";
3) the signal M2 has the value "1" for the relevant word.
These four signals are combined by the AND-gate 49
which can be blocked, via an inverted input, by a
signal from the directly preceding word on the input
81.
During the sequential reading of a number of
word locations, the flip-flop 42 of each time a next
corresponding word is set to the "0" position, so that
each time the above condition 2) is satisfied also for
a further word of the correspondence sequence. If (see ~ `
above) instead of the command SR, however, the command
R is givenr the above three conditions are not satis-
fied and the position of the flip-flop 42 remains the
same. According to this possibility, the same word may
then be read an arbitrary number of times. In the case
of an instruction SR, a number of word locations can
initially supply a signal M=1. The output signal of the
gate 94 (prior to the said resetting of the flip-flop ~;`
42) can then activate, after conduction by the elements
88, 87, controlled by the low value of the signal on the
terminal 89 as described for the operating mode WFP, the
word position 36 in order to read the data on the line
. . .
;. .
g~6
14 PHN 8989
38. Fig. 3b shows the forward and return transport via
the interface line for the operating mode SR. The non-
interrupted lines denote the reading of the first word
of a sequence, the broken lines denoting the reading of
the relevant word as if this word were not the first one
of a series. Contrary to the foregoing, use can also be
made of a known multiple-match resolver sequence gener-
ator.
In this case, the set signal on the line 44
appears, possibly co-controlled by a clock signal, if
at least one of the following conditions is satisfied:
1) no correspondence signal is present on the output of
the gate 86; therefore, there is either no corres-
pondence signal from the flip-flop 141 when the flip-
flop 39 is in the "1" position, or there is no command
WFP when the flip-flop 39 is in the zero position.
This rest position thus automatically occurs when a
new key word is applied for which no correspondence
tMl) exists and also when the data of the relevant
word location are invalidated;
2) an additional signal LM is applied which controls the
loading of a mask word in the mask register. When a
new mask word is applied, all word locations are
available again for outputting their data; ;~
3) an external signal WP is applied which controls the
parallel writing in one or more word locations. In -~
that case all word locations must again be available `
for outputting their data. These cases are effectu~
ated by the OR-gate 80, comprising one inverted input.
The circuit shown is given by way of example. `~
The control signals WFP, COM, WP, LM, SR can be obtained `~
as output signals from a decoder (not shown) which
receives a three-bit code. The time diagrams loaded
during the execution of the commands SR, R, WP and LM,
are not separately shown, because they exhibit onl~
small time-sequential differences as a result of the sub-
stantial correspondence in the signal path wikh the com-
mands WFP and CPM.
~r
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O~
P~IN ~989
Fig. 4 shows an embodiment of a memory for use
in a content-addressable memory in accordance with the
invention. The memory cell comprises ten external con-
nections 1 - 10, and twelve n-MOS transistors 11 - 22.
The line 8 is connected to a supply voltage VDD of, for
example, approximately 5 V and the line 10 is connected
as indicated to earth potential. Contrary to the other
transistors, the transistors 13, 14 drawn slightly dif-
ferently are depletion transistors: they are also con-
ductive in the case of a zero voltage difference betweengate electrode and source electrode. The other trans-
istors, being enhancement transistors, are drawn slightly
different again. In the case of a voltage difference
zero between gate electrode and source electrode, these
transistors are blocked. The lines WL and MA are common
to the bit cells of a word, the vertical lines connect-
ing corresponding bit cells of a plurality of words. The
transistors 11 - 14 constitute a hold circuit for 1 bit
as a result of their feedback~ The cross-wise connection
between the transistors 12 and 13 then carries the sig-
nal X which indicates the state of the hold circuit. The
cross-wise connection between the transistors 11 and 14 ~`
carries the inverted value X thereof. The line pair 1/4
carries the signals Al, A2. In the rest condition, these
two signals are both logic "0", with the result that the
transistors 19, 22 are blocked. This state thus corres-
ponds to the relevant cell being masked for associative
searching. In the active state, the signal Al briefly -- -
assumes the value A, whilst the signal A2 briefly assumes
the inverted value A, as will be explained hereinater.
The line pair 2/5 carries the signals B, B which normally
have opposed values. The lines 3/6 both carry the same
signal S. In the case of associative searching, a signal
source (not shown) applies a signal WL having the value
0 on the line 9 (the value 0 being at the most some tenths
of a volt), the signals B, B, S on the lines 2, 3, 5, 6
having an arbitrary (don't care) value. A logic value
"1" then corresponds to a voltage level which is at the
X , "~
- .: . . . .
,., ..,. , . , "
~, , '1, .. .
06
16 PHN 8989
most a few tenths of a volt lower than the value 5 volts.
The signal WL = 0 is generated by a circuit which acts as
a clock pulse generator which does not necessarily have a
constant frequency. In the above case, generally all
word locations are thus activated. Furthermore, during
associative searching, the key bit A is applied on the
line 1 and simultaneously therewith the corresponding
inverted value A on the line 4. If Al = 0, the transis-
tor 19 remains blocked; iE A2 = 0, the transistor 22
10 remains blocked. If Al = 1, the transistor 19 can con- `
duct. If X = 0, the series connection 9 of the transis-
tors 19 and 20 is blocked. In the latter case, A2 = 0
and X = 1 for associative searching, so that the series
connection of the transistors 21 and 22 also remains
blocked. The line MA is charged to a high voltage by a
transistor not shown, and this logic state is maintained
subject to the condition that for the relevant bit cell
Al = A = X and A2 = A = X. On the other hand, if Al ~ X
and hence A2 ~ X during associative searching, one of the
20 two series connections of the transistors 19/20 and 21/22
is conductive, so that the line 7 carrying the signal MA
is discharged. In the case of correspondence of the two
data, the line MA thus maintains its high voltage. The
line MA is each time common to all bits of a word. It is ! "
only when correspondence occurs for all bits of this word
which are taken into account in the comparison with the
relevant key bits that the line MA of this word remains
at a high potential, so that the signal Ml of Fig. 3 has
the value "1". If at least one bit compared does not
correspond, the line 7 is discharged and the signal Ml
assumes the logic value "0". In the foregoing, the trans- ;~
istors 20 and 21 are controlled by the output signals of
the hold circuit, so that the data content of the hold
circuit remains the same. The line 7 can also comprise
one signal amplifier (not shown) for the entire word in
order to increase the response time; amplifiers of this
kind are known.
In the case of a write operation, the follow-
.: -. , ,
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906
17 PHN 89~9
ing pattern is generated by signal sources not shown.
The lines 1 and 4 continue to carry a low signal
(Al = A2 = 0), so that the transistors 19 and 22 are
continuously blocked. The lines 9 (signal WL), 3 and
6 (both signal S) all carry a high signal. Via lines
2 (si~nal B) and 5 (the inverted signal B), the desired
data are applied. The series connections of the trans-
istors 19/20 and 21/22 are thus blocked in this case,
while those of the transistors 15/16 and 17/18 are con-
ductive. The data of X and X then correspond to thoseof B and B, respectively. The write phase is terminated
in that the signal WL becomes low, with the result that
the inputs of the hold circuit are isolated from the
signals B, B. Isolation can also be realised in that -
the signal S becomes low on the lines 3, 6. The sig-
nals S and WL may alternatively both become low, certain
timing tolerances in this transition being permissible.
In the case of a read operation (R, S~), the
content must be signalled to the outside per bit cell.
The lines 1 (signal Al) and 4 (signal A2) then carry a
low signal. Subsequently, the lines 2 (signal B) and ~ ;
5 (signal B) are both charged to a high voltage by rele-
vant transistors ~not shown) in the same manner as des-
cribed for the line 9 (signal WL). Subsequently, the
lines 9 (signal WL) and 3/6 (signal S) are activated by
a high voltage. As a result, the series connections of
the transistors 15/16 and 17/18 become conductive.
Depending on the data content of the hold circuit, one
of the two transistors 11, 12 will then be conductive. -
For the relevant transistor a conductive series connec-
tion is thus formed of three transistors, so that only
one of the two lines 2, 5 is discharged. In this case
reading is non-destructive as a result of the symmetri-
cal control. Moreover, when the charging transistors
for the lines 2 and 5 are properly proportioned, only a
limited control charge is available and the hold clr-
cuit is stable for such a small disturbance.
The lines 3/6 (signal S) have the following
18 PHN 8989
function. A write operation can take place in two situ-
ations
a) data are to be written in a single available word
location, the full word length being utilized by
complete deactivation of the mask word. The signal
S then obtains the va]ue 1 for all bit positions of
the word;
b) data are to be written in each time the same field
of each of a number (~l) simultaneously addressed
word locations, i.e. writing each time in a key field.
The signal S then assumes the value l only for the bit
positions of said field.
In the case of a read operation in a single
word location, or successively in a series of word loc-
a ions, the value of ~he signal S is made 1 only for the
bit positions outside the key field. The selective con-
trol of the lines 3, 6 by way of the signal S will be
described with reference to Fig. 5.
In order to execute the operation "write par-
allel" (WP), the logic values A and B are on the one
hand made equal inside the integrated circuit, while on
the other hand those of A and B are also made equal.
The implementation will be described with reference to
Fig. 5.
Fig. 5 shows a circuit for generating a num-
ber of control signals as described in the foregoing. ~
The circuit is suitable for controlling one bit posi- ~;
tion per memory word. For a word length of n bits in
a storage circuit of the relevant memory, the circuit
shown in Fig. 5 should be included n times in this
storage circuit. The figure shows a bidirectional data
connection 101, six control connections LM, ~, SR, CPM,
WR, WRP, whose meaning has already been described, and
five data outputs Al/ A2, B, B, S for controlling cir-
cuits as shown in Fig. 4. The circuit furthermore com-
prises a mask register 103 for one mas~ bit, three line
activation elements 113, 114, 115, four AND-gates 102,
104, 106, 111, four OR-gates 105, 107, 108, 116, an ~
.
0~
19 PHN 8989
inverter 109, and an E~CLUSIVE-OR-gate 110. I'he circuit
100 is a one-bit input buffer, while the circuit 112 is
a one-bit output buffer. The latter supplies a tri-
valent signal, ha~ing the feasible values "logic low",
"logic high" and "terminated by a high impedance". The
line 101 can thus be used for the input as well as the
output of data. If necessary, the elements 100, 112
comprise a level shifting circuit for modifying the logic
levels on the line 101 (for example, TTL levels) accord-
ing to those of the further parts of the circuit (for
example, MOS-levels).
During the loading of the mask register 103,
the signal LM = 1 in order to make the gate 102 conduct-
ive. The mask bit is received on the terminal 101 and
15 is stored, via the buffer stage 100 and the gate 102, in
the register 103 ~in this case for 1 bit). The mask
register 103 has the following functions:
1) First of all, the content of the mask field, i.e.
logic 1l0ll or "1", defines the size of the key field.
When the mask register contains a "1", the relevant
position forms part of the key field (the gates 104
and 106 are conductive and the gate 111 is blocked
via the inverter 109). If the mask register contains
a "0", the relevant bit position does not form part
of the key field (gates 104, 106 blocked and gate 111
conductive). When the gate 109 supplies a "1", the
data on the line 101 are transmitted by the stage 113
on the line Al and are inverted on the line A2. To
this end, the stage 113 comprises a line amplifier
which can be driven by the output of the gate 104 and `-~
whose output signals have mutually opposed logic --~
values. This amplifier will not be elaborated herein
for the sake of brevity. It is thus determined which
bits of the key word participate in the comparison.
The foregoing is initiated, via the OR-gates 105, 116,
by the signals CPM, SR, R, WP, the meaning of which
has already been described. If, on the other hand,
the AND-gate 104 supplies a logic "0", a logic "0"
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" 31.1.~'~0~
20 PHN 8989
signal appears on both outputs Al, A2.
2) The data of the mask register also define the extent
of the data to be newly written in the case of a write
operation. The data applied to the input 101 are
applied, via the buffer stage 100, to the element 114.
The latter element has substantially the same con-
struction as the element 113. If the OR-~ate 107 pro-
duces a logic "1", the element 114 supplies signals of
mutually opposed value. On the other hand, if the
logic OR-gate 107 produces a logic "0", the lines B,
B are charged to a high logic value by a transistor
circuit (not shown). This transistor circuit may ~orm
part of the element 114 and performs the function des- -
cribed with reference to Fig. 4. The logic "1" of the
gate 107 appears on the one hand under the control of
the signal WFP, only one word location which contains
exclusively invalid data being addressed, as has
already been described with reerence to Fig. 3. In
the case of the command WP, this takes place exclus-
ively for the bit positionsfor which the mask register
103 contains a logic "1", again under the control of a
word pointer signal as stated with reference to Fig.
3.
3) The commands SR and R furthermore activate the con-
ducting of the AND-gate 111 via the OR-gate 116. The
AND-gate 111 then supplies a logic "1" under the con-
trol of the bit positions for which masking of the
key field occurs. This is because the mask register
103 supplies a logic "0" for these bit positions,
said logic "0" being in~erted by the element 109. In
that case, the buffer stage 112 receives the signals
B, B and supplies a single signal on the output 101,
activated by the "1" output signal of the gate 111.
Elements of this kind are known per se. When LM
(mask loading) or WP (parallel writing) are performed,
the signals R and SR are always equal to 0, so that
the output buffer 112 is not activated.
'$. ':
906
21 PHN 898g
The signal LM controls the loading of the mask
over the full word width: a data signal is applied on
the line 101 for all bit positions. The signal WFP con-
trols the writing over the full word width: elements
114 and 115 are activated for all bit positions. The
latter element then supplies a high signal S. The sig-
nal WP controls the writing over a part of the word width
by way of the content of the bit position 103. If the
bit position 103 contains a logic "1", the inverter 109
supplies a "0" and the EXCLUSIVE-OR gate 110 receives
two unequal signals, so that the output signal thereof
activates the element 115 (via OR-gate 108~ as a lo~ic
"1". Thus, writing takes place in the non~masked parts
of the word locations (i.e. in the key field). On the
other hand, if there is no write command (WP = WFP = 0),
the element 115 is activated, via the inverter 109, only
for the positions which are masked, i.e. situated out-
side the prevailing key field. The gate 111 also con- ;
ducts for these positions in order to activate the out-
put buffer 112 under the control of the signal SR or R.
The construction of a larger content-address-
able memory will be illustrated with reference to Fig.
6. A small memory, constructed as an integrated circuit,
contains all bit cells, the mask register and the con-
trols described with reference to Figs. 3 and 5 accom-
modated on one and the same substrate. The circuit
thus comprises a clock input, three inputs for a three-
bit operation code, decoded in the "chip", the sequence
input 89 (which may possibly be derived from the clock
30 on the chip), power supply terminals and also one con- -
nection (101) for each bit position. The isolating cir-
cuit, comprising the elements 87, 88, 90, 91, may pos-
sibly be substantially simplified or even omitted,
because all components are present on a chip. A 40-pin
circuit may then accommodate, for example, 32-bit words.
The number of these words per se can be chosen at random.
For reasons of modular extension, however, units are
required which can be linked in word length as well as
. ~
.:
~8~6
22 PEIN 8989
in number of words. The arrangement shown in Fig. 6 com-
prises two types of integrated circuit. First of all,
the figure shows the memory chips which are capable of
containing 16 word locations of 16 bits. The complete
memory contains 64 words of 64 bits, so that each word
location is distributed over 4 individual integrated
circuits, for example, over the circuits 120, 121, 122,
123. Each of these circuits comprises 256 bit positions
of content-addressable memory, sixteen times a circuit
as shown in Fig. 5, including each time one bit mask
register and also the elements 90, 87, for each word
location, on the side of the control circuits 136, 137
and elements 91, 88 on the side which is remote from
these control circuits. The circuit 122 is then con-
nected to the secondary side of the circuit 123 in thesame manner as the primary side of the circuit 123 is
connected to the output side of the circuit 136. In
principle, the word length is then unlimited as far as
adequate discrimination exists between the different
states: "all bits correspond as regaxds content upon
comparison" and one single bit position of the two words
compared differs". This can be realised by including
each time regeneration amplifiers in the lines MA (Fig.
4). Corresponding bit positions of the word locations
25 of the circuits 120, 124, 128, 132 are each time inter-
connected by way of the bit-wise lines 101 of Fig. 5.
Each circuit of 16 x 16 bits then comprises sixteen data
lines (101), sixteen lines which pass through the inter-
face 82 in Fig. 3 (WL/MA in Fig. 4), three lines for the
operation code, two power supply lines, a clock line,
the line 89; for a 40-pin envelope, one pin then remains
for a purpose to be specified.
Control is in this case centralized in two
separate integrated circuits 136, 137, each of which
operates on 32 words of 64 bits. Each of these circuits
thus contains 32 times the circuit shown in the right
half of Fig. 3. Besides the 32 word lines, these cir-
cuits comprise three pins for receiving an operation
X
8~(~6
23 PHN 8989
code, a clock input, two power supply inputs, and the
transmission input 81 and the transmission output 140.
A 40-pin envelope again suffices. The signal on the
terminal 89 is then derived from the clock pulse (for
example, in that a clock pulse received each time starts
one cycle of an auxiliary clock pulse generator which
is provided on the chip and which generates a multiple
clock pulse~ Clock pulse generators of this kind are
known per se.
For the sake of simplicity, only the word lines
and bit lines of the storage chips are shown in Fig. 6.
Furthermore, only the word lines (diagrammatically), the
operation code lines (OPC), the clock line (CL) and the ~`
transmission conne~tions (81, 140) of the chips 136, 137
are shown.
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