Note: Descriptions are shown in the official language in which they were submitted.
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The Erasable Programmable Read Only Memory
(EPROM) is being used extensively in modern digital systems.
The present invention proposes an alternative EPROM cell
structure adapted to be integrated into a large EPROM array
for better overall performance.
In p-channel MOS technology, EPROM's have been
designed and fabricated using a FAMOS (floating gate avalanche
metal-oxide-semiconductor) type device which relies on the
avalanche breakdown of a junction to produce electron-hole pairs,
the electrons being injected into a floating or insulated gate
immediately above the avalanched junction. These injected electrons
serve to modify the surface conductance of the semiconductor
under the gate region, to program the previously non-conducting
device into a conductive mode. The programming voltage of this
type of device is usually greater than 45 volts. In n-channel
MOS technology, EPROM's incorporating stacked gate structures are
known which do not require high programming voltages. In these
structures, two levels of gate conductors are required: one, the
floating gate, provides the programming function and the other the
selection gate, located above the floating gate, provides the cell
selection function.
The present invention is superficially similar to
these prior stacked gate structures. However, it differs
fundamentally in that the roles of the two levels of gate
conductors are reversed. Thus, the invention proposes using the
upper gate as a floating gate to store injected charge, while
the lower gate is used as a selection gate. The invention offers
several advantages over the known stacked gate construction, thus:
(i) shorter erasal time when exposed to
ultraviolet radiation;
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(ii) better coupling between selection gate
and floating gate, whereby a lower
selection gate voltage may be used
during programming;
(iii) the threshold voltage of the unprogrammed
device is mainly controlled by the
selection gate to source and selection
gate to substrate voltages. The
selection gate conductor material can be
used to form the gates of any other MOS
transistors to provide a uniform threshold
voltage for all devices;
(iv) achievement of a more compact cell structure
by using the selection gate as a mask for
automatically locating a subsequent diffusion.
An embodiment of the invention will now be described
by way of example with reference to the accompanying drawings,
in which:-
Figure 1 shows a sectional view of an inverted
stacked gate MOS device according to the invention;
Figure 2 shows, schematically, the device ofFigure 1 in its circuit configuration; and
Figure 3 shows a schematic plan view of an EPROM.
Fabrication
The inverted stacked gate injection MOS device 1
of Figure 1 is fabricated using conventional MOS fabrication
techniques; see, for example, H. Iizuka, et al., "Stacked-~ate-
Avalanche-Injection Type MOS (SAMOS) Memory," in Proc. 4th Conf.
Solid State Devices (Tokyo, Japan, Aug. 1972); also ibid., vol.
42, pp. 158-166, 1973j H. Iizuka, F. Masuoka, T. Sato, and
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M. Ishikawa, "Electrically Alterable Avalanche-Injection Type MOS
Read Only Memory With Stacked-Gate Structure", IEEE Trans.
Electron Devices, vol. ED-23, pp.379-387, 1976? B. Rossler and
R.G. Miller, "Erasable And Electrically Reprogramable Read-Only
Memory Using The N-Channel SIMOS One Transistor Cell", Siemens
Forsch-u. Entwirkl-Ber., vol. 4, pp. 345-351, 1975.
An insulating oxide layer 2 and a polysilicon layer
3 are formed on a p-type silicon substrate, the layers being etched
to the cross-sectional shape shown. A p+ type region 4 is then
implanted or diffused in the substrate using the layers 2 and 3
to locate the implant. A second layer of polysilicon 5 on oxide 6
is then formed over the layer 3 and the implant 4. Finally, n+
type regions 7 and 8 are implanted or diffused into the substrate
using the layers 2, 3, 5 and 6 to locate the implant or diffusion.
Operation
In normal operation, the inverted stacked gate MOS
device functions as a MOS transistor. Referring to Figures 1 and
2, the regions 7 and 8 function as the transistor source 9 and drain
11, and conducting layer 3 functions as the transistor gate. The
gate is termed the selection gate 10 to distinguish it from a
floating gate 12 which is the completely insulated polysilicon
layer 5. The substrate channel region is represented at 13 in
Figure 2.
Normal transistor action occurs when an appropriate
potential difference exists between the drain 11 and the source 9
and a voltage exceeding a threshold level is applied to the selection
gate 10. The threshold voltage is ~nfluenced.predominantly by charge
stsred at the floating gate 12, the threshold, ;n the absence of
stored charge being about 2 to 12V.
To program the device, i.e. to substantially raise
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the threshold level, the selection gate is raised to about double
the normal operating voltage and a voltage pulse is applied to
the source. Electrons are accelerated towards the drain 11 by the
potent;al difference between source and drain. The p+ implant
4 enhances the accelerating electric fleld near the drain 11 where
the channel is covered by the floating gate, some of the electrons
gaining sufficient energy to be injected across the oxide layer 6
into the floating gate 12 under the influence of an electric field
across the oxide layer 6 owing to capacitive coupling between the
selection and floating gates lO,and 12.
A lower selection gate programming voltage is
required by the inverted stacked gate device than is the case with
the conventional stacked gate device of equivalent size owing to
more effic;ent capacitive coupling between the selection gate 10
and the floating gate 12. This is achieved because the floating
gate/substrate capacitance can be made lower (thereby producing
high floating gate/substrate voltage), without reducing the size
of the floating gate; reduction in floating gate size would cause
a consequent and undesirable reduction in the capacitive coupling
between the gates.
As a result of the charge injection, the device
threshold voltage is increased. When sufficient charge is stored
in the floating gate, the threshold level of the device is so high
that the device remains non-conducting even when a normal selection
voltage is applied. Since there is no electrical connection to
the floating gate, the injected charge can be stored for as long as
a few decades, the device then being in its programmed mode.
Inverted stacked gate devices can, in practice,
be made more compact than known stacked gate devices. Thus whereas
conventional and inverted stacked gate devices both require an
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implant or diffusion under the floating gate, the polysilicon on
oxide selection gate layer 2, 3 of the present invention provides
a mask ensuring automatic and exact alignment of the implant or
d;ffusion whereas in the prior art device, since the selection
gate overlies the float;ng gate, the substrate implant must be
formed without reference to either of the gates and is consequently
somewhat oversized in order to allow some tolerance in positioning
of the gates.
The stored charge on the floating gates of the
inverted stacked gate device can be removed or "erased" by exposing
the device to ultraviolet radiation. The erasure time is less than
the known stacked gate device owing to the greater exposed area
of the floating gate 12.
The inverted stacked gate device can be fabricated
as a p-channel device with appropriate reversal of dopant polarities.
Since the oxide layer 6 tends to trap holes to a much greater extent
than it does electrons, the n-channel embodiment is preferred.
The programming and erasing properties make the
structure suitable for use in an integrated circuit array such
as an EPROM. A schematic plan view of part of an EPROM is shown
in Figure 3 which shows selection gates 15, floating gates 16,
regions 17 over which insulating oxide extends, active regions 18
between the oxide regions 17, and aluminum leads 19 with contacts
20 to the n+ drain regions. The cells are usually located in an
M x N matrix with all the N selection gates of the same columns
connected to the word line and all the M drains of the same row
connected to the bit line. The N word lines are connected to a
one-of-N decoder and the M bit lines to a one-of-M decoder
(not shown).
