Note: Descriptions are shown in the official language in which they were submitted.
- ` 1124834
BACKGROUND OF TH~ INVE~TIO~
Field of the Inventior.:
This inver,tion relates in general to a method and
apparatus for inserting address signals in a video signal for a
video tape apparatus.
Description of the Prior Art
In order to edit video and/or audio signals rapidly a~
precisely, it has beerJ proposed in the prior art to record an
address signal on the ~agnetic tape in addition to the video
and/or audio signal. In this case, as the address signals are
provided si~nals of various codes, but the SMPTE time code sigr?e
is reco~menaed as an American National Standard and the EBU time
code signal is recommended as a standard code for 625 line/50
field television tape recordings. In the art, the above two
time code signals are recorded on a record medium along its
longitudinal trac~ and read out of the signals can be achie~ed
at tape speeds from slow to high speed. In the case where the
record medium is stopped or transported at véry low speeds, how-
e~er, the re?roduction of the time code sLgnals becomes impossibl~
In fact, upon editir.g a video tape by a video tape recorder, it
1~24834
is very advantageous for an editor to be able to choose indivi-
dual frames presented visually at very low tape speeds but the
disadvantages of this method of operation is that the address
of a chosen frame cannot be readily known with prior art systems.
The time code signals identify each television frame
but the identification of its even or odd field and that of the
phase of the burst signal of each television field are impossible.
Therefore, precise editing cannot be achieved by the kno~m prior
art systems.
In a video tape recorder having a still reproduction
~ode, in order to obtain an address signal n the s.ill repro-
duction mode, it has been proposed to convert the synchronizing
signal in the vertical blanking period of a television signal to
a signal corresponding to an address. For example, Japanese
Patent Publication No. 42/~540 filed by Nippon Hoso Kyokai,
published on February 24, 1967 discloses this method. This
Japanese Patent Publication discloses an address signal including
frame identification that can be reproduced even in a still re-
production mode but since there is no ordinary synchronizing
pulse in the vertical blanking period, a special processing is
necessary so as to supply the reproduced address signal to other
video tape recorders (VTRs) and a time base corrector.
In these prior art devices since one address signal is
recorded for each frame reading errors caused by dropouts or
guard band noise during reproduction cannot be prevented.
SU~ARY OF T~E INVENTION
It is an object of this invention to provide a method
of inserting an address signal in the vertical interval of a
video signal.
l~Z4834
Another object of the invention is to provide a method
of recording an address signal which prevents reading errors.
A further object of the invention is to provide a
method of inserting an flddress si~nal which includes an error
check code.
A still furtl;er object of the invention is to provide
a method of recording an address signal which is suitable for a
helical scan video tape recorder.
A still further object of the invention is to provide
a method of inserting an address signal which overcomes the
time base error.
A still further object of the invention is to provide
a circuit ~hich can read out an address signal ~ithout errors.
A ~et furt~.er object of the invention is to provide a
circuit which derives an address signal from a video ta~e re-
corder independent of the tape speeds.
In accordance with the foregoing, there is provided:
A met~od of inserting a~
address signal in a video si~nal comprising the steps of:
a) providin~ the address signal having a plurality
of time code biLs corresponding to the video signal
recorded 021 one trac~ followed by an error check code
signal;
b) selecting at least one ~redetermined horizontal
line period ~ithin a vertical blanking period from
each field or frame of said video signal; and
c) ir.serting said address signal in said selected
one horizontal line.
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There is also provided:
A method of inserting an
address sigr.al in a video signal comprising the steps of:
a) provi.ding the address signal having a pluraii.
of time code bits corresponding to one field of the
vicleo sign~l followed by an error check code signal;
b) selecting at least one predetermined horizontal
line period ~ithin a vertical blanking period from each
field or fra~e of said video signal;
c) inserting said address signal in said selec~ed
one horizontal line.
There is also provided:
A method of inserting an
address signal in a videG signal com?rising the steps of:
a) providing the address signal having a plurality
of time code bits corresponding to one frame of the
video signal follo-~ed by an error check code signal;
b) selecting at least one predetermined horizontal
line period within a vertical blanking period from
each field Gr frame of said video signal;
c) inserting said address signal in said selected
one horizontal line.
There is further provided:
An apparatus for producLr.
a video signal ~7ith an address signal therein, comprising:
a) means for providing the address signal
corresponding to one field or frame of the ~ideo
signal, s~id address signal consisting of a
plurality of time code bits;
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b) means for providing a cyclic redundancy
check codc signal for the address signali
c) means for selecting at least one predeter-
mined horizontal line period within a vertical
blanking period of each field or frame of said
video signal; and
d) means for inserting said address signal in
s2id selected one horizontal liné period.
There is further provided:
An apparatus for repro-
ducing an addre~s ~ignal from a video signal, comprising:
a) mean~ for receivlng the v~deo signal
including the addre~ signal having a plurality
of time code b~t~ cor~esponding to one field or
frame of the video signal and a cyclic redundancy
check code;
b) means for separating the addregs signal
from the video ~ignal;
c) means for ~toring the time code b~ts;
d) means for checking the address signal; and
e) means for generating a read-out pulse based
on the output of said checking means.
Other objects, features and advantages of the invention
will be readily ap~arent from the follo~ing description of
certain preferred ~,bodi~ents thereof taken in conjunction ~ith
the accompanying dra~ings slthough variations and modifications
may be effected without departing from the spirit and scope of
the novel concepts of the disclosure and in which:
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BRIEF DESCRIPTIOM OF THE DRAI~INGS
_ _ _
Figure 1 is a top plan view of a part of a ma~netic
tape on which a vid~o signal is recorded as slant tracks and
an address signal is also recorded by a prior art method;
Figure 2 is a schematic diagram illustrating an SMPIE
time code signal recordet on the tape;
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Figure 3 is a top plan view of a part of a magnetic.
tape on which a video signal and address signal are recorded
by the method of the invention;
Figures 4A and 4B are diagrams iliustrating a recorded
pattern of signals on a tape according to the invention;
. Figure 4C is a schematic diagram illustrating a time
code signal of the present invention which is recorded on the
tape;
Figure 5A is a diagram illustrating a ~ecorded pattern
of signals on a tape according to the present invention;
Figures 5B through 5K, 8 and 9 illustrate waveform
diagrams-used for explaining the operation of the circuit of
the present invention;
Figure 6 is a block diagram illustrating a circuit
according to the invention which is to be used to produce the
time code signals and record them on a magnetic tape.,
Figure 7 is a block diagram illustrating a circuit of
the invention for reading out the time code signals from a
magnetic tape and decode the address; ~-
Figures 8A - 8H show the wave forms of the various
pulses existant in the circuit of Figure 7; and
Figures 9A - 9D show further wave forms relating to
the synchronizing bit.
DESCRIPTION OF THE PREFERREI) EMBODI~:l`lTS
Figure 1 illustrates a prior art method of recording
an address signal on a magnetic tape comprising a magnetic
tape T upon which an address signal is recorded in addition to
a video signal.
In Figure 1, TV represents a number of video trac~s
formed on a magnetic tape T and each of the video tracks TV
includes a video signal of one field. Of course, a video signal
of one form may be recorded on one video track. TA designates
a track on the tape T which carries the audio signal. Track TQ
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represents the track which carries the cue signals and TC
designates a track which carries the control signals. On the
cue track TQ is recorded an address signal. In this case, a
SMPTE time code signal is used as the address signal and two
video tracks TV which form one frame are identified by one
SMPTE time code signal.
The SMPTE time code is approved as the American
National Standard time and control code for video and audio
tape for 525 line/60 field television systems on April 2, 1975
and published in the journal of the SMPTE, Volume 84, July 9,
1975.
As shown in Figure 2, which schematically illustrates
the SMPTE code signal, each address corresponds to one frame
and consists of 80 bits numbered 0 through 79 and the bit fre-
quency is selected as 2.4 KHz. As illustrated in Figure 2,
time address bits consisting of 26 bits indicate 29 frames, 59
seconds, 59 minutes and 23 hours. The bit number 10 is the
drop frame flag, the bit numbers 11, 27, 43, 58 and 59 are
unassigned address bits and the bit numbers 4 through 7, 12
through 15, 20 through 23, 28 through 31, 36 through 39, 44
through 47, 52 through 55 and 60 through 63 are user bits,
respectively. The synchronizing word of 16 bits is arranged
such that it is determined whether the tape is transported in
the forward direction and, thus, the S~TE time code signal
when read out in the direction indicated by an arrow F or
whether the tape is transported in the backward direction and
hence the SMPTE time code signal is read out in the direction
indicated by an arrow R. Thus, the time code signal can be
correctly read out even if the tape is transported in either
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direction. In this case, the code signal is so recorded that
the information "1" and "O" thereof are recorded as bi-phase
mark as illustrated in Figure 2.
As described above, if the address signal for each
frame of the video signal is recorded on the track TQ which
extends in the lengthwise direction of the tape T, editing
of the tape can be accomplished very rapidly and precisely.
However, in the case of slow or still motion repro-
duction mode, the speed of the tape becomes very slow or the
tape is actually stopped, then the code signal recorded on the
track TQ cannot be read out.
Figures 3 through 9 illustrate an example of the
invention which provides an address signal that can be read
out even in slow or still reproduction modes and, thus,
editing of a tape can be efficiently accomplished. The video
signal of the NTSC system is used as an example.
Figure 3 is a top plan view of magnetic tape T on
which the video signal and address signals are recorded by the
method and apparatus of the invention.
With the invention, an address signal SA, identifying
a video signal corresponding to each TV track, is inserted in
the video signal as a digital signal and the video signal are
recorded on the tape as slant tracks Tv. The address signals
SA recorded on the video tracks TV are indicated as hatched
areas in Figure 3 The address signals SA are inserted into
the video signals of odd and even fields of one frame and then
recorded as shown in Figure 3.
In this invention, the time code signal lncludes
synchronizing bits which are inserted in the time code signal
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at every predetermined bit and then recorded on the video
track TV so that by correcting the phase of the clock at
every predetermined bit by utiliæing the synchronizing signal
upon read out, the code signal and the address signal can be
read out precisely even if the bit frequency of the code
signal varies by jitter, skew or other noise factors or by
the variation of the horizontal frequency in a slow or still
motion reproduction mode.
Further in this invention, there is provided an error
check code in the code signal to avoid read out error.
As shown with hatches in Figures 4A and 4B which
comprises a record pattern of signals on the tape, not shown,
according to the invention, one address signal is inserted into
one horizontal line period in the suppressed line period within
the vertical blanking ?eriod or vertical interval excepting
that portion which comprises a vertical synchronizing pulse
period Tvp and equalizing pulse period TEp The address signal
is inserted in the period after burst signals SB and it is
desired that the sa~.e address signals be inserted repeatedly
into three successive horizontal line periods. Hereinafter,
this address signal ~ill be referred to simply as the VITC
(vertical interval time code) signal. The above suppressed
periods correspond to the 10th through 21st line periods in
the NTSC system.
The bit frequency fB of the VITC signal is selected
as the color subcarrier frequency fsc which equals 3.58 MHz
divided by an integer, for example, one-half (112) of the
frequency fsc. If the horizontal line frequency is taken as
fH and the vertical frequency as fv~ respectively, the following
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relationship is established:
455 f = 455 x 525
fsc 2 H 4 fv .......................... (1)
Thus, if the following relationship is established:
fB -~- fsc ............................ (2)
and the following equation 3 is obtained:
fB ~Z~ f~ ............................. (3j
Now, referring to Figure 4C, the arrangement of code
signal of the invention will be explained. The code signal is
recorded on the video track Tv, so it is not necessary to
employ the synchronizing word at the top of the code Sr~TE
time code signal shown in Figure 2. First, synchronizing bits
consisting of 2 bits are placed at the top of the code signal
as shown by a hatched portion in Figure 4C.
Synchronizing bits, each consisting of 2 bits are placed at
every ten bits, which are shown by hatched portions in Fi~ure
4C. So, the bit numbers 0, 1, 10, 11, 20, 21, 30, 31, 40, 41,
50, 51, 60, 61, 70, 71, 80 and 81 are synchronizing bits.
Time address bits are arranged similar to that of SMPTE time
code. The bit numbers 2 to 5 are units of frames, 12 to 13
are tens of frames, 22 to 25 are units of seconds, 32 to 34
are tens of seconds, 42 to 45 are units of minutes, 52 to 54 are
tens of minutes, 62 to 65 are units of hours and 72 to 73 are
tens of hours, respectively. The bit number 14 is the drop
frame flag, the bit number 15 is a field mark, the bit numbers
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35, 55, 74 and 75 are unassigned address bits and the bit
numbers 6 through 9, 16 through 19, 26 through 29, 36 through
39, 46 through 49, 56 through 59, 66 through 69 and 76 through
79 are user bits.
By making the bit numbers 15 be ~o~i for 1 and 3
field or "1" for 2 and 4 field, the field identification as
to whether the field is even or odd can be accomplished.
Total bits number of these information bits, synchronizing
bits, time code bits, user bits and so on, are 82 bits. After
these information bits, there is provided an error check code
for the preceding code, for example, cyclic redundancy check code
~hereinafter referred to as CRC code) consisting of 8 bits.
In using CRC code, the data presented between O and 81 bit (in
all 32 bits~ are divided by a predetermined code or polyno~ial(
x8 + 1) and the residual is coded into the final 8 bits. The
last 8 bits are the CRC code. In the; decoding process, all 90
bits, including the CRC code are divided by the predetermined
code whic~ is constant and can be expressed by x8 + 1. The
predetermined code used in the decoding process is the same
prede~ermined code as used in the encoding process. The
residual acts as an indicator of error. If there is a residual
the information is incorrect, if not, the information is
correct.
Figure 5A illustrates an example of the time code
signal representing an address according to the present inven-
tion. The code signal consisting of 90 bits is inserted in the
period of 50.286 micro seconds and is inserted from the timing
Ts (for example 10.616 micro seconds) after the front edge of
the horizontal synchronizing signal till the timing 2.65 micro
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seconds before the front edge of the following horizontal
synchronizing signals. The code signal illustrated in
Figure 5A indicates an address of 29 frames, 59 seconds, 59
minutes, 23 hours, the same as the address shown in Figure 2.
In this case, it is sufficient that thè informations
"1" and "O" of the VITC signal are expressed as different
s;~r~al ,J
le ~ wn in Figure 5A. For example, information "O" is
selected as the pedestal level and the information "1" is
selected as 50 IRE units or a signal higher than the "O"
level and then the signals are recorded with opposite level to
the horizontal synchronizing pulse viewed from the pedestal
level.
Fi~ure 6 illustrates a circuit for producing the VITC
signal and for recording the same on a magnetic tape.
In Figure 6, an input terminal 1 receives a video
signal which is to be recorded. The-video signal is fed to a
clamp circuit 2 and synchronizing signal separator 3 which
separates a synchronizing signal from the video signal. There
is provided a clamp pulse generator 4 which generates a clamp
pulse from the synchronizing signal. The video signal through
the clamp circuit 2 is fed to an adder circuit 6 through a
vertical blanking period shaping circuit 5 and also fed to a
synchronizing signal separator 7. Frame pulses are separated
by a frame pulse separator 8 which receives an output of the
synchronizing signal separator 7. The frame pulses are fed to
a time counter 9. The output of the synchronizing signal
separator 7 is fed to a mono-stable multivibrator 10. The
mono-stable multivibrator 10 removes an equalizing pulse from
the signal and generates a signal having a horizontal fre-
quency fH, which is fed to a phase comparator 11. The phase
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comparator 11, a variable frequency oscillator 12 and a
timing clock generator 13 form a PLL ~phase lock loop) circuit.
The timing clock generator 13 generates a signal having a
frequency fH and clock pulses Pl through Plo shown in Figures
5B through 5K. The sign~l having a frequency fH generated by
the timing clock generator 13 is fed to the phase comparator
11 to compare with the input from the mono-stable multivibrator
10. The resulting output from the phase comparator 11 is fed
to the variable frequency oscillator 12 as a control signai
for it. Thus, the clock pulses Pl thEough Plo are generated
which are synchronized with the horizontal synchronizing signal
of the video signal.
The clock pulse Pl has the same frequency as the color
subcarrier frequency fsc~ The clock pulse P2 has a frequency
of 1/2 fsc, and one cycle of the clock pulse P2 is equal to
cel~
one bl ~ f the code signal shown in Figure 5A. Further, the
clock pulse P3 has a frequency of 1/4 fsc. The timing clock
generator 13 is constructed so as to generate the clock pulses
P4 through P6 by a decimal counter from the clock pulse P3,
and the clock pulses ~7 through Plo by a hexadecimal counter.
The clock pulses from the timing clock generator 13 and an
output from the time counter 9 are fed to a time code encoder
14 to form a time code (frame code, second code, minute code,
and hour code) which is fed to an adder circuit 15. ~hile
synchronizing bits are ~ormed by the synchronizing bit generator
16 by using the pulses from the timing clock generator 13, and
user bits are formed at a user bit enco~er 17. These synchron-
izing bits and user bits are fed to the adder circuit 15.
Accordingly, the output of the adder circuit 15 is the code
signal which consists of the time code, the user bits and
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synchronizing bits arranged in the manner shorn in Figure 4C,
Then the output of the adder circuit 15 is fed to a CRC code
encoder 18. Then the code si~nal shown in Figure 4C is
derived from an adder circuit 19 which is added with the CRC
code which is derived by the CRC code encoder 18. The code
signal is fed to a gate circuit 20.
While gate pulses which are corresponding to three
successive horizontal line periods in the vertical blanking
period are derived at the gate pulse generator 22 based on a
vertical synchronizing pulse separated by a vertical syn-
chronizing signal separator 21 from the output OL synchroniz-
ing signal separator 7. Then the gate pulses are fed to the
gate circuit 20. Thus, the code signal gated by the gate
signal is fed to the adder circuit 6. A code signal which
may have been inserted in the vertical blanking period is
removed at the vertical blanking period shaping circuit 5 from
the video signal by gating by the gate pulse from the gate pulse
generator 22. Then the output from the ci.rcuit 5 is fed to
the adder circuit 6.
Thus, the video signal in which the code signals are
inserted into three successive horizontal line periods within
the vertical blanking period is derived from an output terminal
23. The output video si.gnal is recorded on a magnetic record-
ing tape through a signal recording system of the VTR which
includes FM modulator and so on.
Further, i~ is possible to provide the SMPTE timé code
from a terminal 24 and to synchronize the S~TE time code with
the time code which is to be inserted int.o the video signal.
The synchronization can ~e achieved by pre-setting the time
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counter 9 when a preset switch 26 is on. The SMPTE time code
is fed through a decoder 25 and the preset switch 26.
Figure 7 is a block diagram illustrating a circuit
of the invention for reproducing the video signal recorded on
the tape explained in the above, reading out the code signal
from the video signal and, decoding the address.
In Figure 7, an input terminal 31 receives a video
signal reproduced from the video signal recorded on track Tv.
The code signal is derived at an output terminal 32 by the
following way. First of all, the video signal is fed to a
code separator 33. The code signal ijs separated from the
video signal by a synchronizing signal which is separated
from the video signal at the synchronizing signal separator
34. There is provided an oscillator 35 which oscillates with
a frequency which is n times of the.color subcarrier frequency
fsc (n is integer, for example, n equals to 8 ).
An output of the oscillator 35 is fed to a hexadeci-
mal counter 36. An output of the hexadecimal counter 36 having
a frequency of 1/2 fsc is fed to a decimal counter 37. An
output of the decimal counter 37 is fed to a hexadecimal
counter 38. Thus, the clock pulses Pl and P2 which are the
same as the. pulses of recording, are obtained (derived) from
the counter 36, the clock pulses P3 through P6 are obtained
from the counter 37, and the clock pulses P7 through Plo are
obtained from the counter 38. These pulses are synchronized
with the code signal separated from the reproduced video -
signal.
Thus, a mono-stable multivibrator 39 generates a
pulse Pll which is narrower than a horizontal line period but
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wider than the period where code signal of 90 bits exists a~
shown in Figure 8C, while an edge pulse generator ~O generates
edge pulse corresponding to a trailing edge of the code
signal.
The output of the counter 37 is fed to a synchroniz-
ing bit gate pulse generator 41 to generate a synchronizing
bit gate pulse shown in Figure 8B which is similar to the
clock pulse P6 which has a value "1" at the phase corresponding
to synchronizing bits.
Now, let us assume that the code signal including
synchronizing bits of "(10)" as shown in Figure 9A is separated
from the video signal. Then the edge pulse generator 40
generates an edge pulse corresponding (synchronized) to the
trailing edge of code signal, as shown in Figure 9B. This
edge pulse and the synchronizing bit gate pulse P12 shown
in Fi~ure 9C are fed to an AND gate 42 to derive only an edge
pulse synchronized with the trailing edge of the synchronizing
bit.
This edge pulse is fed to the counter 36 as a reset
pulse through an OR gate 43 and an AND gate 44. Accordingly,
as shown in Figure 9~, the phase difference ~between the
output of the counter 36 having a frequency of 1/2 fsc and the
timing of the code signal is corrected and the output of the
counter 36 is synchronized with the code signal. By the
above construction, even when the time base fluctuates from
the normal time base by iitter or slow motion reproduction, the
timing of the clock pulse is synchronized with the reproduced
code. Further, the synchronizing bits are inserted at every
ten bits, so it is possible to achieve a very precise syn-
chronization.
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In the above example, the oscillator 35 is a fixed
oscillator. However, such an oscillator that is phase locked
to, for example, the horizontal synchronizing signal of the
reproduced video signal, can further widen the extent of the
timing that can be synchronized. Then it is possible to read
the code signal even at the still mode reproduction in which
a magnetic tape is stopped and at the fast mode in which the
tape is run at the speed of several times of the normal speed
of reproduction. The counters 37 and 38 are reset by the
leading edge of the pulse Pll which is an output of the mono-
stable multivibrator 39 through the A~ID gate 45.
The output pulses of the counters 36, 37, and 38
are fed to a timing pulse generator 46 to form required timing
pulses.
The code signal separated by the code separator 33
and output pulse of counter 36 is fed to a series-parallel
transformation circuit 47 which comprises a shift register
to rearrange the code signal except synchronizing bits and
CRC code, that is, time codes and user bits (in all 64 bits)
into parallel codes in which each code consists of 4 bits.
These parallel codes are written into a buffer memory
48 of a RAM (Random Access Memory) and also fed to a code
check circuit 49.
The code check circuit _ decodes the time code
consisting of 4 bits which is supplied from the circuit 47
by the timing pulse P14 corresponding to the timing of the
time code signal shown in Figure 8E, which is generated by
the timing pulse generator 46, and check the decoded numbers
whether they are possible numbers or not. There are some
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possibilities that, for example, hour code shows 27 hours or
second code shows 81 seconds which are apparently incorrect
caused by dropout.
The code check circuit 49 generates a signal "1"
when the code is correct, and a signal "O" when the code is
incorrect. The code signal from the code signal separator 33
is fed to a GRC code check circuit 50. The pulse P13 shown in
Figure 8D which coincides the phase of the CRC code generated
by the timing pulse generator 46 is fed to the CRC code check
circuit 50. In the CRC code check circuit 50, the code signal
including the information code and the CRC code (in all 90 bits)
is divided by the predetermined code or polynomial and the
resid~al is checked. If there is no residual the code is
correct then the circuit 50 derives a signal "1". When there
are residuals the code is incorrect, the circuit derives a
signal "O". Further, the synchronizing bits are separated from
the code signal by gating at a gate circuit 51 by the synchron-
izing bit gate pulse P12 show~ in Figure 8B. The separated
synchronizing bits are fed to a synchronizing bit check circuit
52. Whether the synchronizing bits are correct or not, is
checked by the suspected synchronizing ~its from the timing
pulse generator 46. If it is correct, the circuit 52 deri~es
a signal "1", if not, it derives a signal "O".
The outputs of the synchronizing bit check circuit 52,
the code check circuit 49 and the CRC code check circuit 50
are fed to an AND gate 53. When the output o~ the A~ID gate 53
is "1", which means the code signal is correct, a hold circuit
54 generates a pulse P15 which is "1" shown in Figure 8G by
the timing pulse from the timing pulse generator 46. The
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hold circuit 54 is reset by a vertical synchronizing pulse Tvp
(shown in Figure 8F) from the vertical synchronizing separator
55 which is connected to a synchronizing separator 34.
The output pulse P15 of the hold circuit 54 is fed to
the AND gates 44, 45. Thus, when the pulse P15 becomes "1",
reset of the counters 36, 37 and 38 is forbidden.
The pulse P15 is fed to an A~ID gate 56 and
a memory pulse generator 57. The AND gate 56 supplies a
writing clock pulse for the buffer memory 48. During the period
that the pulse P15 is "0" codes of 4 bits from the series-
parallel transformation circuit 47 are continuously written into
the buffer memory, but the pulse P15 becomes "1", the writing
into the memory is forbidden.
And, the memory pulse generator 57 generates a memory
pulse P16 which coincides the leading edge of the pulse P15 as
shown in Figure 8G. By feeding the memory pulse P16 to the
AND gate 58, writing clock pulse is fed to a buffer memory 59
through the AND gate 58. Thus, contents of the buffer memory
48 is transferred to the buffer memory 59. The output data
consisting of the time code and the user bits (in all 64 bits)
is derived at the output terminal 32 by supplying a read-out
address signal through a terminal 60. The read out data is
fed to a display andJor editing apparatus.
As mentioned previously, the code signals are inserted
into three successive horizontal scanning interval of the
vertical blanking period. If the code signal inserted in the
first horizontal line period is incorrect, the pulse P15 ~rom
the hold circuit 54 does not rise then the date is not trans-
ferred from the buffer memory 48 to the buffer memory 59.
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The code signal of the next horizontal line period is checked
in the same manner. Then only the correct code signal is
stored in the buffer memory 59. Then it is not necessary to
insert the code signals into successive horizontal scanning
interval. The code signal may be inserted in any of the in-
tervals if it isnot in the useful scanning lines. Further,
the number of the repetition of the code signal is not re-
stricted.
In this invention, even only one of the code signals
is read correctly, the hold circuit S4 generates the pulse P15
and the system works well.
In the above example, the code si~nal which repre-
sents an address is recorded on the track Tv. But at the
same time, the SMPTE time code signal which represents the
same address which is recorded on the track TV can be recorded
on the track TQ which is extending in the longitudinal
direction of the magnetic tape. The S~PTE time code signal
can be recorded as a bi-phase signal the same as the signal
recorded on the track Tv.
Due to construction of the recording apparatus of
the present invention, since an address signal showing a video
signal is recorded as a digital signal on the track of the
video signal, the digital signal corresponding to the address
can be read out positively even in slow or still motion re-
production mode and, thus, editing of the video tape can be
very ef~iciently carried out.
Also, in the invention, the synchronizing pulses and
other pulses are not processed but the address signal is
inserted in the horizontal line period between the horizontal
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synchronizing pulses within the vertical blanking period 80
that no undesirable influences are caused on signal process-
ing such as clamping the video signal, separating the
synchronizing signal and so forth and the reproduction will
not be interferred with in any manner.
The bit frequency fB of the inserted VITC signal
is selected to be a fraction of the subcarrier frequency fSC
by an integer so that if the video signal with the VITC
signal is routed through the time base corrector the repro
duced video signal is written in the memory by the clock
pulse whose frequency is higher than the color subcarrier
frequency by an integer time and then the written si~nal is
read out in the memory to correct its time base. Thus, the
clock references are the same in number at every one bi ~of
the address signal and the condition of the address code is
not affected by the time base correction.
Further, in this invention there are inserted
synchronizing bits at every predetermined bit in the code
signal, the read out error can be checked by the synchronizing
bits, and by forming pulses synchronized with the synchronizing
bits, read out of the code can be achieved precisely even if
the bit frequency of the code signal varies by jitter, skew,
or other noise factors or by the variation of the horizontal
frequency in a slow or still motion reproduction.
In this invention, error check code of CRC code is
added to the code signal, so read out of the code signal can
be achieved more precisely
The above examples of the invention correspond to the
cases in which the video signal of the NTSC system are utilized
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1~24834
so that the bit frequency of the VITC signal is selected as
n fsc (n being an integer). However, when video signals of
other systems such as PAL systems or other types are utilized,
it is necessary to select the bit frequency of the VITC signal
in view of the predetermined relationship to the horizontal
frequency such that all bits of the VITC signal can be in-
serted in one horizontal line period as, for example, 455/4 fH
horizontal line frequency.
Although the invention has been described with respect
to preferred embodiments, it is to be realized that modifica-
tions and variations can be made by one skilled in the art
without departing from the spirit and scope of the novel con-
cepts of the invention as defined by the appended claims.
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