Note: Descriptions are shown in the official language in which they were submitted.
- 2 ~ S~5 ~
1 The field o~ the invention relates generally to
2 electrical waveform synthesizers, and more particularly ~o
3 DC or AG vol~age conver~ers.
4 Many different ci.xcul~s are known in ~he ~rt
S for co~verting a DC voltage into an AC vol~age. These cir-
6 cuits tend to be very complex, re.quiring a large nu~er o~
7 components, resulting in high cost and reduced reliability.
8 Also~ many of these prior art circuits are limited to con-
9 verting a DC voltage into an AC voltage at a given ~requency,
10 and also the AC voltage is usually high in harmonics, which
11 is undesirable in many applications.
12 The present invention is a wavefGrm synthesizer
13 circuit capable of converting a ~C vol~age into a desired
14 AC waveform, such as a s~newave~ for example. In a irst
embodiment, a ~irst level-shifting stage is included for
16 selectively applying a voltagP having a level equal to or
17 greater than that of a DC voltage supp~y to a pair of tran-
18 sistorized switches. A second level-shifting stage is in-
lg cluded, permi~ting the two level shifting s~ages to be
individually operated during alternate hal~-cycles of the
21 AC waveform, respectively, thereby decreasing the duty
22 cycle time for each one of the level-shifting stages. The
23 transistorized swi~ches o~ the two stages are selectively
24 opera~ed or applying this voltage across a load and driving
current through the load in a given directiong or ~or gro~nd~
26 ing the load. n a second embodimen~, in addition to the
27 inclusîon of a second level-shifting stage~ a pair of
28 mechanical or transis~orized sw~tches are ~ncluded with the
29 other pair of transistorized switches~ respectively, and are
30 operated for selectively prov;ding eit~er rated voltage and
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,
3 ~t,~5~5j~
1 ra~ed current operation, or half-rated voltage and twice-
2 rated current operation.
3 In the drawings, where like items are indica~ed
4 by the same re~erence designat~vn: Flg. 1 is a clrcult
schematic diagram of a prior art DC to AC converter; Fig. 2
6 shows a ~ypical two-level unipolarity waveform tha~ m~g~t
7 be produced a~ point A in the circuit of Fig. l; Fig. 3
8 shows a typical four-level notched stepw~se approximation
9 oE an AC wave~orm, in this example a sinewave; Fi~. 4 is a
rircuit schematic diagram of a waveform synthesizer circuit;
11 Fig. 5~is a circuit schema~.ic diagram of a first embodiment
12 of the inv~ntion; Fig~. 6 is a circuit schematic diagram of
13 a second embodime~lt o~ ~he invention; Fig. 7 is a circuit
~4 schematic d;agram of a high-power switchin~ amplifier, and
Fig. 8 is a block diagram of a controller ~or providi~g
16 control signals for operating the various transistorized
17 switchcs of the p~esent invention.
18 In Figure 1, a prior art DC to AC conver~er includes
1~ a DC volkage supply 100 (shown as a battery) having a level
of voltage equal to E volts, a lavel-shifting stage including
21 a pair of swi~ches Sl~ S2, a diode 102~ and a capaci~or 104;
22 and a bridge-connected SCR mixer network including SCR's 106,
23 108, 110 and 112, eacn having a control terminal 114, 116,
24 118, 120, respectively; four d~odes 122, 124, 126, 128; and
a pair of ou~put term~nals 13~ and 132 be~ween which a load
26 impedance 134 may be connected. In operati~n, when switch
27 Sl is operated ~o connect its pole 3 to its lower con~ac~ 5,
28 the level of voltage at poin~ B is about E volts, and capaci-
2g tor 104 begins taking on charge. If switch 1 is maintained
5'~
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1 in its down posi~ion for a sufficient period of time,
2 capacitor 104 wiLl fully charge, resulting in a voltage
3 drop across capacitor 104 of E v01~5. Thereafter, ~f
4 switch Sl is now operated to connect its pole 3 to ~ts
upper contact 1, the capaci~or 104 is connected in serles
6 with the DC voltage supply or battery 100, rais~ng the
7 Level of voltage at point B to 2E volts. Switch S2 is
8 operated ~o its upper position connecting its pole 3 to
9 its upper contact 1, for applying ~he voltage at point B
to point A, and to ~ts Lower position for connecting lts
ll pole 3 to its lower contact 5 for applying ground to
12 point A. By selectively operating switches Sl and S2 be-
13 tween their respective upper and lower positions in differen~
14 combinations at dif~erent times a the two-Level unipolarity
notched waveform shown in Fig. 2, can be obtained at point
16 A, for example. Control signaLs are select;vely appLied to
17 the operating terminals 114, 116, and 118, 120, of SCRts 106,
18 108, 110 and 112~ respectively, for turning on and ofE in
19 pairs, that is~ 106 and 112 together, 108 and 110 together~
to operate the mixer networ~ for converting the two-level
21 wave~orm of Fig. 2 into the four-level waveform of Fig. 3,
22 for example. In this manner, a stepwise approximat~on of a
23 sinewave can ~e generated 9 for example. A major d;sadvantage
24 of this SC~ mixer circuit is the complexity of the circuitry
necessary to turn o~f the conducting ones o the SCR's 106-
26 112, 108-110. It should be noted that an SCR is a solid-
27 state swit~hing device that can be turned on by applying a
28 control signal ~o its control terminal, but can be turned off
29 only by either interrupting the flow o curren~ to its main
`
s -
~ 8 ~
1 current conduction path, or bac~biasing the anode-cathode
7 electrodes of its main current path.
3 In Fig. 4, a waveform synthesizer circuit includes
4 a DC volta~e supply or battery 136 havlng an ou~put voltage
of level E volts; at least one level-shif~ing stage 137 in-
6 cluding a swi~ch S3, a diode 1389 and a cap~citor 140; and
7 a pair ol switches S4, ~nd Ss. The level sh~ting stage 137
8 is identical in operation to the level shiting stage Sl,
9 1025 104 of Fig. 1. As previously described, such a level-
shifting stage 137 is capable of ei.ther unity gain leveL
11 shifting or voltage doubling. As indica~ed in Fig. 4, such
12 level-shifting s~ages 137 can be cascaded for selec~ively
13 providing at point D~ a voltage ~aving a level equal to E
14 volts, 2E volts, 3E volts up to NE volts, w~ere N is some
integer number equal to the numbe~ of cascaded level-shifting
16 s~ages 137. For the purposes of this discussion, it is as-
17 sumed that only one stage of level shifting is provided (N=l~.
18 The switches S3 and S4 correspond to the swi~ches Sl and S2,
19 whereas the switch S5 replaces the entire SCR mixer circuit
136, 108, 110, 112, 122, 124, 126, 128 of Fig. 1.
21 In operation~ switch S3 is operated to connect its
22 pole 41 ~o its upper contact 45, or lower contact 43, for
23 applying either E or 2E volts at point D r respec~ively. A
24 typical waveform that can be so generated at point D iS shown
in Fig. 2, for example. The time duration for the waveform
26 to be at any given level is determined by the length of time
27 that the switch S3 is heLd in either its upper or lower posi-
28 tion. In this manner, dynamic level shirting is provided,
29 concurrent with pulse width modulation of the voltage steps
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1 between the ~E and +2E levels of voltage. The switch S4 is
2 operated to its upper position (arm 41 connected to contact
3 45) concurrent wi~h switch Ss being operated to i~ lower
4 position (arm 41 connected to contact 43) for a d~rection o~
current flow from switch 4 to output ~erminal 142, through
6 load 144, into output terminal 146, thro~lgh ~witch S5, to
7 ground terminal 148, causing a voltage drop across the
8 load 144 of the polar~ty indicated. For opposite direction
9 o~ current flow through the load and a resultant opposi~e
poLarity of voltage across the load~ switch S4 is operated
11 to its lower position ~arm 41 connected ~o lower contact
12 43) concurrent with switch Ss operated to its upper posi~ion
13 ~arm 41 connected to contact 45). For applying zero volt
14 across the load, tha~ is, grounding bo~h output terminals
142 and 146, switches S4 and S5 are concurrently operated
16 t~ their downward positions (arms 41 connected to contacts
17 43). In this manner, the bipolar waveform shown in Fig. 3
18 can be obtained, for example~ from a waveform such as shown
19 ;n Fig. 2 bel~g generated a`t po~n~ C, as previously described.
Such operation o~ the swîtches S4 and S5 also provides or
21 pulse width modulation of the first steps or levels of vol-
22 tage occurring between ~ero and ~E and zero and -E. The
23 waveform sho~ in Fig. 3 is as pre~iously mentioned a step~
24 wise approximation of a sinewave9 but it should be noted that
through proper control of the switches S3, S4, S5 many other
26 non-sinusoidal stepwise approximated AC voltage waveforms,
27 the frequency of which can be selectively varied, can be
28 synthesized. In Fig. 3, the notches are placed at predeter-
29 mine~ times and have predetermined wid~hs, for reducing th~
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~ 2
1 harmonic content of the approximated waveform.
2 In Fig. 5, a first em~odiment o~ ~he invention i5
3 shown. The circuit is substantially iden~ical to the circui~
4 o Fig. ~, with the addit~on o~ a second stage of Level
shifting 137' or N'-cascaded stages o~ level shif~ing 137'
6 (for purposes o~ this discussion N'=l). This additional
7 stage of level shiftlng 137 ' is connected between the upper
8 contact 45 o switch S5 and the battery 136. The advantage
9 of the cireuit o Fig. 5 over that of Fig. 4 is thak in
generating a symmetrical waveform such as shown in Fig. 3,
11 dur;ng a period of time Tl, swi~ches S3 and S4 are operated
12 to their upper positions, and switches S5 and S6 to their
L3 lower pQS itions, for driving current ~hrough the load 144
14 in a direction to produce the polarity of voltage indicated,
whereby capacitor 140 is discharging through the load and
16 connected in series with the battery E, for producing the
17 voltage steps ~2E, for example. I switch S3 is operated ~o
18 its lower position, a voltage level o~ ~E is applied across
19 the Load 144 and the capacitor L40 takes on charge from the
battery 136 via diode 138. DurLng this perlod of ~ime Tl,
21 the capacitor 150 of the second level shifting stage is per-
22 mitted to fully charge to the polnt where the voltage drop
23 across capacitor 150 is substantially equal to E v~lts.
24 During the time period T2 o the next half-cycLe of the step-
wise approximated AC waveform shown in Fig. 3 9 swi~ches S3
26 and S4 operated to their lower posi~ions, switch Ss to its
27 upper position, and switch S6 between its upper and Lower
28 positions for genera~.ing the -E and -2E levels of steps of
29 voltageO By using at least two level-shi~tLng stages 137,
1 1371 in the manner shown in Fig. 5, in generating symmetrical
2 waveforms such as shown in Fig. 3 9 the level-shifting stages
3 137 and 137' are required for active use during only alter-
4 nate half-cycles of the AC waveform. Contra~ywise, in the
circuit o~ Flg. 47 ~he level-sh~f~ing stage 137 must b~
6 operated over the entire period or full cycle ~Tl ~ T2~ of
7 ~he AC wave~orm. Accordingly~ the circuit of Fig. 5, in
8 generating sym~etrical waveforms, redu~es ~he duty cycle of
9 the level-shifting stages 137, 137' by a factor of one-half.
Or course, i~ non-symmetrical waveforms ara genera~ed, then
11 one or the o~her of the level-shif~ing stages 137 and 137'
12 wiLl be operated or more than half of the period of t~e
13 nonsymmetrical waveorm generated, in most instances. Ac-
14 cordingly, the circuit of Fig. 5 can be operated ~or genera-
tlng a broader range of frequencies o synthesized waveforms9
16 because the capacitors 140 and 150 are kept at a higher level
17 o charge ~hroughout the period of the generated waveform.
18 In Fig. ~ a second embodiment of the invention is
19 shown. In comparison to the em~od~ment shown in Fig. 5, a
pair of switches S7 and S8 have been added as shown. In
21 operation, if the switches S7 and S~ are operated to their
22 upper positions, the operation of the circuit of Fig~ 6 is
23 identical to that of the circuit of Fig. 5. If the switches
24 S7 and S8 are operated to their lower positions, the swi~ches
Ss and S6 are connected in parallel operation with respe~t to
26 output terminal 146, and similarly, the switches S3 and S4
27 are connected in parallel with respect to output terminal 142.
28 Acc~rdingly, when switches Ss and S6 are operated to their
29 upper positions, concurrent with switches S3 and S4 operated
1 ~o their lower positions, current will 10w from the battexy
2 136 through switches S6 and S7 to outpu~ terminal 146, and
3 rom ba~tery 136 ~hrough diode 148 and switch S5 to oùtput
4 ter~inal 146, through the load 144 into outp~t ter~inal 14Z,
and therefrom both through switch S4 to ground a~d ~hrough
6 switches S8 and S3 to ground. Assuming that ~he switches
7 S3, S4, S5~ S6, S7 and S8 all have the same cuxrent rati~g,
8 ~t should be clear that a magnitude of current twice that
9 obt~inable ~rom the circuit of Fig. 5 can be supplied ~o
the load 144, but only at a voltage level of E volts, for
by necessity the capacitors 150 and 140 are out Gf the cir-
12 cuit. For rever~ing ~he flow of twice rated cur~ent through
13 the load ~44, the switches Ss and S6 are operated to their
14 Lower positions, and the switches S3 and S4 are operated to
their upper positions. For applying zero volts across the
16 load, switche~ S~ through S6 are ~pera~ed to their lower
17 positions, for example, thereby grounding output terminals
18 142 and 146. In o~her words, in opera~ing the circuit o~
19 Fig. 6, wi~h switches S7 and S8 in their upper positions, a
voltage of up ~o +~F. volts can be applied across the load
21 144, and a magni~ude of curren~ equal to ~he current rating
22 of the switches S3 through S8 can be driven through the loa~
23 With switches S7 and Sg operated to their lower positions, a
24 voltage level of E volts can be applied across the load 144,
2S and a curren~ having a mag~itude equal to twice the rated
26 curren~ magni~ude of the switches S3-S8 can be suppl;ed to
27 the load 144. Such a circuit may be use~ul in operating an
28 elec~ric motor3 for e~amp~e, through a range o~ speeds at
~9 diferent levels o~ torque.
~ ~o -
~ 5~
1 It should be noted that capacitors ~40 and 150 can
2 each be rep1eced by either a solar cell, a solar cell panel,
3 a battery, a fuel cell~ or any o~her electrical ener~y stor-
4 age means. When any such substitution îs made ~or capac~-
5 tors 140 and 150, ~he dlodes 138 and 148 can be eliminated
(assume n=L or Fig. 5~ However, when batteries are substi-
7 tuted for the capaci~ors 140, 150 in many applications it is
8 desirable ~o re~ain the diodes 138, ~48 to permi~ rechargin~
9 o~ ~he batteries a~ such t~mes that the arLalogous one o~ ca-
10 pacitors 140 and L50 are charging, as previous~y described.
11 Similarly~ ~he battery 136 o~ Figs. 5 2nd 6 can be replaced
12 by ei~her a solar cell, solar cell panel, uel cell9 and so
13 forth.
14 In Fig. 7, a high-power s~itching amplifier cir-
15 cui~ is sho~v~, suitable for serving as each one of the
16 s~itches S3 throu~h Sg (see Figs. 4-6)~ 0~ couxse, as 2re-
17 viously mentioned, in Fig. 6 the switches S7 and S8 can each
18 be mechanlcal or elec~romechanical, i~ desired. A detailed
19 e~lana~ion of the operation o~ the switching circuit o~
Fig. 7 is found in my United States Patent No. 4,125,814,
21 granted November 14, 197~, for HIGH-POWER SWITCHING A~PLIFIER.
22 Reierence is m2de ~o Fig. 6 of this high-power s~itching am-
23 plifier application, which figure is ide~tica1 ~o the cir-
24 cuit shown in Fig. 7 of ~he present application~ even as to
re.erence designa~ions. For purposes of this discussion, i~26 should be noted that the swi~ching circuit of Fig. 7 is pre
27 erred ~oruse in providi~g the swi~chin~ unctions o each
28 one of the switches S3-Sg, ~or s~itching current 12vels up
29 ~O abou~ 100 am~eres a~ vol~ages a~ about ~00 volts. For
1 lower power applica~ions, other ~ra~istorized swi~ching
2 circuits can be appl~ed ~or use ~or providing each one o
- 3 the sw~tches S3-S8.
4 In Fig. 7, when a control signal having a positive
leve1 of voltage (hereinater reerred to as a leveL of "l")
6 is applied to the co~trol ~ermlnal 33, ~he NPN Darlingto~
7 amplifier 37~ 39 responds by turning on for substantially
8 connecting output terminal 41 to ground via the main conduc-
9 tion path of the Darlington 37~ 39, and the high voltage in-
verting amplifier 59 responds by producing a low-level or
11 ground signal a~ point A. A~ ~his ~ime~ NPN transistor 83
12 ~s ~urned of~, a~d diodes 62, 63, 65 and 67 are forward
13 ~iased, permitting capacitor 73 to take on charge from the
14 vol~age source supplying the vol~age appLied to operating
vol~age termina1 45, When ~he control signal goes low ~here-
16 inafter referred to as le~el "O", the Darlington amplifier
17 37, 39 turns off, and ~he inverting amplifier 59 responds
18 ~y changing the level of its outpu~ signal to a positive vo}-
~9 tage. When point B is allowed to go positive (no Longer
held a~ a negative po~en~ial), diode 62 becomes back biased,
21 and ~he curren~ flowing through r~sistor 75 flows into the
22 base electrode of and causes NP~ transistor 83 to tur~ on.
23 A~ the ~L~e of ~urnon of transistor 83, the speedup capaci-
24 tor 77 appears as a short-circuit or closed conduction path7
causing resistors 79 and 81 to be placed in parallel a~ ~he
26 instan~ of tuLnon, and curre~t flows ~rom operating terminal
27 4~ through the conduction paths including resistor 81, and
28 resistor 79, in series with capacitor 77, the main conduc-
29 tion path o~ NPN transistor 83 (col7ector-2mitter current
1 path~ ~ in~o ~he base electrode o~ ~PN transistor 27, thereby
2 turning on the Darlington ampliier 27, 29 When the
3 Darlington amplifier 27, 29 so turns on, curren~ flows ~rom
4 the opera~ing terminal 45 through the main current pa~h o
the Darlington ampliier 27, 29 to the output term~al 4
6 raising the level or voltage a~ the output terminal to a
7 positive leve~9 permitti~g capacitor 73 to begin discharging
8 initially through the circuit of resistor 81 in parallel with
9 a series circuit of resistor 79 and capacitor 77, the main
current path of transistor 83, in~o the base electrode o
11 NPN transistor 27. Once the speedup capacitor 77 becomes
12 appreciably charged, it appears as an open circuit, effec-
13 tively removing resistor 79 and itsel from the paral~el con-
14 nec~ion with resistor 81. Therefore, when this occurs, the
effective resistance o the parallel circuit is increased ~o
the value of resistance of resistor 81 through which a~l of
17 ~he current is now passing. The speed~p circuit o resistor
18 79 and capacitor 77 is know~ in the art, enhances ~he turno~
19 time for transistor 83, and accordingly also ~he turnon time
of ~he Dartington amplifier 27, 29. The capacitor 73, while
21 dischaxging into the Darlington amplifier 27, 29, acts to
22 incxease the leve~ o~ vol~age applied to the base electrode
23 (voltage at terminal 41 plus voltage across capacitor 73~ of
24 ~P~ transistor 27 ~o ensure that the Darlington amplifier 27,
29 goes into saturation for s~stantially ap?lying the opera-
26 ~ing vol~age connected to terminal 45 to output terminal 41.
27 Resis~ors 69 and 38 are current-limiting resistors, and re-
28 sistor ~1 ser~es as an isolation resistor.
- - 13 ~ S~
1 Assume tha~ each one of the switches S3 through
2 S8 are provided by a transistorized switching circuit such
3 as sho~n in Fig. 7. In such a case, six individua1 cont~ol
4 signals herein designated ag C3 through C8, m~s~ be ~pp~icd
to the respective control terminals 33 of each one of the
6 switches S3 ~hrough Sg, respec~ively7 for opera~ g these
7 switches ~o produce a desired waveform. A controller~ such
8 25 the block 152 shown in Fig. 8, is required to supply the
9 control sign~ls C3 through C8. In ~hose applications where
programmability is not im~ortant, that is, where only a
11 single waveform is desired to be synthesized rom a DC vol-
12 tage sou~ce 136~ ~he controller 152 can be hardG~red digital
13 logic. I it is requlred that any given one of a plurality
14 o~ waveforms be synthesized at a given time, the controller
15~ can be provided by a microprocessor, the microprocessor
16 being programmed for producing the desired waveform. As
17 s~own in th~ State Table given below, the level of the out-
18 put slg~al produced across a load for different combinations
lg of a "1" state or "0" state for the control signals C3-Cg
for Figs. ~-6, ara as follows:
5~Z
~l~
o ~ , o ~ o
~t
a: o
vl I ' ~ ' ~ ' ' ~ I I I I ,~oc~oooooo~,s
~` s~t
~ ~ IIIIItI ooooooooo~,l o
~
~ ~ ~t~OO ~O~l~1000 ~1~ 0~0000
V~ ~ . ~
O ~j T~ o o ~l r~ 0 0 0 0 0 ~1 ~1 ~ 0 0 O O O ~I C: 5
~o~
~1 0 ~ ~ ~ ~ ~ ~1 0 0 0 ~! ~1 ~ 0 0 ~1 ~ 0
~ o
al c~
E3 ~ W
o ~ a o ~ o
æo~ z;o~: æc? - ~,
~3
æ
- 15 -
~5~
1 The high power switching amplifier circuit of
2 Fig. 7 is an inver~ing switching amplifier. Accordingly, i~
3 a noninverting transistorized swi~chi~g ampll1er is applled
4 for use for providing ~he swi~ching ~unc~ions o~ ~he
switches S3 through Sg, the levels o the control signals
6 given in the S~ate Table above must be inverted~ that is,
7 "1'l levels will become "O" levels, and "~" levels wi11 be-
8 come "1" levels.
