Note: Descriptions are shown in the official language in which they were submitted.
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BACKGROUND OF THE _NVENTION
This invention relates to an incre~ental phase
tracking position measuring system.
Description of the Prior Art:
In many applications it is required to con~ert
angular displacements into digital information. In numerical
control applications for example, resolver angular displace-
ments are converted to a,b,inary representation of the shaft
position, and pulses are generated which are a function
of the shaft displacement. Conventional phase
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measuring systems, using analog voltage controlled
oscillators to perform this function, require considerable
maintainance and special care to preserve accuracy.
The present in~ention relates to an incremental
phase tracking position measuri~g system. Means are pro-
vided for generating a phase feedback error signal which ~:
is a function of the displacement of a rotating shaft.
Counting pulse means are provided. Means are connected
to the phase feedback error signal means for generatingADVANCE or RETARD pulses ~or application to s~id counting
means to bring the zero state back to coincidence with
the leadlng edge of said phase feedback error signal,
whereby the number and 9ign of said ADVANCE or RETARD is
a ~unction of the incremental displacement of said ro-
: tating shaft.
~0
Figure 1 is a block diagram of the phase to ':
incremen~ converter in accordance with the invention, and
il~ustrating its u~ ation in a numerical control en-
vironment
Fig. 2 is a simplified block diagram of the
phase tracking counter in accordance with the invention;
Fig~ 3 15 a table used in explaining the phase
track count sequence;
Fig, l~ is a more detalled block diagram of the
phase tracklng counter of Fig~ 3;
Fig. 5 is a table of the addresses and outputs
o~ the read-only memory (~OM) porti,on of the phase tracking :~
counter o~ Flg. 4; :~
Fig~ 6 is a block diagram of the phase error
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register the pulse rate ~ultiplier, and the ad~ance
and retard flip flops in accordance with the invention;
and
Fig. 7 is a block diagræm of the logic circultry
for generating preset and ad~ance a~d retard signals for
the ROM addresses.
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Referring now ~o Figure 17 the resolver phase ko
digital converter system of the in~ention, indicated
generally at 10, is here illustrated in ~he environment
of the numerical control of a machine tool indlca~ed gen
eral~y at 12~ Typically, the machine ~ool 12, w~ich may
be a planner mill or the like9 is actuated through a dri~e
gear box 1~ which is drlven by a motor 16. A compu~er 1
controls the rotary displacemen~ of the drive motor 16
through a drive amplifier 20.
A rotary control tr~nsformer (RCT) ~ndicated gen-
erally at 22, has its rotor ~ha~t coupled to precision
gearing 24 to receive a shaft a~gular displacement ~ which
ZQ is a ~unction of the linear axial displacmen~ of the lead
screw of the machine too~ 12~ The electrical output o~
~he rotor ~ R2 of the resolver 22 is-sent to the phase
to digital converter indicated generally at 26.
Two sine wa~es are required to exoite the stator
~lnding Sl S3; S2 S4 of the rotary control trans~o~ner 22~
The sine waves must be ninety degrees apart or in quadrature.
It is of extreme importance tha~ this qaudrakure relatio~
ship as we~l a~ the matching of the amplitudes of the
sine wa~es7 be maintained wlth a high degree of precision~
These wa~es may be generated in any convenien~
and inexpensi~e manner so long as the requisite phase
accuracy is main~ained~ Advantageously9 a pulse width
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modulation techni~ue may be utilized such as taught
in an article entitled "Reduce Statis Inver*er Weighk
and Cost by Ha~oni c Neutrallzation" ~ Pl, W~, E~etsch
appearing ~n the publication EDN on January 15, 1971.
Pulse wid~h modulated sine and cosine PWMSIN and P~MCOS
are applied to ~he s~ator winding oP RCT 22 throllgh
d~Lvers 2g and 30 9 respectively.
For phase encoded resolver pos~tion measurementt
the two stator windings Sl - S3 ~nd S2 - S~ of the rotary
control transformer 22 (which are physically w~und to
pr~duce flux ve~ors in spatial quadrature) are excited
wlth fixed frequency identical ~mplitude A~o signals
P~SIN, PW~COS which are in t;~mporal quadra~ure~ iOe.,
shi~ted in time b~ 90~ The resulting rotor output ~ R2)
is a conskant amplituds AoC~ ~ignal whose phase, with
respe~t to one of ~he excitation A~Co signals, is linearly
proportional to the rotor shai~t position,el OI the RCT 22"
The ou~pu~ o~ the rotary control transformer 22
is a ~omplex wa~e having a number of harmonics ~hich are
the inherent result of generating a square wave, in
addition to those contributed b~ the non-linearity of the
RCT 22 itself. Interest is only in the ~u~damental which
is of cons~an~ ampl~tude~ ha~ing a nominal frequenc~ of
2000 Hz, which move~ along as the rotor shaft turns, that
is, if we synchronize on the sine wa~e, ths phase wll~
shi~t forward or backward in time as the sha~t ro~ates
in one directlon or the otherO ~liS iS identi~iable
by the ~ero cro~sing of the sine wave~
The O~l~pUt of the RCT 22 is fed to a di~ferential
amplifier 32 and then to a filter 3~ The lines RESF~ and
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RES~B2 represent the two sides of the ro~or coil
~ ~ the actual signal being the voltage dif~erence
between th~n~ The signals are passed ~hrough the
dif~ere~ial ampli~ier 32 ~or common mode rejec~ion
and for scaling to the proper amplitu~e for the fllter
3~ Th. ~llter 3~ ef~ectively re~ects the higher har-
monics which are ~iding in the phase encoded signal.
The filtered output is passed to a zero-
crossing detector (ZCD) 36 and ~o a synch~oni~ing cir-
1~ cuit indica~ed generally a~ 36, where the phase datais extract~d from the fundamental, con~erted to a
digital logic level by the ZCDp and is then synchronized
to -the system clock which accomplished the quantization of
the otherwise smooth ~arlation o~ phase with resolver shaft
positio~O The fil~ered outpuk i8 fed to khe ZCD 36 be-
cause 1~ is desired to square the ware -- the only
intere~t Ls in phase and not the amplitude o~ the signal.
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The squared ~eedback phase synchronized signal (F~PS)
is effectively compared with the phase output of a phase track-
ing counter 3~ to develop a digital phase error -~ a binary
number representing the magnitude and direction of the phase
error. m e measurement is accomplished by using the leading
edge of the synchronized digital pulse to strobe the contents
o~ the f~ee r~uming phase tracking counter 38 into the phase
error register. As will be explained, the counter 38 is con-
tinuously counting and has a special count sequence (implemented
by a read-only memory (ROM) and some counters). The special
count sequence is arranged so that when the phase tracki~g ~-
counter 38 and the phase feedback are in phaset at the occur-
rence o~ the leading edge of the phase feedback signal the
contents of the counter 38 are zero. When the phase trackîng
counter 38 is behind the pha~e feedback from the resolver,
ad~ance pulses are sent to the counter 38 to cause it to
catch up; conversely, when the counter 38 is ahead of the phase
feedback ~rom the resolver, pulses are sent to retard the
counter to slow it down. m e number o~ advance or retard
pulses sent to the counter 38 is a functlon o~ how far the
res-~lver shaft has been displaced.
A phase error register 40 is connected to the
phase tracking counter 38. When the feedback phase synchronized
(FBPHS) signal strobes the contents o~ the phase tracking
counter into the phase error register 40 9 the contents o~ th~
register (oalled a phase/error PHFR word) represents the
magnitude o~ the phase error at the tome o~ strobing or
sampling.
me phase error word PHER is coupled tQ a
pulse ra~e multiplier (PRM) and synchronizing circuit 42.
The PHER word controls the pulse rate multiplier (P~M) 42,
generating a ~requency proportional to the magnitude of
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the PHER word. This frequency, in conjunotion with
the sign of the PHER word9 gen~rates counk up ~CTUP)
or count down ~CTDN) pulses cau~ing the ph~se tracking
counter 3~ to phase adva~ce (AD~ or phase rekard (RET)
(by counting by tw~ for one clock time or by remainin~ ~ :
in the same count sta*e for ~w~ clock time~ respectively)~
In this manner the count pulses cause:th~ pha~e of the
phase tracking counter 3~ to track the phase of the
resolver ~eedback signal* Thus if the pha~e error is 10
counts behind, the P~M 42 will send out 10 ADVANCE (CTUP)
pulses to the phase track counker 3~. Howeverp these
pulses will ~ot be sent in a bunch, but instead will be
evenly spac~d in the time between the times of the strobes
by the FBP5 signal. Sta~ed dif~erently, 10 count pulses
will be evenly supplied in the time between the times when
the leading edges of the FBPS signal goes ~rom O to ONE
(marked on the FBPS signal by the x's in Fig. 1), :
The count pulses CTUP, CTDN also go to the
de~a position counter (DELPOS) 44 and to theta
counter 46 where they are accumula~ed. m e accumulated
magn~tude in these counters 44, 46 is read into the
computer 1~ upon signal ~rom the control logic 4~. The
lo~c ~ is controlled by the inpu~/output signals from
the aomputer 1~. The logic 4~7 inter alia~ slgnals
the read out and reset control ~or the DELPOS counter 44.
Upon a signal ~o control logic 4~ from the computer 1~,
the register of ~he DELPOS courl~er 44 is read, ~ha~ is,
a 16 bit word is trans~erred ~rom its register to an
accumulator in the computer 1~, and the counter 44 is
reset to ZE~O. The counter 44 is a delta or incremental
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reading which indicates how ~ar khe resolver 22 has
mo~ed since the las~ reading. The counter 44 accumulates
pulses until the computer lB signals read out and then
resets it to begin the cycle again.
The theta counter 46 ls never reset e~cept at
power turn on t~hen it is synchronized with the electrical
ze~o o~ the resol~er 22. I~ ~eeds its in~ormation into
the ~ompuker 1~ upon signal ~rom the control logic ~
The theta cou~er 46 indic~tes the absolute rotar~ position
o~ the sha~t during 360 of revolution~ From counter 46
the resolver shaft position is known between 0* 60 of
reYolution~ The computer 1~ keeps track o~ the number
o~ revolutions by sampling the register o~ the DELPOS
counter 44.
The phase traoking counter 3~, shown schematically
in Fig5 2, comprises a read-only memory ~ROM~ 50, a ~ ;~
plurality of M ip ~lops indlca~ed generally at 529 and
two 4 bit binary up-do~ counters 54, 56~
The output oP the counter is 11 bits: K~A~B~C7D~E9
F,G,H~I~J. K is a 5ign bik, A is the least significant
bit, and J is the most significant bit. The ROM 50 and :.
the flip ~lops 52 control the state of the counter 3
The bits A to J have the weighted magnitudes
indicated ln Fig~ 2. Since thls is binary notation~ the
counter can count from O to 1024 in each direction ~or a
tot,al of 1024 x 2 or 204~ statesO
Only 2000 state~ are desired, 90 when t,he counter
reaches +0, it is preset ko -1~ and when the counter reaches
-1000 it is prese~ to ~999. This is accomplished b~ the
ROM 50 which is addressed ~ ~he bits X,A,B plus two
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additional ~its~ a retard or prese~, and an advance or
preset.
The preset function i5 performed as ~ollows.
Referring now ~o ~ig. 37 when the counter is counting,
the K bit identi~i0s the direction o~ count. For exampley
when the count sequence is ~7~6,~5,~ e~c. K = O; when
the count se~uence is ~ 2~-3~ etc~ K = lo The ROM 50
is also cognizant of the addresses ~ (A bit), Al(B bit)
plus A3 (retard or preset~ and A~ (advance or preset)t
From logic circuitry which will be explained in connection
with F~go 79 when the preset conditions are approached
~i~e~ -1 and ~999) ~ and A4 become ONES ~the sa~e logic
signPl occurs as both states are approached~ ~uk these
states are numerical~y far enough apart so no am~iguity
obtains). The RO~ 50 is pro~rammed so tha~ when K = O
and a preset conditio~ is indicatedt the coun~er continues
to count until A=O BbO - the ROM 50 now gi~es the
appropriate output a~d the counter is at ~l. As will be
seen fro~ Fig~ 3, -1 ~8 like ~l except that the sign bit
%O has changed, K now equals ~lo ~imilarly, when it -Ls
desired to preset to +999~ ~ and A~ are O~ES as pr~viously
explained) the counter is at K~l, and when A=O B-O~ the
ROM will provide the correct output and the counter will
move to ~999 -- K is now O. Note a~ain ~999 is like
-999 except that the sign bit has changed~
When the trac~ln~ counter 2~ and the *eedback
~PS are i~ phase, at the occurrence o~ the lead:ing edge
of the phase feedback signal, the contents of the counter
3~ are æeroO When the counter 3~ is behind the phase-
~eedback ~rom the resolver ADV~NCE pulses are sent tothe coun~er 3~ to catch upO Conversely~ when ~he counter
3~ is ahead
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of the phase feedback ~rom the resolver 22~ pulses
are sen~ to R~TARD the counter 3B to slow it down. me
ADVANCE and RETARD conditions are also illustrated in
Fig. 3~ When an ADVANCE is sent to the counter 3g, it
skips one state and goes to the next~ When a RETARD is
sent to the coun~er 3B it remains at the same state instead
of moving on to the nex~ st~e. The number of advance
or retard pulses se~t to the counter 3~ is a ~unctio~ o~
the angular displacement of the rotor sha~t.
The phase trac~ing cou~er 3~ is shown in grea~er
d~tail in F~g. ~ The~flip ~lops generally identified
as 52 in Fig. 27 are now ~ur~her identified as $~60962764
and 66,
The RO~ 50 is progr~mmed ~o have the de~initi~e
outputs ~ - Q7 when addres~ed at ~ Al - - A~ as shown
in ~ig. 5. Duri~g a normal counting ~ A~ are ZEROES. ~en
presetting to either -1 or ~999~ both ~ and A4 are ONES~ ~
When an ADVANCE pulse is indicated~ ~ = ONE and A4 ~ Z~RO.
When a retard pulse is required these positions are rerer-
sed viz. ~ = ZERO and A4 - ONE~
The RO~ 50 outputs Ql to Q7 are shown in Fig. 5~
The Q4 output provides CTEN which iæ a count enable signal
to counter 54~ The Q5 output DN provides ~he direction,
that iS9 when DN=O the count is up, and when DN=l the coun~
is down. Q6 and Q7 provlde the next cou~t up (CTUP) and
the next count down (GTDN) signals r~spe¢tiv~ly which are
applied to driver 6~ in the cir¢uitry o~ Figo 60
In F$g. 6 there is shown the phas~ error
register 40, the pulse rate multiplier 42 and the advance
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and re~ard flip flops indica~ed generally a~ 700 The
phase error register 40 stores the 11 bits ~rom the phase
track ¢ounter 3~ ~Fig. 4) at the time th~ the ~eed~ack
phase synchronized (~PS) signal goes iErom a zero to a
one~ By virtue of the par~icular ~ount sequence Or the
phase kraok counter 3~ the re~ulting contents o~ the
phase er:ror register l~û contains bo~h the mag~itude and
the si~n of the number o~ up or dowrl counbs re~uired to
ADVANCE: or RETARD the phase track counter 3~ back inko .
10 s~nchronism w~th the feedback phase ~ynchronized ~BPS)
3ignal. ;~
The phase error register 1~0 stores the state
o~ the phase tracking counter 38` at the time the feedback
phase synchronized signal goes ~r~m zero to oneO The
pulse rate multiplier 4~ receives the bit inpul;s A.. J~ :
The ~ bit out o~ ~he phase error register will be identified
as PHERPL aIld this is applled to khe flip ~lops 70D
The required number of pulses are not generated
i~ one quick burst but are e~enly spread out during the
period o~ t~me before the next leadi~g ed~e of the E~PHS
signal goes ~rom zero to oneg l~e. duri~g the 500 micro-
seconds betwe~n the leading edges of the 2000 Hz signal.
The pulse rate multiplier 42 i8 a binary coun~er
connected to a plurality o~ gates, one ~ate for each ~tage~
The outputs are indicated in Figa 6. For example 1/16
means that one of out o~ 16 will be gated out~ 1/32 means
that one out of thlrt~r two ~rill be gated ou~, etcO The
outpu~ frequenc~ ~ of the pulse rate multiplier i~
~o = 4MH~ x PHER
where PHER is the phase error magnitude~ Thusq i~ the
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phase error magnitude is 1, ~O will be approximately2000 Hz or 1 pulse in the 500 microseconds between the
leading edges of the FBPHS ~i~nal.
Although ten bits are used for the PHER magnil;ude~
normally the higher magni~ude blts will only be u~ed ~hen
initially synchronizing the phase ~rack counter 3~.
Each pulse ~o out o~ the pulse rate mul~iplier
is a re~uest ~o advance or retard the pha~e track coun~er.
me ~lip ~Op 70 compr~se tw~ D flip Mops 72 a~d 72~ .
These two ~lip ~lops act as bu~fers ~or the requested
change to the phase trac~ing counter 3~ until the proper
state o~ the counter 3~ allows 1;he CTUP or CTDN to reset
the ~lip ~lops
li~en the phase e~r i~ tZEP~o~
When a clock pulse arri~es~ AD~ANCE ~ ~NE~ iOe. in flip
~lop 72 ~ Q ~ O. At the same tlme ~ETARD - ZERO~
i~e~ in flip flop 74 Q = ZERO a~d ~ - ONE~
When the phase error is -, P~E~ is ~ (ONE).
When a clock pulse arrives~ RETARD ~ ONE and ADV~NCE = ZERO.
- 20 In the r~ard ~lip ~lop 74 Q = ONE ~ - 0~ In the advance
f~ip flop 72, Q = ON~g ~ z ZEROv Whe~ CTUP and CTDN
occur~ the AD~ANCE and RETARD ~lip Xlop 72g 74 are reset.
The ADVANCE and KETARD signals are applied to
the logic circuitry of Flg~ 7. The advance pulse is
applied to OR ga~e 76 and the retard pulse is applied to
OR gate 7~ The ~ bits a.DEFGHIJ are applied ~o DECODE~
LOGIC ~0 the output9 PRESET -001~ PRESET ~999 bo~g
applied to OR gates 76, 7~ The output oX ths OR gates
are applied to the ROM 50 of the phase tracking counter 3~.
The decode logic ~0 outputs, two on~s at both
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PRESET -OOl and +999, as well as ADVANCE OR RETARD ONES
as explained above. The OR gates 76, 78 develops a ONE
output if there is a ONE at any one of its inputs.
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