Note: Descriptions are shown in the official language in which they were submitted.
~ 5~1~ RD-9838
PROGRAI~ABLE ENE~GY LOAD COL~IT~OLL~ SYSTE~I Al~D ~ETHO~S
Background of the Invention
The present invention relates to systems and methods for
controlling energy loads and, more particularly, to a novel
programmable energy load controller system and methods capable of
establishing the energy consumption state of a multiplicity of
devices in accordance with one of a plurality of programmable
maps.
It is known that the quantity of energy consumed, and
the cost thereof, in a building can be minimized by allowing
energy consumption to occur only at such times as benefit can
be obtained therefrom. One approach to minimization of
energy consumption in a building, such as an office building
and the like, has been to utilize one or more employees, moving
through the building, to switch off those loads which
represent non-beneficial energy consumption. This approach does ;
not, however, provide rapid control of energy consumption, due to
the difficulty and expense of having personnel present at all
loads at all times. An automatic system for controlling ~-
the energy loads is thus desirable.
-20 Brief Summary of the Invention
In accordance with the invention, there is provided
a programmable energy load control system for controlling
the energization and de-energization, as well as the
establishment of a particular one of several levels of
energization, of each of a multiplicity of energy loads.
A central microcomputer facility includes a data storage memory of
size sufficient to store a plurality of energization maps,
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indicative of the energization state of all of the loads at
a particular time. The output of a real-time clock is
compared to the implementation instruction for each map
to cause the proper map to be implemented at the appropriate --
time, whereby each load is controllable to a deenergized
condition or to a selected energized condition of a set
of at least one such energized conditions. Battery backup means
are utilized to maintain the timekeeping function of the real-
time clock in the event of a power failure to the system;
the clock is also addressable and may receive data from a
user interface device, such as a data terminal and the like,
to allow for entry of the correct time at system initialization.
The user-interface device is also utilized to write program
and load energization change information into the microcomputer
facility memories; a separate interface allows a person at
a remote location to access the central facility via the
building's normal telephone lines to request temporary load
energization changes at that, or another, location on a priority
basis.
The central facility is coupled in electrica~ parallel
connection to the input of each of a plurality of load control ~ -
processors (LCP), each having a receiver/decoder with a unique
address and means for controlling a plurality of energy switching
devices located in the area adjacent to each LCP. ~- -
In one presently preferred embodiment, data is sent from
the central facility to the paralleled LCPs in an error-self-
checking format with each byte of addressed data being first trans
mitted in a complementary (inverted)form and thence in a true ~orm,
and with each LCP's receiver/decoder containing circuitry for
storing the inverted byte for comparison with the true byte :
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and issuing a reset to prevent enablement of operations
requested by functional data bytes, if similarly ordered bits of
the data-true and data-complement bytes are identical. The par-
alleled LCPs are driven by a media interface means having the
capability for also providing a signal which causes all of the
LCPs coupled thereto to enter a powersaver-mode, whereby a major
portion of the LCP circuitry is deenergized, to reduce power con-
sumption (and protect and increase the reliability of the compon-
ents on the LCP) during time intervals when load changes are not
being actuated. The central facility is configured to selfload
the user-defined maps (plus any user-defined sectors and map
schedules) stored in a magnetic t~?e unit, and also
to operate in a power-up reset mode, whereby that one of a mul-
tiplicity of load-energization maps, then called for by the timing
lS in~ormation available from the real-time clock, is enabled to
define the state of each load controlled by the system, after
a power outage.
One preferred embodiment of this system is utilized
for controlling the states of a plurality of electric
lighting loads in a building, whereby each load may be
set to a predetermined state, e.g. on or off, by means of
relays (referred to hereinbelow as the "relay" mode).
As defined hereinabove, a second mode (hereinafter referred
to as the "fixture" mode~can also be programmed wherein each
lighting load has several discrete energy utilization states,
such as a lighting load of the fluorescent-dual ballast type
wherein each fi~ture is controllQd by a pair of relays to one
of three states: "Off" (both relays off); '~ow" light intensity
(one relay "on" and the other relay "off"); and "High" light
intensity (both relays in the"on"condition). Each load
control processor, having 16 output lines in our preferred
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embodiment, can control 16 lighting loads in the "relay"
mode and 8 fixtures in the "fixture" mode, wherein each
fixture requires two relays. Each of the relays is of the
conventional self-latching type, whereby the relay will retain
its present state, "on" or "off", until a new signal is
applied thereto to change the state thereof.
In our preferred embodiment, the system causes the
lighting load to be energized in selected patterns, under either
a "MAP" mode or a "SECTOR" mode. In the "MAP" mode,one of a plurality
of maps, each specifying predetermined states or each load,
is programmed to be initiated at a specific time during specific
days of the week; ~he maps are sequentially activated to be
operative during a predetermined time interval. In the "SECTOR"
mode occupants of the building are enabled to override by remote
control, portions of the load patterns then currently in effect
and established in accordance with the "MAP" mode.
Preferably, this remote control "SECTOR" feature is
accomplished by telephone interfacing with the central
facility. Each lig~ting load in the building is assigned
to at least one (and preferably several~ sectors, each having
a predetermined sector number and controlling a specific
group of loads. A building occupant utilizes a desired
sector number to modify the fixture energization patterns
in a particular area, as required and to incorporate greater
flexibility in lighting usage.
Accordingly, it is an object of the present invention to pro-
vide a novel programmable energy load controller system and
methods capable of automatically controlling the energy
utilization state of each of a l~ultiplicity of loads.
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Another object of the present invention is to provide a
programmable energy load controller system capable of storing a
multiplicity of energization patterns affecting every controlled
load in the system and placing a particular loading pattern into
effect at a predetermined time.
Yet another object of the present invention is to provide
a programmable energy load control system with capability to
allow user modification of the state of individual portions of
a pattern without affecting the remainder of the load energiza-
tion pattern then implemented.
Still another object of the invention is to provide a
novel system having means whereby a remote user can initiate a
local override of an existing load pattern via an existing
telephone system in the building served by the system.
A further object of the present invention is to provide a
novel programmable energy load controller system capable of auto-
matically energizing each of a multiplicity of energy loads con- ;
trollable thereby to a proper condition upon restoration of power
to a system from which power was previously accidentally removed. ~
These and other objects of the present invention will become `-
apparent to those skilled in the art upon consideraton of the
following detailed description taken in conjunction with the
drawings.
Brief Description of the Drawings
Figure 1 is a block schematic diagram of a novel programmable
energy load controller system in accordance with the principles
of the present invention;
Figure 2 is a hypothetical building floor plan, useful i~
defining certain concepts relating to the present invention;
Figure 3 is a memory map for the system addressable memory;
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.,,~L"~., ,~.
Figure 4 is a program flow chart for one possible procedure
allowing definition of energization states of all loads in each
of a plurality of map sectors;
Figure 5 is a map or a portion of memory data base, illus-
trating the manner of storage of sector-definition in~ormation
- therein;
Figure 6 is a program flow .chart for one possible procedure
for defining each of a plurality of energization map patterns;
Figur.e 7 is a map of a portion of the memory data base, il-
lustrating the manner of storage of map definition informationtherein;
Figure 8 is a program flow chart illustrating one possible
procedure for loading a timing schedule into the data storage
memory;
Figure 9 is a memory map illustrating the manner in which
time schedule information is stored in a portion of the memory
data base;
Figures lOa-lOf comprise a program flow chart for one pre-
ferred central system executive procedure for managing the large
20 data base and coordinating the system activities; :~
Figures lla-lli comprise a program flow chart for one pre- .-
ferred procedure for servicing a remote load energization change
request received via the telephone interface;
Figure 12 is a program flow chart for one possible boot-
strap, or system-initialization, routine;
Figure 13a is a schematic diagram of one embodiment of a
media interface for use in the system;
Figure 13b is an illustration of the transmitted data for-
mat used in one embodiment of the system;
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Figure 13c is a block diagram of one embodiment of load con-
trol processor utilizable in the system of the present invention:
Figure 13d is a circuit diagram of the receiver/decoder
circuitry of the load control processor of Figure 13c;
Figure 14 is a schematic diagram of one embodiment of a
powersaver-regulating power supply circuit utilizable in the
load control processor of Figure 13; and
Figure 15 is a schematic block diagram of one embodiment
of a real-time clock for use in the system.
Detailed Description of the _ ention
An overall block diagram is shown in Figure 1 of one pres-
ently proferred embodiment of a novel programmable energy load
controller system 10. A central facility ll, shown generally
to the left of the vertical broken line, comprises a microcom-
puter 12, such as a standard INTEL MDS-800 microcomputer, con-
taining a central processing unit (CPU) 12a; read-only-memory
(ROM) means 12b (of about 6 kilobyte capacity), typically
an INTEL MDS-406 PRO~I module in the microcomputer; read-write
random-access-memory (RAM) means 12c (of about 17 kilobyte capa- ;
city); and an input/output (I/O) means 12d includir.g I/O means
in the MDS-800 plus an additional INTEL MDS-504 I/O module in
the microcomputer. The microcomputer also contains
suitable multi-wire signal path structures, commonly
known as a data bus 13a, an address bus 13b and a control
bus 13c, interconnecting the CPU, ROM, I/O and RA~I means, and an
I/O bus 13d coupling the C'~U and I/O means. The various parallel
bus structures 13a, 13b and 13c are coupled to a mass data storage
means 14, which may be a magnetic tape transport and controller,
a magnetic disk, data cassette transport mechanism and the like,
for storage of large quantities of data which may be written into
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and read from data storage means 14 via detectors 13a, under
control of CPU 12a. Data storage means 14 may be physically
located within microcomputer 12 or adjacent thereto, with proper
coupling of the data, address and control buses thereto.
The data bus 13a is of the bidirectional type, whereby data
may be read from data storage means 14 into temporary data storage
means such as RAM 12c, or vice-versa, under control of CPU 12a
and programs executed therein, in manner known to the computing
arts. Data may be received in the microcomputer 12 via a
parallel and/or serial input bus (or buses) 15 from sources
external to the microcomputer.
Also contained within microcom~uter 12 is a real-time clock
module 20, utilizing a high-stability crystal element 21, to
continuously and accurately establish the time-of-day (TOD) and
lS day-of-week (DOW). Real-time clock means 20 is coupled to
bidirectional data bus 13a at clock data port 20a, to address
bus 13b at clock address port 20b, and to control bus 13c, at
clock control port 20c, to facilitate entry of clock starting
time data upon energization of the load controller system of the
present invention, and to facilitate reading the TOD and DOW
data from clock means 20 when the clock means is interrogated
with address codes, at port 20b, corresponding to the unique
address codes previously assigned to the clock. Real-time clock
means 20 is advantageously fabricated upon a printed circuit
board, or other like means, o similar size as that used for
mounting the components of the other portions of the microcom-
puter, and the real-time clock means, along with its timing
element 21 and a rechargeable battery means 29, is physically
positioned within the confines of the microcomputer at the
central facility.
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RD-9838
A power supply means 25, typically a part of the basic
MDS-800, is coupled to the AC power line 26
in the building housing the central facility and is coupled to
the microcomputer 12, via connections 27 and 2~, to provide
the required operational voltages and currents. nc. power
connection 28 provides the real-ti.me clock with operating power
derived from the commercial power means, and is coupled to a
back-up battery 29 via a battery charging circuit 30 which al-
lows charging current to flow easily in the direction of the
battery such that in the event that AC mains power is lost for
any reason, the battery is isolated from means 25 and remains
coupled only to real-time clock 20 to assure that the timekeeping
function of the clock is maintained. Upon reestablishment of
mains power, a bootstrap program (discussed hereinbelow) directs
the CPU to place on address bus 13b the sequential addresses of
the clock portions storing TOD and DOW data such that the system
will then implement the load energization pattern required for
that particular time.
An operations console and interface 35, such as a General
Electric TERMINET 3 ~ data terminal and the like, is generally
physically located near the central computer and is coupled to
the I/O bus via bus portion 15a and thence to I/O means 12d of
the computer. Console 35 allows system personnel to load, debug
and/or modi~y system programs as well as perform computer
diagnostic routines, as required, and in manner known to the art.
A telephone interface means 37, such as a standard AT&T
407A data set and the like, receives tone-coded serial data,
coupled via bus 38 to a telephone line 39, which may be a ded-
icated telephone number in a building-wide telephone system and
the like, and decodes this data prior to coupling the data via
_g_
.
g8 38
a portion 15b of the I/O bus to the computer, in manner known
to the art.
The central facility is substantially completed by
a media interface means 40 se:rving to couple a portion
15c of the I/O bus to transmission media 45 serving to carry
signals representative of data to and from the central facility
and the inputs of each of a plurality of remotely-located
load control processors 50-1 through 50-M. Media 45 is
preferably a cable running between media interface 40 and
each of the parallel inputs of the load control processors 50.
In our preferred embodiment, transmission medium 45 is
a pair of twisted wires, although a coaxial cable may be
equally as well utilized.
Thus, I/O means 12d may ha-~e at least the following I/O
port assignments:
I/O PORT ASSIGN~l~ENT TABLE
PIT I~O. CONTROL LINE ASSIGNI~NT ADDRI~SS
1 Output Termine ~ and Mass OF7H
Storage Control
2 Input Termine ~ and Mass OF7H
Storage Status
3 I/O Termine ~ and Mass OF6H
Storage Data -
4 Input Mass Storage Status 023H
Flags
Output LCP~ Data OF4H
6 Qutput Interface Data OF5H
(PSUR, etc.)
7 Input Interface Status OFjl7
8 Input Telephone Data 021H
9 Input Telephone Interface Status 022H
Output Telephone Interface 021H
- Control
`~
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3.~ ~
~-9838
Each load control processor 50 is assigned an address
unique to that load control processor ~LCP), even if more
than one load control processor is physically located at
the same location within the facility. Each of load control
processors 50, when properly addressed and enabled, decodes
function data transmitted from the central facility thereto,
for energization of combinations of the LCP output lines 51
to enable or disable one of a plurality (n) of loads 52
coupled to each LCP. Additionally, in our preferred
embodiment, each LCP is configured to not only enable and
disable energy con~umption by one of the _ loads coupled
thereto, but also, when our energy load controller system
is utilized for controlling lighting functions and the like,
to enable each lighting load (a single fixture, bulb and
the like) to one of a plurality of different energized
conditions. Thus, where a single lighting fixture contains-
a lighting load capable of being switched between the l-off't `
condition, a low-light "on" condition and a high-light "on"
condition, the load control processor associated with each ;~
such load is configured to properly place that specific load
in the desired one of the plurality of possible energy
consumption states.
In our preferred embodiment, each of the Mxn loads is
a latching relay associated with either the on-off function
or a high lighting level1low lighting level function of each
one of a plurality (Mxn/2) of lighting fixtures provided in
at least one building to be controlled by our novel system.
The number of fixtures controLled by a single LCP is related
to:the numbel- of states of energy consumption definable
per fixture; the number of bits in a data word defined for the
particular CPU utilized in computer facility 12; and the
number of function words to be transmitted in a single
message to the paralleled plurality of LCPs; and the particular
design of the LCP. In the
RD-9838
embodiment herein illustrated, the INTEL MDS-800 microcompu~er
utilizes the well-known 8080 CPU integrated circuit, for which
the data word is defined as being 8 bits (1 byte) wide.
We have arbitrarily chosen to send only two data words
be sent in serial fashion to each uniquely addressed one of
the LCPs; each lighting fixture requires information contained
in two binary data bits (the "on-off" function bit and the
"high-low" function bit) whereby the on/off" states of a set
of eight fixtures a-;e controlled by a first data byte and the
'on-hi/on-lo" states of the eight fixtures are controlled by
the second byte of the preferred two-byte sequential data
function message. Of course, it should be understood that
other CPUs may be utilized, whereby a particular data word
may have more or less bits and that a single data word,
or more than two data words in succession, may be as easily
transmitted to the paralleled multiplicity of LCPs; other
microprocessors CPUs are well known to the art, having four,
twelve or sixteen bit data words, and minicomputers and large
mainframe computers having data words up to at least ` ~`
sixty-four bits are also known-these CPUs may be utilized
within the intent and spirit of the present invention.
It should also be understood that other specific load control
coding arrangements may be utilized, e.g. a lighting load
having an "off" and three "on" conditions (such as a common
three-way incandescent bulb and fixture therefor), which :~
four energy utilization state combinations may be coded
with the appropriate ones of the four possible combinations
available from two sequential binary dig.its. : .
Similarly, other common non-lighting types of energy
consumption loads may be controlled to a lesser or greater
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degree of possible states, e.g. air conditioning duct dampers
may be controlled to one of eight air-flow positions, including
zero air flow, by suitable choice of combination of three
binary digits in a data word, and so forth.
Referring now to Figure 2, the floor plan of a hypothetical
building provided with the energy load controller system of the
present invention, is shown for purposes o illustration of
several of the principles and definitions associated with the
invention. As seen in Figure 2, there are three offices
(office no. 1 in the upper left hand corner, office no. 2 in
the lower left corner and office no. 3 in the lower right
corner), two rooms (room no. 1 at the center left and room
no. 2 at the upper right)and a central corridor. Each
of the corridor, rooms and offices contains some number of
fixtures, with up to eight fixtures being associated with a
particular load control processor. Thus, fixtures Fl-F8
at the left end of office no. 1 are associated with a
first load control processor Ll, while the remaining
six fixtures Fl-F6 at the right side of the office are
associated with a second load control processor L2.
Similarly, the eight fixtures Fl-F8 at the upper end of
room no. 2 are to be controlled by a third LCP, L3; the
eight fixtures at the lower end of room no. 2 are to be
controlled by another LCP,L4; the eight fixtures
in both the corridor and room no. 1 are assigned to a
fifth LCP, L5, and the left half of office no. 2 is to be
controlled by LCP-L6, with the right half of the same office
being controlled by LCP, L7 and office no. 3 having all of its
eight fixtures controlled by another LCP,L8. It is seen
that a load control processor may, but need not, have a
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full complement of loads coupled thereto, as shown by
processor L2 in office no. 1; that the number of load control
processors utilized in a particular area is dictated by the
number of controllable loads therein; and that a single load
control processor may control loads in several adjacent,
but physically distinct, locations (as shown by processor
Ls controlling loads both in room 1 and the central corridor).
A physically distinct unit, such as an office or room (or
portions thereof) within a building may be recognized as con-
stituting a sector, for which energy control would typically en-
compass all fixtures therewithin. Thus, a first sector Sl may
encompass the fourteen fixtures within office no.l, including the
eight fixtures Fl-F8 controlled by load processor Ll and the six
fixtures Fl-F6 controlled through load processor L2.
Similarly, a second sector S2 may be defined within office
no. 2 and comprises the loads controllable via load control
processors L6 and L7. A third sector S3 corresponds to the
loads controllable via load processor L8 and physically located
within office no. 3. The designation of a particular sector may,
as hereinabove explained, encompass all or part of one or more
load control processors and the loads associated therewith,
within a single room or other physically constrained portion
of the building; similarly, a sector may be defined as a
portion of a room, such as sectors S4 and S5, respectively,
consisting of the fixtures associated with load processors
L4 and L3, respectively in room no. 2. The user may equally as
well define a sector ! such as sector S6, to comprise the fixtures
associated with a load control processor such as L5, where the
controllable loads ~e current within two (or more) physical distinct areas,
such as room no. 1 and the corridor in the example of Figure 2.
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The list of energization states of each fi~ure associated
with each load control processor at a particular time
is herein referred to as a map. In our preferred
embodiment, up to eight maps may be transferred to RAM memory 12c
from data storage means 14 (Figure 1) after system powerup, and
the maps thence remain in RAM means 12c to facilitate reimple~
mentation of a particular map by establishing a correspondence
between the time in the real-time clock 20 and the
implementation time program used for actuation of the particular
map. For purposes of illustration, three hypothetical maps'
follow below and are predicated upon a lighting control
system operating in the "ixture" mode, i.e., utilizing a first
relay for establishing the "on" and "off" state of a particular
fixture and a second relay for establishing the "low" or "high"
state of that fixture, ~or each fixture associated with a
particular load control processor. It should be understood
that the control mode is definable in this preferred embodiment
such that the user can specify "fixture" e.g. high/low (2 relays)
control or individual "relay" e.g. on/off (1 relay) control.
~ z ~ RD-9838
MAP A
ENABLE:TOD--0800,DOW-M, T, W, Th, F
SECTOR LCPLOAD STATES(Hl=2,LO=l,OFF=O)
8 7 6 5 4 3 2 1
Sl Ll1 1 1 1 1 1 1 1ENERGY UNITS
Sl L2X X 2 2 2 2 2 2 38x2
S2 L6 1 1 0 1 2 2 1 2xO
98
S2 L71 2 2 1 1 2 2 1
S3 L82 2 1 2 2 2 2 1
S4 L42 2 2 2 2 2 2 2
S5 L32 2 2 2 2 2 2 2
S6 L51 2 1 1 1 2 2 2
MAP B
ENABLE:TOD1730, DOW M~ T, W, Th, F
SECTOR LCPLOAD STA~TES
Sl Ll " O O 1
Sl L2X X 2 2 1 2 2 1ENERGY UNITS
S2 L6 6x2
16xl ~ :.
S2 L70 0 0 0 0 0 o o 40xO ~'
S3 L8
S4 L4 1
S5 L30 0 0 0 0 0 0 0
S6 L5 1 0 0 1 0 0
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MAP C
ENABLE: TOD-130, DOW-~ T, W, Th, F
SECTOR LCPLOAD STATES
Sl ` LlO O O O O O O O
S S1 L2X X 1 0 0 0 0 0 ENERGY UNITS
S2 L6 4xl
S2 L70 0 0 0 0 0 0 0 58x0
s3 ~8
S4 L4 1
S5 L30 0 0 0 0 0 0 0
S6 L5 1 0 0 1 0 0
As will be seen by reference to the three sample maps, a
total of 98 units of energy are expended during the normal
working hours when map A is implemented> with only 28
energy units being expended (~AP B) for a short period of
time after the normal working day ends, to accommodate those
employees still within the area shown in Figure 2; and only
four energy units are required for providing some minimal
lighting level at other times when employees would normally
not be expected to be in this area. An employee, by accessing
the central facility via tone-coded digits from a local phone,
which are converted to 2-out-of-8 encoded data by the telephone
interface 37, can enter a particular sector number.
The telephone data on I/O bus portion 16b is given a priority
interrupt status, when received at CPU 12a and is immediately
implemented as temporary loading pattern changes to the map
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then in effect. The changes received by telephone are not,
however, permanently stored and do not permanently change the
maps stored in mass storage memory 14.
Thus,`the "SECTOR" mode is entered by a guilding occupant --
overriding a portion of the previous established lighting
load pattern by establishing a telephone connection
with the central facility and transmitting a predetermined
sector code thereto by means of tone combinations decoded
by the telephone data set in the telephone interface.
In the "SECTOR" mode, the lighting pattern for each predefined
sector may be preset; further, the system advantageously
allows an overlapping of sectors, i.e. the defining of more
than one sector to include a particular lighting fixture.
In our preferred embodiment, any single light fixture may be
included in the definition of up to four different controllable
sectors. For example, one user-definable-and-controllable
sector S10 may comprise the six fixtures Fl-F6 of the second
load control processor L2 in office number 1, plus the third
fixture F3 controlled by the fifth load control processor L5 ~;
in the corridor. (It should be noted that the digital -
information defining sector S10 will now consist of the
digital word addressing LCP L2, for controlling the six
fixtures attached thereto, and a second digital word addressing
LCP L5 to control the third fixture coupled thereto).
Further, the fixture F3 coupled t oLCP L5 may also be included ;
in the sector definition of three additional sectors, e.g.
sectors Sll~ S12 and S13, which respectively also include
predefined energization information for, e.g. fixtures F5-F8
of LCP L3, for sector Sll; fixtures F6-Fg of LCP L8,
for sector S12; and fixtures Fl and F5 for each of LCPs L6 ~:
and L7 in sector S13, by way of example. It is seen, therefore,
: ` ~ '' ' ' ' :; . ' "' .: '
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that the present novel energy control system and methods
therefor, particularly as applied to lighting loads, provides
an extremely high degree of versatility, due in part to the
use of the telephone interface to establish ~he energy
utilization condition of each load or fixture in each sector.
Referring now to Figure 3, a map of the memory space address-
able by the 8080-type microprocessor, as used in the preferred
INTEL MDS-800 microcomputer, shows that for a sixteen bit
wide address bus, a total of 65,536 data words~(each one
byte wide)can be addressed, from a starting address of 0000H
t~ a final address of FFFFH, where the subscript H indicates
the hexadecimal numbering system, between digits 0 and F.
This total memory space must store a boostrap routine, to
enable program loading, which bootstrap is commonly stored
in ROM memory (as the routine does not change with a change
in either program or data) and begins at the initial
memory address 0000H, and extends over a certain ~umber of
bytes, e.g. 256 bytes to final address 00FFH. The remainder
of the memory space is utilized for storage of the operating
program, which may be partially stored in RAM (as in the
memory space immediately above address 00~FH)~ in ROM,
for that portion of the program in which changes are
never to be made (as that portion of the memory starting at
address 8000H); or a combination of the two, as illustrated.
A portion of the memory space will also be occupied by at least
some part of the data base, always stored in RAM, e.g. that
portion of the memory ending at memory address 3FFFH, ;,
Referring now to Figures 4 and 5, the system advantageousIy
is programmed to allow the user to define each sector in the
controlled building or facility, and contains English language
messages prompting and guiding, in an interactive manner, the
user to supply the required information at the proper time.
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The system operates in one of three modes: the system
definition mode; the system executive (management) mode; and the
power-up/reset mode. In the system definition mode, the user
personnel hold an English-like conversation with the central
S computer facility, which facility guides the operator throu~h
each step of def~ning the various sectors, maps and timing by
; indicating the required inputs to be entered by the operator in
each of the definition procedures. The system (command) execu-
tive routine allows automatic operation of the system in the
event that user personnel are not in communication with the
system; the system reverts to the command executive in normal
operation.
In the sector definition routine of the system definition
mode, user personnel define those fixtures associated with each
sector, by sector number, LCP number and either the fixture num-
bers or the individual relay number (depending on the definition ~ ;
mode) to be assigned thereto. Thus it is seen in Figure 4 that
selection of the routine for sector number definition causes the
central facility to print a title message upon the operations
console 35, and to prompt the operat~r to enter the second
sector number. Upon input, by user personnel, of a decimal-
based sector number, this number is converted to a binary number
and temporarily stored in a two-byte software buffer after being
checked for errors. The system ,hen asks user personnel for the
number of a load control processor which will be in the sector
previously defined, and for the fixture and relay numbers ;~
to be affected. Upon entry of the called-for information, the
system definition routine generates a four-byte encoded word for
loading into an area of memory known as the sector table (Fig-
ure 5). The exact location of a particular entry in the sector
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table is given by adding a base address, i.e., the starting
address of the secto~ table, to an index address determined by
the number of the LCP affected. The four-byte word includes
the two-byte sector number address, taken from a temporary buffer,
and includes a two-byte word defining the affected control points `
in accordance with the load control processor number, fixture
number and relay number information entered by the operator.
Upon loading of affected control point and associated sector
number information in memory, the system definition program
prompts the user personnel to enter further sector definitions
and cycles through the above procedure as such definitions are
presented, or, if no further definitions are presented, reverts
to the command executive program and continues to operate the -
system automatically in accordance with the data now stored in
system memory. In this manner, sector Sl may be defined
by a sixteen bit binary number having its low order byte
entered as the first byte of the four-byte word and its high
order byte entered as the second byte of the four-byte word
in accordance with the data formating procedure utilized with
the particular microprocessor, the 8080 ? used in this
embodiment. The binary representation or the associated
load control processor, e.g. Ll, and the particular fixture,
e.g. F6, as well as the state of each of the relays, e.g.
the "on/off" and "high/low" relays, associated with that
fixture of that LCP, is represented by a second sixteen-bit
word formed of a low order-affected control point byte, con-
taining "on/off" data for the 8 associated fixtures, and a high
order-affected control point byte, containing "hi/lo" inform-
ation about the same sequence of 8 fixtures with ~hese types
being sequentially stored after the sector number byte.
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In somewhat analogous manner, each of a plurality o
energization maps and map starting times are defi.ned.
Figure 6 illustrates the program flow for defining a map
pattern and commences with the operator calling for the ~ap
definition mode, whereupon the console prints a map definition
title message and requests the map number to be defined.
In this preferred embodiment, a total of 8=23 maps are
allowable. The operator enters a letter, A-G, to select/name
the desired map and the computer prompts the operator for
the particular map base desired, i.e. whether a prexisting
map base is to be displayed for modification or whether a
new map base is to be generated. Thus, when the operator
names a map pattern to be defined and also specifies
whether an existing map pattern is to be used as a base
for the new map pattern, a memory buffer is either initialized
with the old map specified as the base or is cleared to
facilitate creation of a new map. The operator now enters
the states of the fixtures associated with each load control
processor. As an example, in previously given map A,
a specific load control rocessor L6 in the second sector, S2,
is to hav~ its fixtures Fl through F8 energized in the following
pattern - low, high, high, low, off, low, low and off,
Representing each fixture by two similarly placed bits, with the ;
bit in the first (low) byte indicating the on-off state and the
same bit in the second (high) byte indicating the high-low state,
the control word for these eight fixtures is the ~wo-byte
pattern: (LOW BYTE) 01101111 (on/off)
(HIGH BYTE) 00000110 (hi/lo)
This word is loaded as the hexadecimal data, e.g., 066FH in
the memory map of Figure 7. The starting address SA' of this
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particular control point block is based upon the address of the
associated load control processor, e.g., L6, as an index and is
added to the base address of the control point loading pattern to
point to the actual block address SA' where the word is stored.
~ 5 When the load control processor word is completed, the control
; word is stored in the address location and the system definition
routine returns for further user-input definitions. Upon com-
pletion of user input, the system reverts to the command execu-
tive for automatic system operation, while the defined map data
base is transferred from the map software buffer into memory.
As the map pattern has stored addresses determined by index and
relative addressing concepts, the map definition table can be
loaded in any predetermined memory location and can be retrieved
by defining the starting address of the map.
The schedule definition procedure (Figure 8) is similar to
the sector and map definition procedures, in that the schedule `
procedure is selected by the operator and the system prompts for
schedule information. The system operator enters the designation
of the particular map whose schedule is to be defined' and then
enters the time of day and day of wee~ information defining
when that particular map is to be implemented. The system
definition program then builds a three-byte word relating the
map number, the date of the week and the time of the day
and stores this word, represented as in Figure 9, in a
pattern schedule table in memory, wherein the time schedules
are arranged in chronological order. The chronological
schedules are established beginning at some storage address
SA'', whereby the addresses may be permanently programmed
into ROM means if the map time schedule will be invariant.
It should be understood that time scheduling information
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may be programmed into RAM (for subsequent storage in the mass
data storage means 14 until requested under program control) or
may be implemented in semipermanent storage means, such as
EPROMs or EAROMs, configured to have the appropriate starting
address SA " . The use of EPROMs and the like allows the system
operator to merely replace a single integrat~d circuit to com-
pletely modify the time scheduling of the system, which provides
a useful manner in which the system may be reconfigured during
vacation schedules and the like, without the time-consuming task
of manually entering a new map schedule portion of the data base.
Referring now to Figures lOA-lOF, a flow chart the
command e~ecutive routine is shown. As will be seen, the system
executive is a continuously cycling program which starts out with
subroutine 1 thereof initially checking the activity of the
device used for operations console and interface 11. If such
device is active, signifying that user personnel are attempting
to communicate with the central computer facility, the system
executive routine proceeds to interact with the console and pro-
cess the information or requests therefrom. I~hen console
servicing is complete, the command executive opens the I/O ~
port, via I/O line portion 15b, to the telephone, or map `
override, interface 37. If a request to override a portion
of the map then in effect is present on telephone line 39,
the system executive receives the change information and
decides whether a telephone requested map override presently ;
in effect is to be eliminated or whether a new map override
is to be inserted into the map program. In either case,
a new set of override flags are generated and data is
established to indicate which receiver/decoder (REC/DEC),
or set thereof, is to be addressed and which loads controllable
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~ RD-9838
thereby are to be affected. Once this data is inserted into
memory, or if no change in a map override is requested,
the system executive checks the entire map then in e~fect for
recognition of all overrides thereto. If one or more map
overrides are in effect, the system command executive enters
~ subroutine 4 thereof,to be discussed hereinbelow; if a map
override is not in effect, the system command executive checks
the validity of the real-time clock data; if the data is not
valid the routine exits to subroutine 2, discussed hereinbelow.
If the real-time clock data is valid, the routine determines
which map is then scheduled to be effective at the time read
from the real-time clock 20 and checks that map against
the current map in effect (CURMP). If the CURMP is correct
for the time information received from real-time clock 20,
no change is required and the routine continues; if a map
change i9 required the routine begins installing the new map
and sets a map processing flag (MAPFL) to prevent receipt of
' outside-originated map change requests and implementation
: thereof. If the MAPFL flag is set, ~.he routine goes to
subroutine 4 to format data for transmission to the various
receiver decoders of the multiplicity of remote LCPs, to
effectuate the map change. If a map change is not in progress
the routine exits to subroutine 2.
Subroutine 4, for transmitting data to the paralleled
receiver/decoders of all of the multiplicity of load control
processors, co~nences by checking a receiver/decoder transmitter
counter for a zero state. If the transmitter counter is in the
zero state, ind:icating that no further receiver decoders
are to have data transmitted thereto, the subroutine resets
the MAPFL flag and causes the media interface 40 to place the
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powersaver signal on data line 45 to place all of the load
control processors in the powersaver mode. I the transmitter
counter is at a count other than zero, a receiver/decoder
pointer is set and a software data output buffer is loaded
with the particular output data to be sent to a given receiver/
decoder, The receiver/decoder address pointer is checked for
overflow and the proper address is entered into the software
buffer. The complete data word, having a format explained
hereinbelow with respect to Figure 13b, is transmitted from
the software buffer, via I/0 bus portion 15c to the media
interface 40 for transmission to the load control processors.
After transmission of all receiver/decoder data words,
the routine enters subroutine 2 (Figures lOD, lOE and lOF).
Subroutine 2 is entered if all map changes and all -
operations console interaction is terminated. The subroutine
commences by checking whether a telephone service request
(TLR~S) is present. If such service is requested, the type
of service, either normal sector control or control of an
individual relay, is in effect. If normal sector control, as
determined by a telephone input code, is in effect, the routine
exits to subroutine 3, hereinbelow discussed. If individual
relay control is requested by the person on the telephone line,
the individual relay control data transmitted by that user
presently on the telephone line is sent to the receiver/decoder
of the particular load control processor affected; the tele-
phone line is then checked for further user input and if such
input is present, the routine exits to subroutine 3; if no
further input is forthcoming, a telephone timer is reset and the
telephone interrupt program is reenabled prior to re~urning to
the beginning of subroutine 1 of the system command e~ecutive.
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In the event that TLRQS was not reques-ted at the beginning
of subroutine 2, the subroutine checks whether the telephone is
presently ringing with a remote user request and if so, readies
the telephone data set comprising telephone interface 37 and
requires data therefrom. If no phone ringing is present, sub-
routine 2 continues to check the activity of the telephone line,
the enablement of connection 38 between telephone line 39 and
the interface 37 and further checks for time-out of the specific
time interval allotted for any user on the telephone to complete
his call. If the system has timed-out, if normal sector control
was requested; or if the user is still on the telephone with
further input past the time limit, the command executive program
enters subroutine 3 whereby the telephone connection is broken
and all telephone I/0 and processing flags and interrupts are
returned to their initial conditions, prior to reentering the
system command executive at subroutine 1.
Referring now to Figures lla through llh, a flow chart for
the telephone interrupt service routine is shown, which routine
is entered by initiation of a priority interrupt when the user
dials the dedicated phone number allowing access to telephone
interface 37. After the telephone has been answered by the
central facility, a telephone priority interrupt is enabled.
Thus, the central facility can continue to perform normal
executive activity and be interrupted only when a telephone input
is entered. Each time a telephone interrupt appears, the routine
passes through the telephone director of Figure lla. This dis-
patches the input to the appropriate subroutine (0-4), depending
on the position of the sequence o~ data received. The director
(TLDIR) is initially set to 0 for the first input.
Figure llb corresponds to TLDIR equal to 0. In this section,
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.
the type of service is determined; TLSRV is either se~ to
normal sector service or individual relay service determined if
the first input is a numeric or a "#", respectively. Before
returning to normal processing TLI)IR is set to one for the
next input.
Figure llc corresponds to TLI)IR equal to l. This program
sequence inputs telephone data and stores the data in order of
entry by the remote user into a buffer in RAM memory. 1~1hen a
delimiter (# or *) is found, a check as to the type of service
is determined before processing of the data in the buffer is
undertaken. If type of service is individual relay, then the
telephone input buffer is packed into a two-byte binary number,
as shown in Figure llb, to be stored as the LCP number~ The
LTDIR is then set to 2 for the reception of the affected relay
number. If type of service is normal sector control, process- :
ing continues as shown in Figure lli.
In Figure lli, it is first checked if the last telephone
input was a "*" or a "~" to determine if sector level control
or vacation overrride control, respectively, is requested. If
vacation override control is requested, the sector level data
: word is forced to zero. The service request flag is then set
(TLRQS) so that when control passes back to the main executive
loop, telephone service will be undertaken in the normal activity
flow, as shown in Figure lOd. If a normal sector change is
requested, then control passes to C of Figure lld. However, the
packed binary number is taken as the sector number and TLDIR is
set to 2 to setup for the input of the level information.
Figure lle corresponds to TLDIR=2. This program segment
takes in either sector level information when in normal sector
control or the relay number when in individual relay control.
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A check is made on the incoming data for errors. As shown in
Figure llf, if the data is interpreted as a sector level, then
the telephone service request flag is set, the phone connection
is broken and processing returns to the main executive for
telephone serviceing.
Figure llg corresponds to TLD]:R=3. This program segment
interprets the telephone data as being an individual relay level
input. A check ~or errors is made on the input character. If
the input is valid the telephone service request is set and the
TLDIR is set to 4 for any additiona} relay change for the given
LCP.
Figure llh corresponds to TLDIR=4 and determines if ad-
ditional individual relay control inputs are requested. If so,
TLDIR is set to 2; if not, the line is terminated.
In the event that power is removed, either intentionally
or inadvertently, from the system, upon restoration of power
thereto, the system automatically resets, clears all
RAM memory locations and loads the system definitions from
the memory storage media in mass data storage means 14,
all without user intervention. The real-time clock, being
backed up by a large-capacity battery means 29, will provide
proper time in~ormation to the power-up/reset bootstrap
routine of Figure 12, to allow the system to install the
proper map called for at that time and to do so in automatic
fashion. The bootstrap routine, which is loaded into ROM
memory 12b, is located starting at memory address
0000H (see Figurle 3), which address is the initial address called
upon restart by the particular CPU (the ~0~0) utilized in our
preferred embodiment, whereby the bootstrap routine can
initialize the CPU and reset all LCPs, as well as the operation
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RD-9838
of the console 35 and telephone interface 37. The bootstrap
checks the mass data storage means 14, and if the magnetic
tape contains the proper system software and map/sector/schedule
information, the bootstrap loads this data, checking for
errors, and if the data is successfully loaded, proceeds to
the command executive routine (see Figure 10) ~or execution
thereof.
Referring now to Figure 13a, media interface means 40
couples to the preferred twisted-pair media 45 both a data
signal, having a binary one level of about +V volts and
a binary zero level of about 0, or ground potential, volts
as well as a power saver (PSVR) signal which is a negative
voltage of about -V volts for the purpose of turning off
a major part o~ each load control processor 50,
F.aCh of the data and power saver signals is received by
an identical input section lOla or lOlb, utilizing optical
coupling techniques between a current-limited photodiode 102a
or 102b and an associated phototransistor 103a and 103b.
The emitters of both phototransistors 103 are coupled to :
the negative potential 'DUS 104, while the collector of the
first phototransistor 103a is coupled via a load resistor 105a ;
to the positive voltage bus 106, and the collector of the second
phototransistor 103b is coupled via another load resistor 105b
to the ground bus 107. The collector of each phototransistor is
coupled through a DC amplif-ier transistor lO~a and lO~b, respectively,
with its associated load resistance lO9a and lO9b, respectively,
to provide isolated and amplified data and powersaver signals
ed and ep, respectively, to the media data driving circuitry
110 and powersaver: driving circuitry 111.
In the absence of a PSVR input, driving voltage ed is coupled
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to the input of the Darlingto-n amplifier 114 coupled between the
positive bus 106 and output resistor 115. The driving signal
is also coupled via emitter follower 117, comprised of transistor
117a, base resistor 117b, 7,ener diode 117c and emitter resistor 117d
to an output stage 118, comprisecl of a transistor 118a,
its base resistor 118b and a coll.ector diode 118c, with the
colLector diode-transistor col].ector-emitter circuit coupled
across output load 115. A binary one (positive true)
signal at input llna causes Darlington amplifier 114 to
saturate, while causing transistors 117a and 118a to
enter the cut-off state, whereby the interface means output
40c is forced to a voltage approximating the +V potential,
in logic one condition. When a data zero signal appears at
data input 40a, a logic zero signal appears at amplifier input
llOa, driving Darlington 114 to the cut-off state and
allowing the voltage at output ~Oc to fall to approximately
ground potential. The ~Qregoing is true if the powersaver input
40b does not have a powersaver signal present, whereby the input
voltage ep at both the powersaver amplifier input llla and
the data amplifier auxiliary input llOb is a binary zero
level,of approximately -V volts, cutting off the powersaver
amplifier Darlington transistors lllb and lllc to prevent
any interaction thereby with the data levels across output
load 115. The large negative voltage at auxiliary data
amplifier input llOb biases the associated transistor 119,
via ~ts base resistor ll9a, into the cut-off condition, whereby
transistor 119 does not affect the voltage at data amplifier
input llOa.
When a powersaver signal is present at powersaver input
40b, the signal ep has a binary one voltage of approximately
: --.~1--
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~ RD-9838
ground potential. This ground potential at powersaver amplifier
input llla causes saturation of the Darlington transistors lilb
and lllc and pulls the interface means output 40c to the negative
voltage -V. Simultaneously, transi.stor 119 is saturated, placing
a negative voltage signal at data amplifier input llOa to place
both the Darlington output circuit 114 and the pull-down tran-
sistor 118a in their respective cut:-off conditions, removing
all influence thereof on the voltage state of the output. Col-
lector diode 118c is now utilized to prevent damage at the col-
lector electrode of the reverse-biased transistor 118a. Thus,
it is seen that the PSVR signal takes precedence over all data
signals and prevents transmission of the latter over the system
media 45.
Referring now to Figure 13b, when data is present, data
is transmitted to the receivers/decoders, of the individual
load control processors over the dedicated two-wire
transmission link at a high data transfer rate of about
2400 bits per second, with a high noise immunity being achieved
by utilizing a complementary-redundant error-detecting code;
a la~ge voltage swing between the two logic levels transmitted;
and threshold-crossing data recovery techniques at the receiving
end. The data transmission format thus transmits the two-byte
address code commencing with the low-order byte (as required
by the particular data format of the 8080 microprocessor
utilized in the illustrated embodiment) which low-order -
byte is first transmitted as ~ bits of complementary data
in time interval Tl and is followed by the eight bits of the
low order address byte transmitted as true (or non-complemented)
data in time interval T2. The high order eight-bit address byte
follows with the complement of the eight data bits being
first transmittecl in time interval T3 and followed by the
eight bits of the high order byte transmitted in data-true
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RD-9838
manner in the fourth time interval T4. Thus, if the sixteen-bit
address of a particular receiver/decoder to be addressed
is 47AFH, or 0100011110101111 in binary, the transmitted
address will be 01010000 in time lnterval Tl (the complement
of the low order byte), follo~ed by the eight bit true low-
order byte 10101111, in time interval T2, followed by
the high-order byte complement eight-bit pattern 10111000,
in time interval T3 and ending the address portion of the
transmission with the high order byte data-true eight-bit
pattern 01000111. The following t~70 bytes of data are also
transmitted with the low-byte in complementary form during
time interval Ts followed by the low-order byte in true-data
form during time interval T6, and then the high-order byte
in complementary data form during interval T7 with the true-data
represent.ation of the high order bit following time interval T8.
A framing error is transmi~ted during a tirne
interval T9 to act as a reset at the end of the address-data
transmission.
Referring now to Figures 13c and 13d, the data input from
transmission media 45 is received at load control processor
input 50a, and is coupled to receiver logic circuitry 200, prefer-
ably comprised of some signal conditioning means 201, including
low pass filtering means for removing high frequency interference
from the incoming signal and means, such as a Schmitt trigger
and the like, for restoring sharp leading and trailing bit edges.
The conditioned signal is coupled to a universal asynchronous
receiver-transm:itter (UART) 202 at the data input 202a thereof.
A load control processor clock 203 is coupled to the clock in~ut
of the UART; the clock serves to establish the bit rate accept
able for reception by the UART. Signal transmission through
.
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media 45 and into UART 202 is in serial fashion. The UART,
having been previously reset by the application of a reset signal
at reset input 202b, coupled via master clear 207
to the potential energizing the entire receiver/decoder, receives
the eight serial bi~s and simultaneously presents these eight
bits, through a set of inverters 204, on an eight-bit-wide
parallel data bus 205, when a data ready (DR) output 202b
is enabled for a short time interval.
The data bus is coupled to a sixteen-bit wide data latch
210 comprised of a pair of eight-bit data latches 210a and 210b
having their data inputs coupled in parallel to bus 205. The
less significant byte of each of the address and data words are
stored in the less significant byte (LSB) latch 210a while a
more significant byte is stored in the remaining (MSB) latch
210b, when the respective data latch is properly controlled to
the storage condition by control circuitry outputs to be described
hereinbelow. The eight-bit wide data bus is also coupled to ~;
error checking logic exclusive-OR gates 212 in manner such that
,he data line assigned to the most significant bit is coupled to
first exclusive-OR gate 212a and the remainder of the lines are
coupled in sequential order to sequential exclusive-OR gates 212
until the data line assigned to the least significant bit is
coupled to one input of the last exclusive-OR gate 212k. The
remaining input of each exclusive-OR gate 212 is coupled to one
associated bit on paralleled MSBO output bus 211b from the more
significant byte latch 210b. The output of each of the exclusi~e
-OR gates 212 is coupled to one input of a k-input NAND g2te 213
to generate a wrong data (WD~ signal, as required and herein- ~:
: below explained.
Similarly, a plurality of exclusive-OR gates 214a-214K have
one input terminal thereof coupled to one different output
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~ J ~'3 RD-9838
line from the LSBO and MSBO busses, with a remaining gate
input coupled to one switch Sx of a receiver/decoder address
determination switch assembly SO The switch is coupled between
the remaining gate input and ground, with a pull-up resistor Rx
being coupled between that gate input and a positive voltage.
The output of all exclusive-OR gates 214 is coupled to an assoc-
iated input of a k-input NAMD gate 215 to generate a wrong
address (~A) signal as described hereinbelow,
Each of latches 210a and 210b have a reset input
220a and 220b, respectively coupled to the reset output of the
-~aster clear circuitry 207; via a jurnper 20~; a ~irst latc~~enaDle
input 221a and 221b, respectively, is coupled to the
data ready output 202c of the UART; and a second data-load
input 223a and 223b, respectively, is each driven by the output
of a three-input AND gate 225a and 225b, respectively.
Control circuitry 229 includes four flip-flops 230-233 used
as a state-sequence counter; the clock input C of first flip-
flop 230 is coupled to the data ready output 202c of the UART,
with the clock input of each following flip-flop being coupled
to the Q output of the preceding flip-flop. The J and K inputs
of the first three flip-flops 230-232 are coupled to a positive
potential (not shown for purposes of simplicity) while the
K input of the last flip-flop 233 is coupled to ground
potential and J input of flip-flop 233 is coupled to
reset bus 235, which bus is also coupled to the reset inputs
R of the preceding three flip-flops 230-232. The Q output
of first flip-flop 230 is coupled to one input of each of
a pair of NAND gates 240 and 241, while the Q output of
flip-flop 230 is coupled to one input of AND gate 225a; the Q
output of flip-flop 231 is coupled both to one input of AND
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gate 225b and to one input of NAND gate 240; The Q output of
flip-flop 231 is coupled to one input of ~ND gate 225a; the Q
output of flip-flop 232 is coupled to another input of NAND
gate 240, while the Q output of last flip-flop 233 is coupled to
to an input of both AND gates 225a and 225b. The remaining input
of AND gate 225 is coupled to a positive potential (logic one
level).
NAND gates 240 and 241 form a portion of system reset logic
circuits 242, in conjunction with AND gate 244, having an
input thereof coupled to the output of each of NAND gates 240
and 241, and another J-K flip-flop 246, receiving its clock
input from the output of gate 244 and having its J-input coupled
to a positive potential and its ~-input coupled to ground
potential. The Q output.of flip-flop 246 is coupled back to its
reset R input via an inverter 247 and a time delay capacitor 248;
the Q output is also coupled to one input of a three-input NOR
gate 248, receiving the Q output of flip-flop 233 at another
input and a framing error (FE) output of UART 202 at its remain-
ing input. The output of NOR gate 248 generates the reset sig-
nal on line 235.
The reset R input of flip-flop 233 is formed by a one shot
multivibrator (OSM) 250 acting on the output of load distribution
clock means 260. The load distribution clock receives the 60 Hz.
power line frequency and includes a divide-by-10 frequency
divider 261 coupling its 6 Hz. output frequency to the input 263a
of a four-bit binary counter 263. Counter 263 has its reset
input 263b coupled to the Q output of flip-flop 233, along with
.
the reset input 265a of a one-of-sixteen deco~er 265. Each of
the four outputs 263c of the binary counter a ~ coupled to th~
corresponding one of four inputs 265b of the decoder. The sixteen
~,
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~ RD-9838
individual decoder outputs Ro~ R15 are coupled via a sixteen-
wide relay bus 267 to a set of sixteen relay driver circuits
270; the last decoder output R15, i.e. the sixteenth bit,
is coupled to OSM 250 to form the reset signal for flip-flop
233.
As previously explained hereinabove, each LCP
is ~apable of operating sixteen relays, with two relays typically
being required for a lighting fixture having both an"on-off"
function and a "high-low" intensity function. Each of the
relays is a latching type, being pulsed with current flow
in a first direction to latch in a first condition and
being pulsed with a current flow in another direction to latch
in the remaining condition. The drivers for relay RN,where
1~ N _16,comprises a pair of high-current buffers
271a and 271b, each having its output coupled to ,
the particular relay N respectively for enabling the "on"
and the "off" condition; and having a strobe input 273
coupled in parallel to the Q output of flip-flop 233.
Each relay driver input is coupled to the output of an
associated AND gate 274a and 274b, respectively, each having
one input thereof coupled to a different single one of
the sixteèn relay output lines from decoder 265. The remaining
input of the AND gate 274a associated with the " on" state,
and the input of the remaining AND gate, coupled through
an inverter 275, is coupled to the bit output of that one
bit of the data latch 210 assigned to that particular
relay. It should be understood that we prefer to tra~smit the
first byte of data (fixture "on-off") information is inverted
logic fashion and the last byte of data (fixture "hi-lo")
information in non-inverted fashion, and place the relay drivex
inverters 275 for only the first 8 relays in the input circuit
of gates 274a (w:ith the inverters in the last 8 relay drivers
being coupled as shown) for facilitating implementation of a
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$
"power-up-reset" mode hereinbelow described. It should be understood that
while a single relay driver circuit 270, for a single relay, is shown in
Figure 13b, an additional fifteen such circuits are utilized for the re-
maining fifteen relays actuatable by the single load control processor of
the present embodiment.
In operation, assuming a powersaver single is not present on the
data input line, the data sequence shown in Figure 13b is received and
conditioned by means 201 and is loaded into VART 202 in serial fashion.
All of flip-flops 230-233 and 246 have previously been reset whereby
the respective Q outputs are at a binary zero level. The first eight-
bit-serial signal is loaded into UART 202 responsive -to, and enabled by,
timing pulses from the load control processor clock 204. The single
byte signal is assembled and presented as an eight-bit parallel signal at
the output of the UART; inverters 204 act to convert the complement data,
initially received, to -true-data placed on data bus 205 when the data
ready (DR) output 202c is enabled. The DR signal enables both latch
first inputs 221a and 221b, while the enabled Q outputs of flip-flops 230,
231, and 233 are combined in AND gate 225a to enable the LSB latch 210a
second input 223a, to clock the eight bits of parallel data into the
LSB latch and present the data at the latch output LSB0. The MSB latch
second input 223 is also enabled as the second AND gate does not receive
the Q output of flip-flop 231 at its input, but does receive a continuous
logic enable ~positive voltage) signal instead. The first DR signal
appears at the clock input of flip-flop 230 and toggles the first flip-
flop such that, after the first byte of info~mation is loaded into the
LSB latch 210a, flip-flop 230 has energized its Q output and de-
energized its Q output.
The second (address low order true) byte of data is transmitted to
the receiver decoder and loaded into UART 202 and -then inverted by
inverters 204 for presentation in parallel on da-ta bus 205, simultaneous
with enablement of DR output 202c.
38 -
,' ' : ; : .:
RD-9~38
As the Q signal from flip-flop 230 is disabled, second LSB
latch input 223a is disabled and the true data is not stored i-a
latch 210a. The now-complemented data on data bus 205 is routed
to exclusive-OR gates 212, whereby comparison is made with the -
now-true output of the LSBO bus 211a. If the complementary data
on data bus 205 is the bit-for-bit complement of the true data
now on LSBO bus 211a, the output of each exclusive-OR
gate 212a-212k is enabled and the output of NAND gate 213 is
disabled, indicating that proper first address byte data has
been received. Conversely, if even one bit of either the
complementary-data or the true-data word is improper, the
I~D output of gate 213 is enabled and is coupled to NAND
gate 241, which gate has its remaining two inputs enabled
by the presence of DR signal from the UART and the enablement
of the Q output of flip-flop 230. In such case, the BD
output of gate 241 is disabled and provides a falling clock pulse
to flip-flop 244c which generates a reset pulse to NOR
gate 248 coupled to the control logic reset line 235 to
reset all flip flops and prevent the receiver/decoder from
taking any action pursuant to the address-low-order-byte
code having transmission errors associated therewith.
Assuming that the low order byte complementary-data and
true-data transmissions have been error free, the output
211a of the LSB latch contain the address low-order-byte
true -data code. The address high-order-byte is now transmitted
with an eight-bit complementary code, which appears inverted and
in parallel on data bus 205, simultaneous with the third enable-
ment of the DR output 202c. The previous DR output had re-tog-
gled flip-flop 230 such that the ~ output was enabled, and ha
also goggled second flip-flop 231 such that its Q output was
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RD-9838
enabled (indicating that the more significant byte is to be
operated on). The inputs of gate 225b being all enabled, the
second gating input 223b of MSB latch 210b is enabled, such that
the now-true data on bus 205 is loaded into MSB latch 210b at the
third DR enablement~ The address more-significant-byte true
data is now present on MSB latch output bus 211 and one bit
thereof is coupled to each of exclusive-OR gates 212. The third
DR enablement also toggles flip-flop 230 such that the Q output
thereof is again enabled. As at least one input of AND gate 225a
is disabled, the data in LSB latch 220a is unaffected.
The high-order-address data-true byte is received at the
UART and presented in inverted manner and in parallel on data
bus 205. As both of gates 225a and 225b are disabled by the
disablement of the Q output of flip-flop 230, 'his complementary-
data byte is not leaded into either latch 210, but is coupled
in bit-by-bit fashion to the remaining inputs of ch~cking gates
212a-212k, where the bit-by-bit complementary nature of the
true-data and complementary-data bytes are checked and a reset
signal issued if the data bits are not full complements of each
other, as previously explained hereinabove. If all data bits are
correctly received, and no reset signal is present, the
outputs 211a and 211b of the respective LSB latch and MSB latch,
respectively, are routed bit-by-bit fashion to associated
inputs of address-checking exclusive-OR gates 214a-214k.
The remaining inputs of exclusive-OR gates 214 are either
enabled or disabled by means of the pull-up resistors and
grounding switches, previously set to encode the complement of
unique address assigned to the particular load control processor
receiver/decoder. The data on both latch output busses 211a
and 211b are, as previously mentioned, in true-data form, which
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is exclusive-OR'd to the complementary-data address configuration
of the switches and pull-up resistors and causes t~e outputs
of each gate 214 to be enabled only if the corresponding bit
of switch matrix complementary data is indeed the complement
of the true-data established at the latch outputs. Therefore,
gate 214 outputs are enabled and the output of NAND gate 215 is
disabled, indicating a proper address.- If one or more
of gates 214a are disabled (indicating that at least one bit
of the address data received is not the same as the corresponding
bit of the preselected address) the output of gate 215
is enabled to signify that a wrong address (WA) has been
received. The WA signal is received at NAND gate 240,
having the remainder of its inputs enabled respectively by the
..
Q ou~put of f'lip-flop 230, the Q output of flip-flop 231
and the Q output of flip-flop 232. Thus, the output of gate
240 is disabled, indicating a bad address (~0 condition,
which causes the output of gate 244 to fall and toggles the
reset flip-flop 246 to place a reset on control reset line
235 and effectively terminate action by the receiver/decoder.
The correct address having been received, and th;'rd ;
flip-flop having had its Q output enabled by the fourth
DP~ signal at UART output 202c, the receiver/decoder
is now ready to receive the high and low order data bytes '~
in successive complementary~true fashion. The low order
complementary data byte is received, inverted and clocked into
both LSB and MSB latches 210a and 210b in the same manner as the
low order inverted-complementary address byte was stored in
latch 210. Thence, the low order data-true byte is received,
inverted and compared with the true data now available on the MS B
latch output bus 211b, by the exclusive-OR gates 212 and gate 213.
;
.
.
i,i ' ' !, : !` . .:
R~-9838
If the low-order data byte is properly received, the high order
data byte com?lementary-data bits are next received, inverted
and stored only in ~ISB latch 210b, and the high order data true-
data bits are inverted and made available on bus 205, in the
same manner that the low order address bytes were received,
as hereinabove explained. The high order data byte complementary
and true data bits are also compared in gates 212 and if no
data transmission errors are detected, the operation of the
receiver/decoder continues. If a data error is detected, the
wrong data I~D output of gate 213 is enabled, to disable the
output of gate 241 and cause a reset to be generated on control
logic reset line 234, preventing continued processing of the
incorrect data received.
When a transmission is received containing the proper
address previously assigned to the particular receiver-decoder,
and containing two bytes of errorless data, the "data ready"
signal associated with the data-true high order data byte
transmission toggles all of flip-flops 230, 231 and 232 to
disable the Q outputs thereof; the clock input of the fourth
flip-flop 233 is thus toggled and brings the Q output thereof
(the relay ready state) to its activate~ ~ndition, to
enable relay strobe line 273, as well as to enable the
remaining input of NOR gate 248 to generate a reset signal
on line 235 and reset the control logic preparatory to receipt
of a next data transmission to the paralleled load control
Receipt of a framing error during data-address
transmission wil:L cause the FE output 202d to be enabled to reset
the control logic; the deliberate transmission of a
synchronizing framing errbr signal at tlne end
of the LCP adaress sequence, also causes FE output 202d
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~ RD-9838
to be enabled and reset the control logic preparatory to receipt
of a next transmission. This is used to synchronize all of the
LCPs with the central facility.
Latches 210 each now store a byte of data in true-data
format. The relay clock circuitry 260, having been reset by the ~
temporary disablement of the Q output of flip-flop 233, is now
again enabled as flip-flop 233 is toggled responsive to receipt
of the FE output generated by the reset portion of the data
transmission. The four-bit binary counter 263 again counts
through its count range and causes each one of the sixteen out-
put lines of decoder 265 to be sequentially enabled, whereby
each of the relay driver circuits 270 is sequentially enabled to
set each of the sixteen relays either to the "on" or the "off"
condition, dependent upon the st.~te of the particular bit
contained in the associated latch. As the relay data is present
at the latch output in true-data form, inverter 275 is utilized
in the "relay off" path between the latch output and the gating
and driver associated with the relay "off" driver.
The above described LCP, and particularly the receiver/
decoder section thereof, is configured to operate with a
dedicated, separate data transmission medium and with a
particular data encoding scheme. It should be understood that
other transmission data media and encoding methods may be
equally as well utilized; in particular, where the novel system
of the present invention is to be retrofit in an existing
building, devoid of the desirable twisted-wire-pair or coaxial
cab~e media for data transmission to the LCPs, the existing
power distribution wiring, for example, may be utilized. One
receiver/decoder for such usage although requiring a different
data transmission method is described and claimed in U.S. ~
Patent No. 4,091~''3'6'1 dated May 23, 1978 to Eichelberger et al.
. .
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.
~ ~ 2 ~ RD-9838
Referring now to Figures 13c and 14, the result of
transmitting a PsvR signal to the paralleled receiver-decoders
is considered. Each load control processor 50 includes ~ -
a power supply circuit 280 coupled to the AC power line and in-
cluding a power transformer 281 and transient suppression means
282 and noise suppression means 283 generally located
across the primary of transformer 281. Coupled to the
secondary of transformer 281 is a rectifier means 284 and
a filter means 285, yielding some DC voltage at the junction
therebetween for coupling to the relays and relay driver circuits
270. Additional filtering 285 and overvoltage protection means
287 are utilized to establish two additional DC voltages
VA and Vx, of positive polarity in the illustrated embodiment.
The powersaver circuit 290 includes a Darlington amplifier
291, comprised of first and second Darlington transistors 291a
and 291b, with a protection diode 291c having its cathode
coupled to the base of transistor 291a. A Zener diode
~92 has its anode coupled to data line input terminal 50a
and its cathode coupled to the anode of signal diode 291c.
A resistor 293 is coupled between the junction of diodes
291c and 292 and the +Vx power supply output. A series-
pass Darlington switch 295 includes Darlington pass transistors
295a and 295b coupled between the power supply +VA output
and a filter capacitor 296, in parallel with the input
terminal 29~a of a voltage regulator 297. The power supply
switch circuit 295 also includes a resistive biasing network
comprised of resistors 295c and 295d, coupled between
voltage VA and the output of the Darlington transistors 291.
The output of the voltage regulator, at terminal 298 supplies
the positive voltage necessary to operate the integrated
circuits utilized to implement the logic of the LCP.
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~ RD-9838
In operation, the data transmitted to LCP
data input terminal 50a is of the positive-true type, i.e.
a binary zero level generally corresponding to a voltage
level of about zero volts and a binary-one logic level
generally corresponding to some positive voltage level (typically
on the order of +15 volts. Du:ring normal
data transmission, it will be seen that the voltage at
terminal 50a is never less than zero, whereby the voltage
on the anode of signal diode 291c, and 'nence across the
base-emitter junctions of Darlington transistors 291a and
291b, is always positive. Hence, the Darlington transistor ~ :
base-emitter junctions are forward biased and the magnitude
of resistor 293 is adjusted to place the Darlington pair
in saturation, with the result that the end of resistor
295d furthest from transistor 295a, is substantially at
ground potential. The resistive divider comprised of
resistors 295c and 295d is chosen such that the Darlington
switch transistors 295a and 295b are in saturation whereby
substantially the full magnitude of voltage VA appears at
the input 297a of the voltage regulator. The magnitude
of volta$e VA is chosen to be larger than the required
logic voltage V~OGIC~ such that regulator 297 operates and the
proper logic voltage is available at output terminal 298 to
allow proper operation of the LCP.
The Zener voltage of diode 292 is chosen such that
when the negative magnitude PSVR signal is received, the
sum of that negative voltage plus the positive Zener voltage
is such that a negative voltage still appears at the anode
of signal diode 291c. The base-emitter junctions of both
Darlington transistors 291a and 291b are reverse-biased and the
transistors are then in t~e cut-off condition, placing each of
2 ~ RD-9838
the Darlington transistors 295a and 295b also in the
cut-off condition, whereby current does not flow to the
input 297a of the voltage regulator. The magnitude of
the logic voltage at regulator output 298 falls substantially
to zero, and not only prevents operation of the receiver/decoder
but also prevents any substantial power consumption by the
circuit.~y G~ the LCP. ~s prevlously explained hereinabove,
the negative DC voltage level utilized for the powersaver
function is removed to again provide a non-negative voltage
at data input 50a and allow the receiver/decoder logic
circuitry to be re-powered and readied for sub~equent receipt
of new data transmission.
Advantageously, the master clear circuitry 207 recognizcs
re-application of mains power after some finite time interval
of absence thereo, with the time interval being set by means
well known to the art, and, if jumper 208 is intact, applies
the reset signal to a switch means 300, which may comprise
another Darlington amplifier similar to Darlington 291. The
output of switch means 300 is coupled to the output of switch
291 through a protection diode 302. Thus, when mains power
is re-established, any PSVR signal at LCP input 50a is
effectively overriden by enablement of switch means 300
response to the master clear reset output, to cause saturation
of Darlington switch 295 and provide for the operation potential of the
~CP. The sa~.e reset output is cou~led, via jumper 20~, to the clear,
or reset, inputs 220a and 220b, of respective latches 210a and
210b. The latch outputs are all reset to a binary zero
state, while a preset input P of flip-flop 233 is enabled
to establish energization of the Q output thereof (corresponding
to relay cycling enablement). The load distribution clock
-46-
~- RD-9838
260 cycles the relay driver circuits 270. If the above-
described repositioning of inverters 275, in the first 8
relay drivers9is accomplished, the latch outputs thereto
are at a binary zero state and cause the fixtures to be in the
"on" condition (due to the logic inversion prior to the
relay-on driver 271~; the logic zero outputs of the remaining
latch then cause the "hi-lo" drivers to be in the "low"
lighting condition, whereby all fixtures are turned on after
a power-outage, bu~ are placed in a low lighting condition.
The fixtures remain in this condition until the central
facility has loaded the now-stored data from the mass data
storage means (transferred thereto from RA~I 12c responsive to
the power outage) back to RAM and the proper time comparisons
and map selection has been made. Once the map is selected,
the CPU causes that map energy utilization pattern to be
implemented and the overall low lighting condition is
replaced by the proper lighting pattern for that time-of-day
and day-of-week. Thus, even if mains power is temporarily
removed, the system continues to function in manner
such that some lighting is provided as soon as the power is
resetored
If the "power-up reset" option is not desired, the
jumper 208 is re.moved. Upon restoration of mains power, the -~
relays (being of the latching type) remain in the same
states as prior to the power outage and the prior energy
utilization pattern is restored, until subsequently modified
by the system's normal map-time-matching technique. Note that
if the option is not to be used, the data bytes may both be
transmitted in normal data-true fashion and the coupling of
inverters 275 and would then always be to the input of the
"relay-off" AND gate 274b.
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, ~
,-. i ~ "
...
~ RD-9838
Referring now to Figure 15, the real-time clock 20,
allowing the energy load controller system of the present
invention to implement a particular load energization map at
a particular time, comprises an oscillator 300 having its
frequency established by means of crystal element 21,
The output of oscillator 300 is coupled to a frequency divider
302 which divides the crystal frequency, typically on the
order of 32768 Hz., to produce one output pulse each minute,
on line 303. The pulses on line 303 are coupled to the count
C input of a minute counter 305, configured to count between
~ero and 59 and to reset to zero on the 60th pulse.
The reset-to-zero in counter 305 generates a pulse on a line
307 coupled to the clock inpuL C of an hour counter 308
configured to count from ~ero to 23 and to reset to æero
on a 24th pulse received from line 307. The resetting to zero
.n hour counter 308 gene-:ates a pulse on another line 310,
coupled to the count C input of a day counter 312,
configured to count sequentially from one to seven and
` to reset to one on the eightll pulse. Thus, counters 305, 308
and 312 are configured to count the days, hours and minutes
of a full seven day week. The data output lines 305a, 308a
and 312a, respectively, of the minute, hour and day counters,
respectively, are routed to the data inputs of an associated
bidirectional bus driver 315, 316 and 317, respectively, which
are INTEL 8212 bus drivers in our presently preferred embodiment.
The outputs of each of bus drivers 315 -317 are coupled to
parallel data bus 12b. Data bus 12b is also coupled in
parallel to the data inputs of a second set of bidirectional
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~ RD-9838
bus drivers 321, 322 and 323, each having its respective
data output coupled to the pre-settable data inputs D of the
associated minutes, hours and days counters 305, 30~ and 312,
respectively. Address bus 12c is coupled to an address
decoder 325 configured to recognize three unique addresses
respectively associated with the day, hour and minute
functions; upon recognition of the previously selected
addresses, one of address decoder outputs D, H or M is
energized. Each of the address decoder outputs D, H and
M are routed to a first data strobe input of both bi-directional
bus drivers associated with that timekeeping function. Thus,
the D address decoder output is routed to the first data
strobe input 317a and 323a of the day timekeeping function
I/O bus driver circuits; while the H address decoder output
is coupled to both first data strobe in~uts 322a and 316a of
the hour bus drivers; and tlle M output of the address
decoder is coupled to both first data strobe inputs 315a and . ~;
321a of the minute timekeeping function bus drivers.
The read control line 330 of control bus 12a is coupled
to a second data strobe input 315b, 316b and 317b of each
of the output bi-directional bus drivers 315-317, respectively.
The write control line 331, from control bus 12a, is coupled ~`
to the second data strobe inputs 321b, 322b and 323b,
of the remaining bus drivers, as well as being coupled to
one input of each of a set of three two-input AND gates 334,
335 and 336. The remaining inputs of the AND gates are
coupled to the associated output of address decoder 325.;
thus, the remaining input of gate 334 is coupled to the M output
the remaining input of gate 335 is coupled to the H output and
the remaining input of gate 336 is coupled to the D output
of address decoder 325.
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~ d'-~f; ~D-9838
In operation, time data is loaded (written) into real
time clock 20 by energizing the write control line 331
and transmitting the address, on address bus 12c, of the
time data which is presented on data bus 12b. Address
decoder 325 recognizes the proper address and energizes one
of the day, hour or minute lines. The energization of write
line 331 and one of the D, .I or M lines enables one of
AND gates 334, 335 or 336 and the associated preset enable
(PE) input of the associated one of counters 305, 308 or 312.
The data is removed from the data bus and entered into the
appropriate bus driver by simultaneous energization of
the first input thereof (facilitated by the energization of
one of the three address decoder outputs coupled to the first
data strobe input of each bus driver) and energization of
the second data strobe i-.~put coupled to write line 331.
The data is taken from the data bus and is transmitted through
the appropriate input d~iver 321, 322 or 323, to the data
D input of the appropriate counter. Presence of data at the
D data input of the counter along with energization of the PE
counter input causes the data to be loaded into the counter
and the counter to count from that starting data. By
sequentially placing the three sets of data on the data bus with
presentation of the associated address on the address bus,
the three counters of the real-time clock are loaded with the
desired time data~
Time data is read out fYom the real-time clock by
causing read line 330 to be energized and issuing the
address of the desired tlmel~eeping function: days, hours or
minutes, Address decoder 325 recognizes the address and
raises the appropriate output line, and enables one control input
-50-
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~2.~ RD-9838
of one of bus drivers 315, 316 or 317. As read line 330 is also
energized, the remaining control input is enabled and the proper
day, hour or minute data output bus driver is caused to transmit
data from the appropriate counter output 305a, 308a or 312a,
respectively, onto data bus 12b for s-ubsequent utilization by
the CPU.
There has just been described a novel energy load controller
system capable of being programmed to define each of several
maps of energy utilization load programming in a plurality of
sectors, each containing a plurality of controllable loads.
:~ovel real-time clock and receiver/decoder circuitry useful
in load control processors of this programmable energy load
controller system have also been disclosed, as well as novel
means of remotely actuating loads from a remote location using
the telephone system.
Other novel features and advantages of the present invention
will be apparent when reference is again made to Figure 2 of
the drawings wherein a floor plan of offices, corridors and ,
rooms is shown. In actuality, the corridor and offices and
rooms are described in terms of a floor plan, but the layout
of the lighting fixtures in these areas is essentially com-
parable to a ceiling plan of lighting.
In the preferred embodiment described and illustrated
herein, the lighting map is really a designation for the ;
energy level of each of the lighting fixtures illustrated
in Figure 2 or in the larger facility of which the rooms, `
offices and corridor of Figure 2 are a part. If eight
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RD-9838
different lighting maps are laid out,which can be identified
as Map A through Map H, the operator of the system has a choice
of installing any one of the eight maps in the system through
the schedùling means which are described above. In other
words, the schedule can be established so that the real time clock
will call for a first Map A be installed at a certain-time
of day, while another Map B could be installed at
a different time of day and yet another Map C could be
installed at a still later time of day. But the installation
of the maps according to the time of day alone assumes that
all of the use or utilization of the facilities will remain
fai.rly constant and that the environmental lighting conditions
will remain essentially constant or at least will follow
essentially the same daily schedule. However, if the outer
solid line at the upper, left-hand and lower surfaces of Figure
2 are considered to be outside walls and these walls are provided
with windows, then it will be apparent that depending on the
position of the sun, the time of the day, the clear or overcast
nature of the sky, the amount of light entering the windows
will vary. It is entirely within the purview of this invention
to provide additional maps which accommodate the increase
or decrease of light through the windows at the outer wall of
the building. For example, all of the lighting fixtures at the
outer wall of Room No. 2, that is Fl-F4 of L3, can be set at
either half ("low") light when there is a moderate level of light
entering Room 2 from windows on its outer wall or, alternatively,
these fixtures can be fully shut "off" when there is a high
level of light entering the windows at the outer wall of
Room No. 2. .
Similarly, the lighting fixtures at the perimenter of
-52-
. . . ~ .. : :
~ ~ 2'~ ~ ~ RD-9838
Office No. 1 and adjacent the outer wall, can be adjusted
to be either half-off ("low'l) or full-off ("off") depending
on the level of light entering through the windows of the
outer wall. A fourth Map D might be provided to have each of
the lighting fixtures at the outer wall at a half level
of light and yet another Map E can be provided to have each
of the fixtures at the outer wall shut off. One of the
unique features of the control.mechanism of the present
invention is that once the maps are provided, they can be
initiated by a number of alternative means and can also be
initiated in parts rather than in their entirety. It should
be nderstood that a map, such as fourth Map D, is really
a predetermined condition for each of the lighting fixtures
of all of the fixtures within a particular facility or a
mapped area within the facility.
In one preferred embodiment of the invention described
above, the energy utilization patterns may be established
independently of any sectors which are established within :
the mapped area. However, a part of the novelty of the
control system and mechanism of the present invention is that
one pattern can be in force in one sector of the facility while ~
a different pattern can be in force in another sector, ~ ;
adjacent or remote from the first area, of the same facility
or in another facility. For example, if Room No. 2
constitutes one sector in the facility and Office No. 1
constitutes another sector of the facility, a sector pattern
from Map D can be put into effect in Room No. 2 and a
sector pattern from Map E, or any other map, can be put into
effect in Office No. 1. As an example, this might be done
because there :Ls more outer wall space and, accordingly, more
-53-
.2~ t$
RD-9838
potential window space in Office No. 1 than there is
in Room No. 2. Accordingly, Office No. 1 would receive more
light through the windows of Office No. 1 than Room No. 2
would receive from the windows of Room No. 2. Thus, Office
No, 1 might have a map which has all of the perimeter lighting
fixtures including Fl-F5 of Ll plus Fl and F4 2
full "off" condition pursuant to Map E. By contrast, Room No.
2 might have the perimeter fixtures Fl-F4 of L3 in the half-off
("low") condition pursuant to application of Map D to Room No.
2. As explained above, the way in which an energization pattern
or a map is pu~ in force in a sector is by employing the
teIephone interrupt to address a particular sector and then
once the sector is addressed to install a specifically selected
map pattern in that sector. The applicable por,ion of each of
maps A through H can be installed in a particular sector, such
as in Room No~ 2, even though an entirely different map is
installed in an adjoining sector, such as in Office No. 1.
Accordingly, it is possible for the occupant of Office No. 1
to make contact with the central facility through a tone-
coded telephone instrument and to call into operation within
Office No. 1 a particular map pattern which suits the lighting
needs of Office No. 1. Independently, the occupant or
occupants of Office No. 2 can contact the central facility
through a tone-coded telephone instrument and a call into ;
effect in Office No. 2 the lighting map pattern which is "
particularly suited for Office No. 2.
Considering next an arrangement of lighting within Office
No. 2, which may be, for example, an executive office in
which there is a desk for desk work of the executive occupant
of the office and also a conference table for holding
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.. , . . -
,:, , , , ` :
,~ "
s r
~ RD-9838
conferences within the same office. The desk area may be in
the left hand side of the room within the lighting area of L6
and the conference area may be in the right hand side of the
; room within the lighting area of L7. It will be apparent
that the lighting requirements in the office will change
from time to time depending on whether a conference is in
session within the office or whether the executive is at work
at his desk. The lighting needs within the office may vary
considerably, as additional light may also enter the office
through the windows in the external walls on two sides of the
office. The change in lighting output of the lighting fixtures
based on the change in the entry of light through the windows
can be carried out in accordance with the scheme described
above with reference to Room No. 2 and Office No. 1. However,
in addition to those changes in the lighting within the
office, responsive to changes in the ambient light entering
the office through windows, the lighting need and use within
the office will also change xesponsive to the areas of the
office which are then in use. A portion of Map M5 might be
the proper sector map pattern needed to establish the proper
lighting in the left hand side of the office where the desk
is located, when the desk is in use, and may be established -
to additionally cause the light in the right hand side of
the office, where the conference table is located, to be
energized to a "low" or`partially "low" and partially "off"
condition. Conversely, when the conference area, on the
right hand side, of the office is in use, portions of another
map, e.g~ F, can be put into effect in the office to provi~
adequate lighting in the lighting fixtures of lighting control
L7 and the lighting fixtures of lighting control L6 can be
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energized to "low" level or turned "off" because the desk
area was not in use. Again, once these maps are established,
the occupant or occupants of the office can access the
central facility through the telephone and install Map E, F
or G, or one of the other of a number of maps which can be
established for the office, depending on the various lighting
needs and the ambient lighting conditions of the office at
different times. It will also be understood that the addressing
of a sector constituting Office No. 2 can be done through the
telephone interface completely independently of whatever lighting
instructions are given to the central facility for Office No.
l and Room No. 2, as discussed hereinabove.
It will be understood that Maps A through H, or Maps M
through Mn (where n is some integer greater than one), are
n~t established for a sector only but are established
for all of the lighting fixtures within a map area. Thus, a
Map Ml would include a lighting condition for each fixture
of Figure 2 and in fact of all fixtures of a mapped area of
which Figure 2 is a part. Further, it will be understood
that the map, once established, will remain in effect for all
lighting fixtures whether or not the whole map or any part
of the map is used. Use of a full map occurs when it is
~nstalled in all of the fixtures of a lighting system, such
as those illustrated in Figure 2, in accordance with a schedule
for map installation as described hereinabove. A partial
use of a map occurs when a first map, such as Map C, is scheduled
to be in effect, but the occupants of a particular sector use
the telephone interface 37 to install a different map in their
sector. In fact, a change in the map in effect in a particular
sector can be changed by a person in another sector. For
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example, if the secretary of the executive from Office No 2
is located in Room No. 2, she can access microcomputer 12
through telephone lnterface 37 from a telephone in Room No. 2
and adjust the lighting in Office No. 2 by changing the map
in effect in that office or she can simply turn off all
lights in Office No. 2 by proper tone instructions once the
Office No. 2 sector has been addressed through telephone
interface 37.
As another il'iustration, with reference to Office No. 3, if
this office has a number of desks> as for example, in the
corners under the lighting fixtures Fl> F3, F6 and F8, then a
number of different maps can be provided for the lighting
of this office depending on the presence or absence of persons
at the various desks in the corners of the office.
Thus> Map A might provide light at a full ("high") level from `'
fixture Fl and low level light from fixture F4 with all the
other light fixtures being in the "off" condition.
A second map might provide full ("high'~ light at Fl and F3>
half (low") light at F2 and F4 and place the other fixtures ~ -`
in the "off" condition. A third map might provide full light
at Fl> F3 and F6 and half light at F2 and F7> if three of the
four desks of the office were occupied. Obviously> other
combinations of high, intermediate and off ene~gy utilization
conditions can be provided for the lighting fixtures in
Office No. 3. If Office No. 3 is one of the sectors
defined in the overall lighting system, then any of the
occupants of the office can address the central facility 11
through telephone interface 37 and put into effect the
lighting map within the sector of Office No. 3 which is
appropriate for the use then being made of that office at the
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time. In addition, there is the factor of the change in the
ambient light entering the office through the exterior wall
windows and additional maps which provide for adjustment of
the lighting within the sector of Office No. 3 can be defined
pursuant to the scheme described above so that the most
appropriate lighting will be in effect depending on the ambient
source of lighting and the occupants of the office and the
work they are doing.
Another facet of the control system provided pursu.~nt to
the invention as described above is that once a sector has
been addressed through telephone interface 37, there are three
elementary commands which can be addressed to all of the
lights within that sector independently of any map. The
three commands are all lights "high", all lights "low" and
all lights "off". Accordingly, if the sector defined
as Room No. 2 is addressed by tone-coded telephone and a
command is given to put all lights to the "low" condition, then
all lights in the addressed sector will be put to the "low"
condition independently of any map which may be pertinent to
the sector of Room No. 2.
Another unique feature of the control system of this
invention is that each sector can be identified and defined,
and once a sector is so defined, can be addressed via
telephone interface 37. In one preferred mode of the
present inventi.on, the primary purpose of the sectors is to
permit addressing a particular group of lighting fixtures
by a direct swi.tching mechanism. In the preferred illustration
given, the tone-coded telephone is the switching mechanism
which is described. However, it will be understood that
other switching mechanisms may be employed in controlling the
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lighting within a sector. For example, in relatively
smaller mapped areas of a building, a conventional card-reader
mechanism can be employed in establishing schedules as well
as in establishing maps to be set in place by the established
schedule and further in defining sectors and in controlling
those sectors to impose different maps into different
sectors. The imposition of a map in a particular sector would,
of course, be out of the normal map sequence inasmuch that, if
the map of the established sequence is the one which is
desired, there is no need to override the scheduled map to
impose a different map in a particular sector or sectors based
on conditions or activities within that sector. ;
Also 2S explained more fully hereinabove, if a particular
map is in effect in a sector(T.~hetller this map is the established
scheduled map to be in place for that sector or is a different
map) there can be certain desirable lighting arrangements for -
a particular temporary use or condition of the area within
the sector. If minor change in the existing lighting map is
desired, it is also feasible, as is explained more fully
hereinabove, to directly address a particular lighting
fixture or fixtures within the area and to modify the
lighting of the individual lighting fixture(s). Such
modification is intended for temporary adjustment of lighting.
Such telephone addressing of an individual fixture will
override the scheduled map in effect or a prior temporary map
imposed by addressing the sector. Normally, pursuant
to the preferred embodiment of the invention described above, ;
the override of an individual lighting fixture will remain
in effect only during the remainder of the day on which the
override was imposed. On the following day, the normal
scheduled maps will go into effect.
Accordingly, if it is desired to make a change in the
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lighting of an individual fixture or fixtures over an extended
period, the manner in which this is accomplished pursuant to the
present invention is by changing the assigned energization of
that particular fixture or fixtures in one or more of the
several maps which establish the energization level of each of
the fixtures within the mapped area, including the fixtures
within any smaller areas defined as sectors.
One of the advantages of the present invention il].ustrated
by the description above is that the lighting can be modified
from time to time during the eay, for example within a
particular office, to meet the optimum need for efficient
lighting during the period in which the premises is in use.
For example, if someone is working in Office No. 2 late
in the day, the lighting within the office can be
independently controlled through telephone interface 37 although
according to the scheduled map all light fixtures in the
office would be off. The lighting within the office can be
made fully adequate in the area of the executive desk in the
office and "low" or "off" in other areas of the office. This
will be so even though all of the lights in Room No. 2,
Office No. 1, Room No. 1 and Office No. 3 are either at a ;~
very minimal level for security purposes or are entirely off.
For example, the lights of fixtures F6 and F7 of L6 can be left
full on and the lights F5, F2, F3, and F8 and L6 can be left
half on with the lights Fl and F4 completely off. Further,
in L7, Fl, F4 and F6-F8 can be left completely off; F2, F3
and F5 can be left half-on (with Fs being left half on for
easy access to the door). Such an after-hour executive
offdce work map can be established as one of the maps stored
in the mass data storage means 1~ and can be called into
effect by the subject control scheme described above.
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While one presently preferred embodiment of the present
invention has been disclosed herein, various modifications and
variations will now become apparent to those skilled in the art.
It is our intent, therefore, to be limited only by the appending
claims and not by the specifics of the single embodiment
. , .
presented herein.
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