Note: Descriptions are shown in the official language in which they were submitted.
BACKGROUND OF THE INVENTION
, s
. 1 1. Fièl~ of the Invention
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This invention relates to a supervisory control system,
and more particularly, to a method and apparatus for an im-
proved supervisory control system.
2. Description of the Prior Art
Supervisory control systems often must operate in an
extremely noisy electrical environment. For example, such a
system used to monitor and control status monitoring stations
for a network of substations and transformers connected to a
power plant of a power utility is highly susceptible to the
high voltage and electrical noise environment. To cope with
such an environment, typically prior art systems have been
arranged to repetitively send a signal and detect and compare
the repetitively sent signals and send a return signal when
the comparison indicates reliable reception. But such a
system is not found very rel~able when a high level of noise
is injected into the system from the power plant substations
or transformer or o~her external sources. Generally the
prior art systems are found incapable of providing reliable
monitoring and supervisory functions in a noisy environment.
Also it is found that as the number of the monitoring
stations increases and as channels allocated for trans-
mission of monitoring, status, supervisory, and similar
signals get crowded, the prior ar' supervisory systems are
found incapable of expanding their capability. To increase
capacity, the systems require additional communication
channels. ~rhey are not capable of sharing existing radio
channel o using existing voice communication channels.
They do not allow easy and inexpensive expansion fGr addi-
tional stations that grow upwards to thousands of stations.
Confronted with this situation, some prior art systems
resort to manual operation where interrogation of the stations
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is more generally accomplished by operator assisted manual
methods~
In short, none of the prior art systems provides a
satisfactory automated supervisory control system that is
highly reliable and that can operate in a noisy environment
and that can handle large numbers of monitoring stations.
For the foregoing and other shortcomings and problems, there
has been a long felt need for an improved supervisory control
system.
OBJECTS OF THE INVENTION
. .
It is an object of the invention to provide an improved
supervisory control system.
It is a further object of the invention to provide an
improved supervisory control system that is highly reliable
in the transmission and reception of status and command
signals.
It is a still further object of the inventicn to provide
an improved supervisory control system that includes a large
number of stations and that can be easily expanded to accom-
modate additional stations.
It is a still further object of the invention to provide
an improved supervisory control system that can operate
reliably in noisy and hostile environments.
~UMMARY OF THE INVENTION
In accordance with the present invention, the afore-
men~ioned problems and shortcomings of the prior art are
overcome and the aforementioned and other objects are attained
by an inventive method and an inventive system.
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More particularly, there is provided:
A display system comprising:
~ plurality of stations having means for providing
respective status signals;
a predetermined number of display elements;
a plurality of memory elements for storing the status
signals;
means for providing a train of first clock pulses;
first counting means;
an enable signal source for applying an enable signal
to said first counting means to count a predetermined number of
first clock pulses in successive frames and provide a first
output pulse for each of the frames;
second counting means responsive to the enakle signal
for counting a predetermined number of the first output pulses
and providing a second output pulse thereafter;
said plurality of memory elements being responsive to
the second output pulse for storing the status signals;
means for providing a train of second clock pulses;
third counting means for counting a predetermined
number of second clock pulses in successive frames and providing
a third output for each of the frames; and
said plurality of memory elements being responsive to
the third output pulses for reading out the stored status
signals.
There is also provided:
A display ~ystem comprising:
a plurality of stations having means for providing
respective status signals;
input means for receiving the status signals;
a predetermined number of display elements;
a plurality of memory elements for storing the status
signals;
means for providing a train of first clock pulses;
first counting means;
an enable signal source for applying an enable signal
to said first counting means to count a predetermined number of
first clock pulses in successive frames and provide a first
output pulse for each of the frames;
second counting means responsive to the enable signal
for counting a predetermined number of the first output pulses
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and providing a second output pulse thereafter;
said plurality of memory elements being responsive to
the second output pulse for storing the status signals;
means for providing a train of second clock pul~es;
third counting means for counting a predetermined
number of second clock pulses in successive frames and providing
a third output for each of the frames; and
said plurality of memory elements being responsive to
the third output pulses for reading out the stored status
signalsO
There is further provided:
A display system for a supervisory system having a
plurality of stations that provide respective status signals,
the display system comprising:
a predetermined number of display elements;
a plurality of memory elements connected to the
plurality of stations and to the display elements for receiving
and storing the status signals in words and transmitting the
status signals to the display elements;
means for providing a train of first clock pulses;
first counting means ~onnected to the means for
providing a train of first clock pulses;
an enable source connected to the first counting means
to apply an enable signal to the first counting means to cause
the first counting means to count a predetermined number of
first clock pulses in successive words and provide a first
output pulse for each of the words; and
second counting means connected to the first counting
means, to the enable source, and to the plurality of memory
elements, the second counting means responsive to the enable
signal for counting a predetermined number of the first output
pulses and providing a second output pulse to the plurality of
memory elements to direct storage of the status signals in the
memory elements.
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BRIEF DESCRIPTION OF THE DRAWINGS
Fig. 1 illustrates a supervisory control system of the
present invention.
Figs. 2a, 2b and 2c illustrate the format of the coded
signals which are utilized by the supervisory control system
Fig. 2a shows in detail the organization of the status
signal transmitted by the respective stations to central
control station. Fig. 2b shows in detail the organization
of the command signal transmitted by the central station to
the stations. Fig. 2c shows the detailed timing for a
frequency shift keying modulated coded signal with a randomly
selected sequence of bit states.
Fig. 3 shows a general block diagram of the central
control station.
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Fig. 4 shows a detailed block diagram of the display
driver unit and the display unit which are sub-units o~ the
central control station.
Figs. 5A, 5B and 5C in combination show a block diagram
of the status and control station.
Fig. 6 shows a block diagram of the control station.
Fig. 7 shows a block diagram of the status station.
I. GENERAL DESCRIPTION
A. System
Re'erring now to Fig. 1 of the drawings, it is intended
that the stations of the supervisory control system can be
located physically adjacent to one another or can be remotely
located from one another and interconnected by a communication
means. It is further intended that many more of each type
of station can be added to the configuration of the system
shown in Fig. 1. The communication links shown in Fig. 1
can be either radio communication links or telephone wire
line communication links. Many other means for providing
communication links and system configurations can be devised
by those skilled in the art.
Central control station 31 is connected by telephone
wire lines to radio transceiver 30, status station 42,
control station 45, status and control station 47, and
central control station 32. Radio transceiver 30 communicates
by way of a single duplex radio channel 17 to radio trans-
ceiver 41, radio transmitter 22, radio receiver 25, and
radio transceiver 29. The central control station 40 is
connected to radio transceiver 41. The status station 20 is
connected to radio transmitter 22. The control station 23
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CM-77884
is connected to radio receiver 25. The status and control
station 26 is connected to radio transceiver 29. The status
stations 20 and 42 monitor up to 16 input signals 21 and 4~
respectively. Control stations 23 and 45 can send out up to
8 output signals 24 and 46 respectively. Status and control
stations 26 and 47 can each monitor 16 input signals 27 and
48 respectively and can control up to 16 output signals 28
and 49 respectively.
The supervisory control system of the preferred embodi-
ment has the capacity for 2,048 stations. However, systems
can be devised with many more or even less stations. Each
of the 2,048 individual stations can have up to 16 output
signals and 16 input signals. Each of the central control
stations 31, 32, 40 can interact with 512 stations. Thus,
four central control stations are required for a supervisory
control system with 2,048 stations. For the purpose of
increasing reliabilitly, two redundant central control
stations could be co-located and configured to control the
same 512 stations.
In the supervisory system shown in Fig. 1, messages are
communicated over a transmission channel, a radio channel or
a plurality of wire lines, between the central control
stations and the plurality of status, control, and status
and control stations. Command signals are sent from the
central control stations to control stations or status and
control stations to enable particular stations to send
selected output signals. Status signals, reflecting the
change of state of input signals, are transmitted from
status stations or status and control stations to the central
control stations where the changed status signals are displayed
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as alarm conditions. The operator manning the central
control station then acts on the alarm conditions as called
for by the changed status signals.
B. Signalling Format and Scheme
The signalling scheme used in the present invention is
essentially digital in nature. The status or command signals
are rendered in digital word form. Each digital word includes,
for convenience, a given number of digital bits, for example,
32 bits. The signals in the digital word forms are encoded
into the well known frequency shift keying ~FSK) format for
transmission purposes. To assure transmission and reception
in noisy environment, the signals are sent repetitively.
For example, a command or a status signal, in the form of 32
digital bits, is sent in successive frames. Each frame may
have a given number, for example, 20 digital words transmitted
in series, thereby providing message redundancy. The number
of frames repeated for transmission is selected to assure
correct transmission and reception. In the present system
the frames are repeated up to 8 times. Preferably the
number of frames of the digital word signals repeated is
selected to assure time diversity, that is, given a particular
interval of any noisy transmission that may have taken three
frame intervals, by repeating 8 times, the receiver is
enabled to disregard the noisy frames essentially, and
receive the remaining frames properly in receiving the
transmitted signal.
Figs. 2a and 2b show detailed illustrations of the
digital bit organization of the 32 bit digital word for the
status and command signal, respectively.
Referring to Fig. 2a, the status signal 200 in the form
of a 32 bit digital word is composed of 26 information bits
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(bit 0 through bit 25) and 6 security bits (bit 26 through
bit 21). The information bits are made up of station control
(bit 0), station address (bit 1 through 11), alarm group
address (bit 12 through 14), check-back bit (bit 15), alarm
bits (bit 16 through 20), primary power fail bit (bit 24)
and a change-of-state bit (bit 25). The station control bit
201 (bit 0) is always coded as a logic 1. The station
address 202 (bits 1 through 11) is a binary address which
identifies each individual station. Bits 10 and 11 identify
one of four central control stations. The alarm group
address 204 (bits 12 through 14) is used to select up to 8
alarm groups of which only two are presently used in the
preferred embodiment. The check-back bit 205 (bit 15) is
used for system control, as will be explained shortly. Each
of the alarm bits 206 (bits 16 through 23) is associated
with one of eight binary status signals. The primary power
fail 207 is indicated by bit 24. The change-of-state (COS)
mode 208 i5 indicated by bit 25.
The security signal includes bits 26 through 31 and is
composed of a 5 bit Bose Chaudhuri (BCH) cyclic code and a
parity bit for detecting errors in the status signal 200.
The status signal 200 in the form of 32 bit digital
word is transmitted from the status stations 20 and the
status and control stations 26 to the central control stations
31 to report the status of the monitored input signals 21
and 27 respectively (see Fig. 1).
Referring to Fig. 2b, the command signal 250 is likewise
composed of 26 information bits and 6 security bits. The
information bits are made up of the station control bit (bit
0), the station address (bits 1-12), the command group
address (bits 12-14), an unused bit (bit 15), the command
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CM-77884
bits (bits 16-23) and the command signal control bits (bits
24 and 25). The station control bit 251 (bit 0), if encoded
as a logic 1, directs the command signal to a particular
station, and, if encoded as a logic 0, directs the command
signal 250 to a group of stations. The station address 252
(bits 1 through 11) can select any one station or a group of
stations in response to the station control bit 251. The
command group address 254 (bits 12 through 14) can select
any one of 8 command groups, although only 2 command groups
are used in the preferred embodiment. The unused bit 15 is
a logic 0, and is presently not allocated to a particular
function in the preferred embodiment. Each of the command
bits 256 (bits 16 through 23) encodes a binary command for
each one of the 8 command signals. The command signal
control word 257 (bits 24 and 25) selects one of 4 operational
modes in the stations. The station operational modes are
the execute mode, interrogate mode, select mode and acknowledge
mode, as will be explained later.
The status signals and command signals are encoded
according to frequency-shift keying (FSK) modulation, which
shifts between 900 hertz and 1500 hertz tone signals for
each bit of the coded signal and codes logic 1 bits with a
pulse width twice as long as logic 0 bits. Fig. 2c shows a
16 bit segment of the 32 bit digital word in the ~orm of a
frequency-shift keying (FSK) modulated signal 280. The FSK
modulated signal includes a synchronization signal and a
digital word as illustrated. The synchronization signal 281
is coded with a pulse width four times as long as that of a
logic 0, the logic 0 pulse width being represented by a time
period "T". The digital word is made up of transitions
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CM-77884
between 900 and 1500 hertz in T or 2T time intervals as
illustrated. The transitions 282 between tones, 900 hertz
and 1500 hertz, are illustrated by the changes in state of
the waveform. The FSK modulated signals can be transmitted
over a radio channel or over a telephone wire line that has
sufficient bandwidth to pass the 900 hertz and 1500 hertz
tones.
The transmission of the coded signals between the
stations utilizes both the message redundancy and the time
diversity principle to insure that the coded signals are
received in the noisy environment. To obtain message
redundancy, each coded signal is transmitted up to 20 times
in a two second interval or can optionally be transmitted
eight times in a one-half second interval. The message
redundancy increases the probability of reception under
conditions of severe noise. The reception of just one
of the coded signals is sufficient to get the message through.
Time diversity is achieved by repeating the two second
messages (or one-half second messages) up to eight times at
intervals of approximately one minute. If the first trans-
mission of messages is lost due to radio frequency inter-
ferance or noise interferance on a telephone line, then sub-
sequent messages have a high probability of being received.
The number of repetitions of the bursts of messages can be
adjusted to suit the particular system. In addition, a
channel monitor can be used to ascertain if there is any
activity on the radio channel or on the telephone wire line
before transmitting a particular burst of messages. The
channel monitor would insure that two stations are not
attempting to transmit messages at the same time.
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A received coded signal is subjected to a number of
tests to determine that the coded signal is valid. The FSK
modulated coded signal is checked for proper bit width of
the binary signals and the synchronization signal. The
coded signal is checked to insure that a synchronization
signal precedes and follows the coded signal and also that
the coded signal is composed of exactly 32 bits. The security
portion of the coded signal includes checking the Bose
Chaudhuri (BCH) cyclic code and the parity code. Together,
the Bose Chaudhuri and parity checks reject all one bit
errors, all two bit errors, all three bit errors, approxi-
mately 96% of all four bit errors, all odd numbered errors
and all bursts of errors up to 31 bits in length. The level
of security provided insures very reliable system operation
under high noise conditions.
The reliability of the signalling scheme is further
enhanced by use of a check-forward or check-back mode of
operation or both, where necessary. Briefly stated, according
to the check-forward mode of operation, a command signal
received at the remote stations are compared to an applied
command signal, which is the stored command signal that is
momentarily applied to the output means, and if the received
command signal is identical to the applied command signal,
the output means is permanently enabled. By way of the
check-forward method, the circuitry at the remote station is
checked at the output means, not just at the receiving
means.
According to the check-back mode of operation, a received
command signal is transmitted from a remo$e station back to
central control station where the central control station
veri~ies that the command signal is identical to the signal
CM-77884 1~3~374
it had oriqinally sent. Then, the central control station
transmits the command signal again for subsequent execution.
The remote station receives the second transmission of the
command signal and enables the output means accordingly.
The signalling scheme further provides that the remote
station can perform a check-forward operation on the first
and second transmissions of a check-back command signal.
The check-back mode of operation which requires three trans~
missions, two from the central control station and one from
the remote station, provides additional reliabilitly at the
cost of creating congestion on the communication channel.
II. DETAILED DESCRIPTION
A. Central Control Station
A central control station is used to provide all necessary
control functions for the system. The central control
station includes a computer, a plurality of peripheral
equipments such as keyboard for operator-machine interface,
teleprinter, FSX transceiver facility, and the like. The
station also includes a plurality of display units, and
display drivers for driving the display unit under the
command of the computer.
The present illustrative central control station is
designed to handle up to 512 stations. The central control
station computer has a stored program for providing system
flexibility to accommodate a wide variety of requirements
and options. The stored program of the central control
station has an executive program and a plurality of sub-
programs for providing the features and operational capabilities
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described hereina~ter. The various programs can be written
by one skilled in the art based on the following description
of the central control station features and operation. The
central control station man-machine interface allows an
operator to interact with the stations in the system for
various diverse functions as will be explained in detail
hereinafter.
Referring to further details, as illustrated in Fig. 3,
the central control station 300 includes a computer 301, keyboard
and pushbutton switches 302, a teleprinter 303, an FSK
transmitter and receiver 307, a radio or wire line unit 308,
display driver units 304 to 306 and display units 320 to
324. The computer 301 can be any of a number of commercially
available minicomputers or microcomputers, such as the
Motorola M6800 system. The computer 301 samples the status
of the keyboard and pushbutton switches 302. The keyboard
can be of any suitable type. For example, it can be of the
type that has a 3 X 5 array of pushbuttons including the
digits 0 through 9 and alphabetical characters A and B. The
keyboard is similar to a telephone keyset. The pushbutton
switches include an entry clear key, message send key,
printer control keys, time set key, operation mode select
keys, an audio alarm reset key, and display control keys.
The functioning of the keyboard and pushbutton switches will
be discussed shortly.
The computer 301 is of the type that can be operated to
provide an output to an 80 column serial ASC II external
printer 303. The teleprinter 303 is driven by the computer 301
and automatically prints out all status signals received from
the stations, an indication of the status signals which have
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changed, all operator initiated command signals to the
stations, summaries of the status of the stations at predetermined
time intervals and any other types of information. Received
status signals, which indicate a change-of-state (COS) of
one or more of the status signals, are referred to as alarm
messages and cause an audible alarm to be activated. The
audible alarm is turned off by depressing the audio reset
pushbutton.
By operator entered directives, the stored program of
the central control station can provide the following printouts:
status summary of all stations or a set of stations;
status of a selected station; and
COS status for all stations or a set of stations. The
printer control keys, print disable, alarm print, and summary
print, together with the keyboard are used by the operator
to select the foregoing printouts.
The computer 301 transmits command signals and receives
status signals through thP FSK transmitter and receiver 307.
The FSK transmitter and receiver 307 performs the FSK con-
version for transmitted and received signals and is connected
to a radio or wire line unit 308 which provides a transmission
channel to the stations in the supervisory control system.
The stored program in the computer 301 performs all the
validity checks on the received status signals and generates
the pulse duration timing and security codes for the trans-
mitted command signals.
The computer 301 communicates display data to and
receives display unit status from the display driver units
304, 305 and 306. The computer 301 communicates to the
display driver units 304 to 306 by means of an eight bit
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data bus 340, and update clock signal 341, an update start
signal 342 and a flash switch signal 343. The display
driver unit 304 communicates with the display units 320 to
323 by means of 24 display driver signals 352, 8 display
driver signals 351, and flash reset switches 353 to 356.
The display driver unit 304 stores the data received from
the computer 301 to enable the light emitting diodes (LED)
displays in the display units 320 to 323. The display units
320 to 323 each contain up to 48 LED display indicators.
Each of the display units can provide a visual indication of .
the status of any of the stations in the system. In the
preferred embodiment, the computer 301 can communicate with
up to 16 display driver units each controlling 4 display
units, for a total of 64 display units. Three of the display
units are combined to provide a control display, which
includes a 6 digit 7-segment display for display of the
time, keyboard entries and program control modes; command
indicators; a time set indicator; a set indicator; a printer
indicator; a set call indicator; an audio disable indicator;
and a display overflow indicator.
The central control station incorporates a shared
display concept which provides fewer display units than
there are stations in the supervisory control system. A
portion of the display units is organized together as a
rolling display. The display units in the rolling display
physically are located side by side to facilitate observation
by an attendant. Alarm messages are entered into the leftmost
display unit of the rolling display and the changed status
signals are flashed in the display. The flashing of the
received alarm message can be reset by depressing the reset
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pushbutton for that display unit. If an alarm message is
received from a station and the rolling display is completely
filled, the status signal for that station is stored in the
overflow memory in the computer for subsequent display, and
the display overflow indicator is flashed.
By depressing the roll key, the status signal in the
leftmost display unit is deleted, the status signals in the
display units to the right of the vacated display unit will
each be shifted to the left, and the highest priority message
in the overflow memory will be displayed on the rightmost
display unit in the rolling display. Flashing status signals
that have been rolled out of the rolling display are stored
back into the overflow memory. The overflow memory can
store all of the alarm messages which exist in the system.
A specific station can be rolled off the rolling display by
entering the octal coded station address from the keyboard
before depressing the roll key. By repeatedly depressing
the roll key, all of the alarm messages with a flashing
indication in the overflow memory can be reviewed in the
rolling display.
To fix a display unit in the rolling display to a
particular station, a station address is entered from the
keyboard and the call fixed ~ey is depressed. The status
signals for the specified station will be displayed in the
leftmost display unit. If there are one or more previously
allocated fixed display units, the newly entered fixed
display unit will be the display unit immediately to their
right. Any number of display units can be fixed, providing
that at least one display unit remains available for alarm
messages. A fixed display unit is indicated by illumination
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of the decimal point in the rightmost digit of the station
number display.
The stored status signals of any station can be entered
into an available display unit by entering the station
address from the keyboard and depresslng the recall key.
Several different operation modes of the central control
station can be entered by using the operation mode select
keys and the keyboard. A parameter mode of operation is
used to select the frequency of automatic interrogations of
stations and to enter the stations which will be automatically
interrogated. The parameter mode is entered into and exited
from by consecutively depressing five numerical keys and a
sixth key for the particular operation desired. The sequence
of numerical keys entered is displayed in the control display.
An interrogate mode provides for manual interrogation
of a selected station or group of stations. To interrogate
a station, the interrogate key is depressed followed by
entry of the station address from the keyboard. If it is
desired to interrogate a set of stations, the set select key
is depressed before entering the station address. The
control display will indicate an error for incorrect entries,
and if so indicated, depressing the clear key will cancel
the entry. The interrogate command is then transmitted by
depressing the send key. The send key is depressed a second
time if it is desired to send the interrogate command while
the communication channel is busy. Additional transmissions
of the interrogate command can be provided by depressing the
send key for each desired transmission.
In order to send an acknowledge command, the acknowledge
key is depressed and the station address is entered from the
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keyboard. The set select key ~an be depressed before entering
the station address to send the acknowledge command to a
group of stations. If the acknowledge command has been
entered correctly, the send key is depressed to transmit the
command. To transmit the acknowledge command when the
channel is busy, the send key is depressed a second time.
Additional transmissions of the acknowledge command can be
provided by depressing the send key for each desired transmission.
The central control station also provides a control
mode of operation. Entry and exit from the control mode is
achieved by sequentially depressing six numerical keys. The
exact sequence of keys depressed can be uniquely specified
for a particular supervisory control system to provide
security from unauthorized entry of control commands. In
order to send a control signal, the control key is depressed
and the station address is entered from the keyboard. The
set select key is depressed to transmit the control command
to a group of stations. Next, the A or B key is depressed
to select the desired control group. Then, the numbers of
the control signals to be activated are entered from the
keyboard. The entire entry can then be reviewed in the
control display. If an error has been indicated, the clear
key can be depressed and the control command can be reentered.
To transmit the command signal, the send key is depressed.
The send key can be depressed a second time to transmit the
command signal while the transmission channel is busy.
Additional transmissions can be provided by depressing the
send key for each desired transmission.
The time in hours and minutes is displayed in the
control display unless data for a command signal has been
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CM-77884
entered or the parameter mode has been entered. When the
time is displayed, the decimal point between the hours and
minutes is flashing. In order to update the time, the time
set key is depressed. Next, the year, month, day, hour and
minutes are sequentially entered from the keyboard, and
finally the time set key is depressed again. The new time
setting is entered, displayed and printed out on the external
printer.
B. Display ~river Unit and Display Unit
The display driver units and associated display units,
under control of the computer, provide a visual indication
of the system status, including the status of the central
control station in the control display and the status of the
other stations in the system in the display units. Each
display unit provides status for an individual station,
including the station address, the status of 8 input signals,
and particular operational status of the station. If a
station reports an alarm condition, the displayed status is
flashed in the display unit until the flash reset pushbutton
is depressed. In the illustrative system, the computer
controls up to 16 display driver units which, in turn, drive
the control display and up to 61 display units.
The display driver unit contains a logic and memory re-
quired to drive the associated light emitting diodes (LEDs)
so as to achieve the display of the status signals re~uested
by the computer and to transmit the status of the flash
reset switches from the display units to the computer in the
central control station. The display driver unit has three
functional sections: a display control section which accesses
the display data from the memory and drives the LEDs accordingly;
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CM-77884
the memory update section which updates the memory in accordance
with the data received from the computer on the data bus;
and the flash switch selector which multiplexes the four
flash reset switches from the display unit onto the flash
switch signal to the computer.
Referring to Fig. 4, the display driver unit 400 is
shown with one of the four display units 450. The display
unit 450 contains a status display 451 which includes 48
LEDs to be illuminated. A four digit 7 segment display,
which contains 28 of the LEDs, is used to display the station
address. The decimal point LED in the rightmost digit is
illuminated to differentiate fixed display units from rolling
display units. The remaining 19 LEDs indicate the power
fail condition, the test condition, the station fail condition,
and the on/off condition of a group of 8 input signals for
that station, a green LED being illuminated for a normal
condition (off) and a red LED being illuminated for an alarm
condition (on). The flash reset switch 452 is depressed to
acknowledge reception of the signal change indicating an
alarm condition.
The display control section drives up to 192 display
LEDs organized in a 24 X 8 matrix in accordance with the
display data stored in the memory 415. The display LEDs
include both point displays and the elements of 7 segment
numer cal displays. A clock signal source 401 is applied to
the address counter 402 to produce a 5 bit binary address.
The clock signal source 401 provides a 5,000 hertz train of
clock pulses, having a period of 200 microseconds and a
pulse width of 20 microseconds. The 5 bit binary address
from the address counter 4G2 is applied to the address
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decoder 403 and to the address selector 414. The address
decoder 403 decodes the 5 bit binary address into 24 signals
which are then applied to the display drivers 404 to produce
the display driver signals 406.
The display driver unit 400 is assumed not to be in the
update condition. Therefore, the address selector 414
routes the 5 bit binary address from the address counter 402 -,
together with the output of inverter 413 to the memory
address lines 435. The memory 415 being in the read mode
places the data stored at the address selected by the address
lines 435 onto the data lines 434. The read-out data on the
memory data lines 434 is then placed in the 8 bit latch 420
in accordance with the clock pulse from the clock signal
source 401. The output signals from the latch 420 are then
applied to the display drivers 421 to provide the display
driver signals 408. The display driver signals 406 together
with the display driver signals 408 are then applied to the
status displays 451 in each of the 4 display units 450 to
illuminate the LEDs therein.
The address counter 402 continuously reads the 24 data
locations in the memory 415 and sequentially strobes the 24
rows of the display LEDs, while the data from the memory 415
enables selected LEDs in each row by activating the display
driver signals 408 for the column of the selected LEDs.
The memory update section of the display driver unit
400 stores new data into the memory 415. The memory 415 is
organized into two 24 byte sections so that data can be
updated in one section while data is being read out to the
displays from the other sec.tion. This organization of the
memory 415 insures that data is uniformly updated before
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being read out and applied to the display units 450. The
update of the memory 415 is started by receipt of the update
start signal 441 from the computer. The update start signal
441 is applied to inverter gate 440, the-output of which is
applied to toggle flip flop 442 and is provided to enable
address counter 424, unit counter 430 and pulse generator
431.
The update clock signal 423 is applied to the AND gate
4~2 and to the pulse generator 431. In other embodiments of
a display driver unit, the clock signal source 401 can also
be derived from the update clock signal 423 by appropriate
divider means. However, in the preferred embodiment, the
clock signal source 401 has been provided independent of the
update clock signal 423.
The AND gate 422 provides the update clock signal 423
g~ted with the output of inverter 444 to enable the address
counter 424 to count a predetermined number of the update
clock signal pulses, the number of pulses being 24 for the
preferred embodiment. The address counter 424 provides a 5
bit binary address signal to the flash switch selector 410
and to the address selector 414. The 5 bit binary address
signal from the address counter 424 is gated together with
the memory select signal 443 by the address selector 414 and
applied to the memory address lines 435 to provide the
addresses at which data is stored. The three most significant
bits of the binary address from the address counter 424 are
gated together with the unit enable signal 412 by the flash
switch selector 410 to successively gate the 4 ~lash reset
" switch signals 405 onto the flash switch signal 411 to the
computer.
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CM-77884
The address counter 424 provides an output pulse to the
unit counter 430 for each frame of 24 update clock signal
pulses from AND gate 422. The unit 430 counts a predetermined
number of the output pulses from the address counter 424 as
determined by the four switches 425 to 428 and then provides
a unit enable signal 412. The unit enable signal 412 is
activated for the next 24 pulses of the update clock signal
423.
The pulse generator 431, being enabled by the unit
enable signal 412, provides a pulse on the update time
signal 433 in response to each of the next 24 pulses of the
update clock signal 423. The pulses on the update time
signal 433 are relatively short compared to the period of
the clock signal from the clock signal source 401 and are
approximately 5 microseconds in the preferred embodiment.
The pulse generator 431 also provides a write enable ~ignal
432 which is of shorter pulse width than the update time
signal 433. The update time signal 433 is applied to the
address selector 414 to gate the address from the address
counter 424 together with the memory select signal 443 to
the memory address lines 435. The update time signal 433 is
also applied to the buffer gate 416 to enable the data bus
lines 407 to be routed to the memory data lines 434 and to
. the latch 420 to prevent the data in the latch 420 from
changing during the update time signal 433. The write
enable signal 432 enables the memory 415 to store the data
on the memory data lines 434 at the address on the memory
address lines 435. The update time signal 433 is also
applied to inverter 444, the output of which is applied to
AND gate 422 to stretch the output of the AND gate 422 and
prevent the update clock signal 423 from being applied to
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the address counter 424 and change the 5 bit address data
during the memory store cycle. This is necessary since the
update time signal 433 has a pulse width greater than the
pulse width of the update clock signal 423.
When 24 bytes of new data have been stored in the
memory 415, the update start signal 441 changes state and
causes toggle flip flop 442 to change the state of the
memory select signal 443, which causes data to be read from
the 24 bytes of the memory which were just updated with new
data. The foregoing process is repeated for the next update
cycle and new data is stored in the half of the memory
determined by the memory select line 443. At the end of
each update cycle, the memory select signal 443 changes
state so that the new data is read out to the display units.
The four switches 425-428 of the unit counter 430
provide for sixteen diffPrent unit enable signals 412 so
that each of the possible sixteen display driver units 400
can be consecutively enabled. The use of a data bus 407,
update clock signal 423 and an update start signal 441 can
be adapted to store data in a plurality of memories using
the principles of the foregoing embodiment. Only one clock
signal, the update clock signal 423, need be provided since
the clock signal from the clock signal source 401 can be
derived from the update clock signal 423 by appropriate
divider means. Likewise the number of LED indicators that
can be driven from the display driver unit 400 can be increased
or decreased to accommodate a particular application.
C. Status and Control Station
The status and control stations are used for monitoring
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the status and controlling the operation of external devices.
The monitored status, sensed from input signals, is coded
into status signals and sent to the central control station.
Command signals are received from the central control station
and enable the status and control station to send output
signals to the external devices. In the present illustrative
system, the status and control station can monitor up to 16
input signals from and send up to 16 output signals to the
associated external devices. The status and control station
has several different modes of operation which provide
additional message signal security, including the check-
forward mode and the check-back mode, as will be explained
shortly. The status and control station is weIl suited for
applications that require the status and control of unattended
remote stations in a supervisory control system.
The status and control station includes a radio or wire
line unit, a power supply, an encoder/decoder, an input
unit, and an output unit. The input unit monitors a plurality
of input signals and provides an output signal to the encoder/decode~
unit if one or more input signals has changed state. The
encoder/decoder unit loads a status signal, including monitored
input signals together with validity codes, into registers,
encodes the status signal according to FSK modulation and
sends the status signal by means of the radio or wire line
unit to the central control station. Coded command signals
from the central control station are received by the radio
or wire line unit and converted from FSK modulated signals
into digital words by the encoder/decoder unit. The command
word is loaded into registers in the output unit, and the
output unit sends out the output signals in accordance with
the command word.
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The detailed operation of the status and control station
can be understood by referring to Figs. 5A, 5B and 5C taken in
combination. The status and control station 500 interfaces
with a radio or wire line unit 580 in order to communicate
both status and command signals to and from the central
control station. The radio or wire line unit 580 provides a
channel monitor signal 501 which indicates when the radio or
wire line is in use. The channel monitor signal 501 is
applied to the control 505~ The radio or wire line unit 580
receives a push-to-talk signal 502 from the control 505
which enables the radio or wireline unit to transmit FSK
signals 504. The radio or wire line unit 580 also receives
FSK signals 503 which are applied to the FSK receiver 510.
The control 505 provides the necessary control signals
and timing for the various modes of operation of the status
and control station 500. The control 505 provides an
encode/decode signal 507 which provides for encode operation
to transmit a status signal and decode operation to receive
a command signal. An output enable signal 508 is provided
from the control 505 to enable the timing circuit 520. The
test switch 506 is applied to the control 505 to cause the
transmission of a status signal in response to activation of
the test switch 506.
The power supply 521 provides the supply voltage 530 to
the voltage regulator 522 and the DC to DC power supply 523.
The voltage regulator 522 provides the VDD supply to all the
logic circuits of the status and control station 500. The
DC to DC power supply 523 provides an isolated voltage
necessary for the input monitor and protection units 524 and
525. The power supply 521 provides a power fail indication
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signal 531 which is applied to the selector 528.
The encode mode of operation of the status and control
station 500 will be described next. The input monitor and
protection units 524 and 525 each monitor eight input signals
by means of a sensing circuit which is described in a related
Canadian Patent No. 1,070,410 'ISensing Circuit". Upon
sensing a change of state of one or more of the input signals,
the input monitor and protection units 524 and 525 provide
an input change-of-state signal 532 to the control 505. In
response, the control 505 provides the encode state on the
encode/decode signal 507. The control 505 also provides a
logic 1 on the output change-of-state (COS) signal 533 which
is applied to selector 528. For the test mode, the output
change-of-state signal 533 is a logic 0.
The timing circuit 520 being enabled by the output
enable signal 508 provides a frame synchronization signal
534 to enable the pulse duration generator 513 and by way of
selector 541 to load the various data regis~ers. The
selector 541 gates the frame synchronization signal 534 to
the load signal 536 in response to the encode state on the
encode/decode signal 507. In response to the load signal
536 the 12 bit shift register 546 is parallel loaded with a
logic 1 in the first bit position from VDD and an 11 bit
. station address from the address unit 545. The 4 bit shift
register 547 is parallel loaded with a 3 bit group code 537
from the input group selector 551 and a check-back bit 538
which is a logic 0 from the control 505. The 8 bit shift
register 526 is parallel loaded with the 8 signals from the
input monitor and protection unit 524, and the 8 bit shift
register 527 is parallel loaded with the 8 signals from the
input monitor and protection unit 525. The power fail
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indication signal 531 followed by the output COS signal 533
are consecutively applied to the serial input of 8 bit shift
registers 526 and 527 by the selector 528 in response to an
output signal from the timing circuit 52~. The selector 550
routes the serial data output from the 8 bit shift register
526 to the serial input of the 4 bit shift register 547 for
the first transmitted status signal and the serial data
output of the 8 bit shift register 527 to the serial data
input of the 4 bit shift register 547 for the second transmitted
input signal. This process is repeated so that the data
from each of the 8 bit shift registers 526 and 527 is transmitted
alternately. The appropriate group code 537 is provided by
the input group selector 551 for each of the 8 bit shift
r~gisters 526 and 527.
The pulse duration generator 513 receives the clock
signal from the clock generator 514 which is enabled by the
encode state of the encode/decode signal 507. The clock
signal output of the pulse duration generator 513 is routed
to selector 543, and gated by the selector 543 to the clock
signal 539 in response to the encode state on the encode/decode
signal 507. The clock signal 539 serially clocks the bits
from the shift registers 546, 547, 526 and 527 to the selector
515. The timing circuit 520 enables the selector 515 to
gate the first 26 status bits from the 12 bit shift register
546 to the pulse duration generator 513. The next 5 bits
are gated by the selector 515 from the BCH code generator
518 to the pulse duration generator 513. Next, the parity
bit is gated by the selector 515 from the parity code generator
517 to the pulse duration generator 513. The selector 516
gates the outpu~ of the selector 515 to the parity code
generator 517 and to the BCH code generator 518 in response
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to the encode state of the encode/decode signal 507. The
output of the pulse duration generator 513 is a clock pulse
train in which the interval between pulses is determined by
the logic 0 or logic 1 state of the data. If the data ~it
is a logic 1, the interval will be twice as long as the
interval for a logic 0. The synchronization signal which
precedes and follows a data word is four times as long as a
logic 0 bit. The output of the pulse duration generator 513
is applied to the divider 512 which divides the pulse train
output by two and applies the resultant signai to the FSK
transmitter 511. The FSK transmitter 511 provides an FSK
signal 504 composed of two alternating tones, 900 hertz and
1500 hertz, in response to the output signal from the divider
512. The FSK signal 504 is applied to the radio or wire
line unit 580 and transmitted to the central control station.
Next, the timing circuit 520 provides another frame
synchronization signal to initiate the transmitting of the
next status signal. The timing circuit 520 sen~s up to 20
repetitive transmissior.s of the status signals which alternately
provide the status of the two groups of eight input signals.
By optional programming, the timing circuit 520 can select a
variety of repetitive transmission sequences.
In the decode mode the status and control station 500
receives command signals from the central control station by
means of the radio or wire line ~nit 580. The radio or wire
line unit 580 routes the received command signals t~ the FSK
receiver 510 which converts the FSK coded signal into a
digital received data signal 552. The FSK receiver 510
incorporates the principles and concepts of related Canadian
Patent No. 1,067,589, "A Tracking Oscillator and ~se of the
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CM-77884
Same in a Frequency to Voltage Converter." The FSK receiver
510 also provides a data shift signal 553 which is gated by
selector 543 to the clock signal 539 in respon~e to the
decode state on the encode/decode signal 507. The received
data signal 552 is applied to the synchronization and pulse
duration detector 540 which checks for the presence of the
synchronization signal and for proper timing of the logic 0
and logic 1 states of the received data signal 552. The
detection of a synchronization signal by the synchronization
and pulse duration detector 540 provides a reset signal 535
to the selector 541, which gates the reset signal 535 to the
load signal 536 in response to the decode state on the
encode/decode signal 507. The load signal 536 causes the
station address to be loaded from the address unit 545 into
the 12 bit shift register 546. If the synchronization and
pulse duration detector 540 senses the absence of a synchroni~
zation signal or invalid pulse duration timing, a signal is
provided to the valid data detector 542 to indicate invalid
data.
The received data signal 552 is gated by the selector
516 to the parity code generator 517, the BCH code generator
518 and the data comparator 544 in response to the decode
state on the encode/decode signal 507. The data comparator
544 compares the address portion of the received data signal
to the address data from the 12 bit shift register and
produces an output signal 554 if the addresses are not
identical. The BCH code generator 518 generates a BCH code
for the received data signal and compares the generated BCH
code to the received BCH code and provides an output to the
valid data detector 542 if the codes are not identical. The
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parity code generator 517 generates a parity signal for the
received data signal and compares the generated parity
signal to the parity signal of the received data signal and
provides an output to the valid data detector 542 if the
parity signals do not agree. The valid data detector 542
receives the output signals indicating invalid data from the
parity code generator 517, the BCH code generator 518 and
the data comparator 544 and an enable signal from the timing
circuit 520, and provides a valid data signal 555 if the
received data signal is valid.
The selector 528 gates the received data signal 552 to
the 8 bit shift register 526 in response to the decode state
on the encode/decode signal 507. The received data signal
552 is serially shifted through the 8 bit shift register 526
to the RB24 signal 557. When all 32 bits of the command
signal have been received, the 8 bit shift register 526 will
contain the command signal control bits, RB25 (556) and
RB24 (557) . The command signal control bits are used to
provide the execute mode, the interrogate mode, the select
mode, and the acknowledge mode. The bits RB25 (556) and
RB24 (557) are applied to the control 505 for decoding and
appropriate response.
The received data signal is further serially shifted
from RB24 (557~ into the 8 bit shift register 562 and the 4
bit shift register 564 in response to the data shift signal
553. When all 32 bits of the command signal have been
received, the 8 bit shift register 562 contains the command
word and the 4 bit shift register 564 contains a command
group code. In response to a valid data signal 555 and the
execute mode as coded by RB25 (556) and RB24 (557), the output
control 566 provides a load signal to the 8 bit latch 561
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CM-77884
and the 4 bit latch 563 which receive the data from the 8
bit register 562 and 4 bit register 564, respectively, and
then enables the timer 567.
The timer 567 provides an output signal to activate the
relay drivers 570 and the enable buffers 571. The relay
drivers gate the data from the 8 bit latch 561 to the relay
units 576 and 577. The enable buffers 571 gate the data
from the 4 bit latch 563 to the relay units 576 and 577.
The relay units 576 and 577 are enabled by the enable signals
from the enable buffers 571 to provide the output signals in
accordance with the data signals from the relay drivers 570.
The received command signal is specifically directed to
activate only one of the relay units 576 or 577 as determined
by the coding of the enable signals from the enable buffers
571. A subsequent command signal must be transmitted to
enable the other of the relay units 576 or 577. The relay
units 576 and 577 can provide either momentary or magnetically
latched output signals~
The change-of-command detector 565 receives the data
from the 8 bit latch 561 and the 4 bit latch 563 and con-
tinuously monitors the latches for a change in the state of
the data stored therein. If a change in the state of the
data in these latches occurs during the output signal from
the timer 567, the change-of-command detector 565 provides
an output signal to reset the timer 567 and the output
contro} 566 to prevent the changed data from being applied
to the relay units 576 and 577. Any disturbance or noise
which changes the state of the data in the 8 bit latch or
the 4 bit latch during the output signal from the timer will
be prevented from being applied to the output signals by the
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CM-77884
change-of-command detector 565. This procedure insures that
the system controlled by the output signals does not affect
the applied output signals due to a change of any command
storage elements in the status and control station during
the time period (approximately one second) while the output
signals are being applied.
The status and control station 500 can be configured to
provide a check-forward mode of operation. In this mode of
operation, the receipt of two valid command signals which
are identical is required before the timer 567 is enabled by
the output control 566. The first valid received signal is
stored in the 8 bit register 526, the 8 bit register 562 and
the 4 bit register 564. The output control 566 loads the 8
bit latch 561 and the 4 bit latch 563 from the 8 bit register
562 and the 4 bit register 564, but does not enable the
timer 567.
The next valid received signal is compared by the data
comparator 544 to the stored signal of which the command
portion is the output signals of the relay drivers 570 which
have been momentarily activated and stored, as described
hereinafter. First, the relay drivers 570 are momentarily
activated by output control in response to the load signal
536, which in turn momentarily activates the enabled relay
unit 576 or 577. Due to the slow response time of the
relays, the momentary activation is not long enough to
change the state of the relay output signals. The output
signals of the momentarily activated relay drivers 57~,
which connect to the relay coils of the relay units 576 and
577, are parallel loaded into the 8 bit register 57~ in
response to the load signal 536. The data from the 8 bit
shift register 57~ is gated by the data selector 575 to the
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CM-77884
input/output data signal 558 in response to the output
control 566 and is ready for serial transfer together with
generated bits 24 and 25 (573) for the check-forward
configuration to the 4 bit shift register 547. The command
group code from the 4 bit latch 563 is gated by the output
group selector 560 to the group code signals 537 by the
output control 566. The command group code is loaded into
the 4 bit shift register 547 along with a logic 0 from the
check-back signal 538 in response to the load signal 536.
The station address from the address unit 545 and VDD are
loaded into the 12 bit shift register 546 from the address
unit 545 in response to the load signal 536. The data
comparator 544 then serially compares the contents of the 12
bit shift register 546, the 4 bit shift register 547, the 8
bit register 574 and the generated bits 24 and 25 (573) to the
next received data signal. If the compared data words are
identical, the data comparator 544 provides a compare signal
554 to the output control 566, which then activates the
timer 567 to enable the selected relay unit 576 or 577.
If the received data signal is valid but is not identical
to the stored signal, the received data signal, having been
serially shifted into the 8 bit register 562 and 4 bit
register 564 in response to the clock signal 539, is then
loaded by the output control 566 into the 8 bit latch 561
and 4 bit latch 563 from the 8 bit register 562 and 4 bit
register 564 r respectively. Subsequent comparisons are
performed with the new valid received data signal stored in
the latches and succeeding received data signals in a similar
manner to that described by the foregoing. The check-
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CM-77884
forward mode of operation not only provides additional
command signal security, but also performs a check on the
control circuitry of the status and control station 500.
The acknowledge mode of operation is detected by the
control 505 upon receipt of a command signal which provides
the acknowledge code on signals RB25(5S6) and RB24(557). In
response to the receipt of an acknowledge command signal,
the control 505 terminates the sending of successive status
signals by preventing further output enable signals 508 to
the timing circuit 520 which controls signal transmission.
The control 505 will send up to eight groups of twenty
status signals to the central control station, unless an
acknowledge command signal is received between transmission
of groups of status signals. The use of the acknowledge
command signal eliminates unnecessary congestion on the
communication channel.
The interrogate mode of operation is directed by the
control 505 upon receipt of a command signal which provides
the interrogate code on signals RB25(556) and RB24(557).
The interrogate mode initiates transmission of the status
signals as previously described. Normally, the status
signals are transmitted by the control 505 in response to
the input change-of-state signal 532. Depressing the test
switch 506 will also enable the control 505 to transmit the
input signals. For the test mode and the interrogate mode,
the output COS bit 533 of the status signal will be a logic
0. The control 505 transmits up to eight groups of twenty
status signals in response to the test switch 506 or the
interrogation command signal.
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CM-77884
The select mode of operation is initiated by receipt of
a select command signal which provides the select command
code on RB25(556) and RB24(557). In the select mode, the
control 505 provides an output enable signal 508 to the
timing circuit 520 for transmission of a single group of up
to 20 status signal. The command data from the select
command signal, which was loaded into the 8 bit latch 561
and 4 bit latch 563, is now routed back to the shift registers
547 and 546 as described for the check-forward procedure.
The 4 bit shift register 547 is loaded with the output group
code from the 4 bit latch 563 and a logic 1 from the check-
back signal 538, and the 12 bit shift register 546 is loaded
with the station address from the address unit 545 and a
logic 1 from VDD. The data in these registers is then
transmitted to the central control station as described for
the encode mode of operation.
The central control station then verifies the check-
back signal and issues an execute command signal if the
check-back signal is identical to the select command signal.
In the status and control station 500, the execute command
signal is either received and applied or compared with the
stored select command signal as described in the check-
forward mode of operation. If the compared signals are
identical, the timer 567 enables the relay unit 576 or 577 in
accordance with the command data.
D. Control Station
The control station is used for controlling the operation
of external devices. Command signals are received from the
central control station and enable tne control station to
send output signals to the external devices. In the present
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CM-77884
illustrative system, the control station sends up to 8
output signals to the associated external devices. The
control station is similar to the basic control portion of
the status and control station and can be adapted to provide
similar modes of operation.
The control station includes a radio or wire line unit,
a decoder, an output unit, and a power supply. Generally,
coded command signals are received by the radio or wire line
unit from the central control station and converted from FSK
modulated signals into digital words and loaded into a
register by the decoder unit. The output unit sends out the
output signals in accordance with the command word in the
register. The radio or wire line unit need only have a
receiver, since transmitting is not required.
The detailed operation of the control station 600 can be
understood by referring to Fig. 6. A command signal received
by the radio or wire line unit 601 is applied to the FSK
receiver 602. The FSK receiver 602 converts the command
signal into a digital data signal 620 and provides a data
shift signal 621 for each bit of the data signal 620. The
received data control 603 receives the data shift signal 621
and provides enable signals to the valid data detector 605
for controlling the validity check on the data signal 620.
The received data control 603 also insures that the data
signal 620 consists of exactly 32 bits.
The synchronization and pulse duration detector 604 `
checks to insure that a synchronization pulse precedes and
ollows the data signal 620 and checks the pulse width dura-
tion of the bits of the data signal 620. The pulse duration
of logic 1 bits must be twice as long as the pulse duration
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CM-77884
of logic 0 bits, and the pulse duration of the synchronization
signal must be four times as long as the pulse duration of a
logic 0 bit. The synchronization and pulse duration detector
604 provides a reset signal to the received data control 603
and the 12 bit shift register 611 upon detecting a synchronization
signal and provides an output signal to the valid data
detector 605 if invalid pulse durations are detected.
The proper BCH code and parity bit are generated by the
BCH code and parity generator 610 from the data signal 620,
and then are compared to the respective BCH code portion and
parity bit of the data signal 620. An output signal is
provided to the valid data detector 605 if the generated BCH
code is not identical to the BCH code of the data signal 620
and if the generated parity bit is not identical to the
parity bit of the data signal 620.
The 12 bit shift register 611 is parallel loaded with
12 bits consisting of the station address from the address
unit 612 and a logic 1 from VDD in response to the reset
signal from the synchronization and pulse duration detector
604. The data signal 620 is shifted into the 12 bit register
611 in response to the data shift pulses 621, while the
address data stored in the 12 bit reyister 611 is shifted
out to the address comparator 613, The address comparator
613 receives the data signal 620 and the data shifted out
from the 12 bit register 611 and provides an output signal
to the valid data detector 605 if the data signal 620 is not
identical to the shifted-out data.
The valid data detector 605 provides an output signal
to the timer 606 if the data signal 620 passes all of the
foregoing mentioned checks. The timer 606 provides an
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CM-77884
output signal to enable the relay driver 607 in response to
an output signal from the valid data detector 605. The
timer 606 also provides an output signal to the FSK receiver
602 to prevent reception of further command signals while
the relay driver 607 is enabled. The relay driver 607
activates the relay outputs 608 in accordance with the
command data 622 from the 12 bit register 611. The execute
bit 623 from the 12 bit register 611 must also be a logic 1
to enable the relay drivers 607. Upon activation, the relay
output unit 608 provides up to eight output signals. The
relays in the relay output unit 608 can be of the momentary
output type or the magnetic latching type.
The power supply 614 provides the supply voltage for
the relay driver 607 and the voltage regulator 615. The
voltage regulator 615 provides a regulated supply of voltage
VB 624 for the radio or wire line unit 601 and VDD 625 for
the logic circuitry in the control station 600.
E. Status Station
The status station is used to continuously monitor the
operation of remote devices and transmit the monitored ~,
status, encoded into status signals, to the central control
station by means of a radio or wire line unit. The coded
status signals are received and automatically displayed by
the central control station. Those status signals which
have changed state are indicated as alarms in the display.
In the present illustrative system, the status station
continuously monitors up to 16 input signals from the associated
external devices. The status station is similar to the
basic status monitoring portion of the status and control
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CM-77884
station and can be adapted to provide similar modes of
operation.
The status station includes a radio or wire line unit,
a decoder unit, an input unit and a power supply. Generally,
the status of the input signals from the associated external
devices are monitored by the inpu~ unit, which provides an
output signal to the encoder unit if any monitored input
signal changes state. The encoder unit loads the input
signals into a register, converts the input data word together
with a generated validity code into an FSK modulated status
signal, and transmits the coded status signal to the central
control station by means of the radio or wire line unit.
Since the status station only transmits signals, the radio
or wire line unit does not require a receiver. However! a
receiver in the radio or wire line unit can be used to
monitor the communication channel for activity, so that the
status station can be operated to transmit status signals
only when the communication channel is not busy.
The detailed operation of the status station 700 can be
understood by referring to the block diagram shown in Fig.
7. Up to sixteen input signals are continuously monitored
for a change of state by the input monitor and protection
units 720 and 721. The change of state of the input signals
is detected by a sensing circuit which incorporates the
principles and concepts of the related Canadian Patent No.
1,070,410,"Sensing Circuit". If a change of state is detected
by the sensing circuit, the input monitor and protectlon
units 720 and 721 provide an input change-of-state signal
731 to the control 702.
In response to the input change-of-state signal 731,
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CM-77884
the control 702 provides an encode enable signal 733 to the
clock source 707, an output enable signal 734 to the timing
circuit 708 and a push~to-talk signal 735 to the radio or
wire line unit 701. The radio or wire line unit 701 provides
a channel monitor signal 736 to the control 702 to indicate
the presence of activity on the transmission channel. If
activity is present on the transmission channel as indicated
by the channel monitor signal 736, the control 702 will not
provide the push-to-talk signal 735 until the activity has
ceased.
In response to the encode enable signal 733, the clock
source 707 provides a clock signal to the pulse duration
generator 706. The timing circuit 708 initiates transmission
of the status signal in response to the output enable signal
734. A frame synchronization signal 736 is provided by the
timing circuit 708 to the pulse duration generator 706 and
the shift registers 722, 723, 726 and 727.
The frame synchronization signal 736 enables the shift
registers to parallel load respective data into the shift
registers. The 12 bit shift register 727 is parallel loaded
with 12 bits composed of a station address of 11 bits from
the address unit 728 and a logic 1 bit from VDD. The 4 bit
shift register 726 is parallel loaded with 3 bits from the
group code signals 737 and a logic 0 bit from ground. The 8
bit shift registers 722 and 723 are parallel loaded with the
8 sensed states of their respective input signals.
The timing circuit 708 enables the selector 710 to gate
the first 26 bits of the status signal from the 12 bit shift
register 727 to the pulse duration generator 706. The pulse
duration generator 706 provides clock pulses 740, which have
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CM-77884
a pulse width duration determined by the logic state of the
data from the selector 710r to the divider 705 and the shift
registers 722, 723, 726 and 727. The clock pulses 740
serially shift the data from the shift registers to the
selector 710.
The selector 724 alternately routes the 8 bit shift
registers 722 and 723 to the 4 bit shift register 726 for
succeeding transmissions of input signals. The input group
selector 725 provides the group code signals 737 to enable
the selector 724 to select the appropriate 8 bit shift
register 722 or 723. During the shifting of the data, the
selector 716 gates the power fail indication signal 730
followed by the output change-of-state signal bit 732 to the
8 bit shift registers 722 and 723 in response to an enable
signal from the timing circuit 708. The first 26 bits of
the input signal are shifted from the 8 bit shift registers
722 and 723 (alternately for successive transmissions) to
the 4 bit shift register 726, from the 4 bit shift register
726 to the 12 bit shift register 727 and from the 12 bit
shift register 727 to the selector 710.
The data signal 738 from the selector 710 is applied
to the parity code generator 711 and to the BCH code gen-
erator 712. The BCH code generator 712 generates a 5 bit
BCH code for the first 26 bits of the data signal 738. The
parity code generator 711 generates a parity bit for the first
31 bits of the data signal 738. The timing circuit 708 en-
ables the selector 710 to gate the BCH code to the data signal
738 following the first 26 bits from the 12 bit shift register
727. The timing circuit 708 enables the selector 710 to gate
the parity bit from the parity code generator 711 to the data
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signal 738 following the BCH code from the BCH code gen-
erator 712.
The clock pulses 740 from the pulse duration generator
706 are divided by two by the divider 705 to provide a pulse
duration signal to the FSK transmitter 704. The FSK trans-
mitter 704 provides a tone output to the radio or wireline
unit 701 which alternates between two tones, 900 hertz and
1500 hertz, in response to changes in the logic state of the
pulse duration output signal from the divider 705.
The radio or wireline 701 transmits the FSK coded status
signal to the central control station. The timing circuit 708
provides a frame synchronization signal 736 preceding and !
following each of the input signal transmissions. The
timing circuit 708 provides for up to twenty transmissions
of the input signals. The control 702 further provides for up
to eight repetitions of the group of twenty transmissions of
input signals in xesponse to an input change-of-state signal
731. Depressing the test switch 703 will also enable the
control 702 to transmit the input signals as described
hereinabove.
The power supply 714 provides a supply voltage VB to
the voltage regulator 713, the DC to DC power supply 715,
and the radio or wireline unit 701. The voltage regulator
713 provides the VDD supply to all the logic circuits of the
status station 700. The DC to DC power supply 715 provides
an isolated voltage necessary for the input monitor and
protection units 720 and 721. The power supply 714 pro-
vides a power fail indication signal 730 which is applied
to selector 716.
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Hereinabove, various features of the invention have
been described in detail in conjunction with a supervisory
control system. Certain of these features are broader in
scope so that they are not limited to a supervisory control
system ~or potential application, and that they can be more
broadly applied to other types of systems. Stated briefly
by way of illustrations, these features include the busing
system for storing and reading out data from a memory, the
rolling display system, the check-forward system and the
change-of-command sensing system described in detail hereinabove~.
Referring to the busing scheme for storing and reading
out data from a memory, according to the prior art, separate
buses or leads are provided for data and memory address
incorporation. In contrast, as described in detail hereinabove
with reference to Fig. 4, in accordance with the present
invention the separate leads or buses for the memory address
are entirely eliminated, and instead clock and enable signals
are used, via clock and enable signal paths or leads, to
address the memory. The number of leads or buses eliminated
in this manner increase very significantly as the size of
the memory increases. This reduction in the number of leads
or buses required for data and memory address incorporation
has a broader applicability that can be advantageously
utilized in any applications.
As described hereinabove, the rolling display system
entails receiving certain messages, such as alarm messages,
from the stations in the system, and the messages are displayed
in a limited number of display elements. Once the display
elements have become filled, then the messages are stored in
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the overflow memory in the computer for subsequent display,
and the display overflcw indicator is flashed. The messages
in the overflow memory can be viewed by sequentially depressing
the roll key provided for in the central control station
(see Fig. 2). Depressing the roll key causes the status
signal in the leftmost display unit to be deleted and stored
back into the overflow memory. The status signals in the
display to the right of the vacated display unit are each
shifted to the left one unit. The highest priority message
in the overflow memory is displayed in the rightmost unit in
the rolling display. Thus the messages in the overflow
memory can be continuously accessed and displayed without
loss of any vital information. Clearly the aforementioned
rolling display system need not be limited to a supervisory
control system, but can be applied more broadly to any type
of systems wherein such a rolling display system can be
advantageously utilized.
Still another feature of the present invention of
general applicability is the check-forward method for processing
coded signals as described in detail hereinabove with reference
to Figures 5a, 5b and 5c in combination. Restated briefly
with reference to Figures 5a, 5b and 5c in combination, in
the check-forward mode, the status and control unit 500
compares a valid second command signal to the stored command
signal (latches 561 and 563) which is momentarily applied to
the output means (relay units 576 and 577) and if the command
signal is identical to the applied stored command signal,
the output means is permanently enabled. By sensing the
stored command signal at the output means, the circuitry at
the status and control station 500 is checked for proper
operation at the output driving means (relay drivers 570).
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CM-77~84
Thus, the check-f~rward mode of operation not only provides
additional command signal reliability, but also performs a
comprehensive check on the operation of the control circuitry.
The check-forward method provides a means of checking remote
circuitry without the use of a check-back method or a large
number of signal transmissions. Many signal processing
systems could advantageously utilize such a check-forward
method.
Still another feature of the present invention of
broader applicability is the change-of-command sensing
described hereinabove in detail with reference to Fig. 5c.
Restated generally, the change-of-command sensing entails
the following. An incoming signal from a central control
station is received by the status and control station into
the registers of the output unit (Fig. 5c) and is sent out
to the relay units 576 and 577 via the latches, relay drivers
and the enable buffers as illustrated. The output unit is
so designed that the selected relay unit is enabled a given
duration of time, for example, one second, whereby the
output signals from the relay unit are utilized to activate
an external device. Inasmuch as the circuitry is designed
to operate in a highly noisy environment, for that one
second duration, the relay unit prcviding the output signal
is rendered immune or impervious to internal changes taking
place in the registers, that is, the changes caused by
noise signals. More specifically referring to Fig. 5c
this is attained as follows. In the status and control unit
500, the command signal is applied to the output means by
the timer 567 while the internal latches 561 and 563 are
monitored by the change-of-command detector 565 for any
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change of state during activation of the timer 567. If a
change of state is detected, the timer 567 is reset and the
command signal is cancelled. In controlling systems in a
noisy electrical environment, activation-of the external
system can result in a significant amount of noise which can
easily change the state of storage elements. The monitoring
of internal storage elements for a predetermined time interval
while the output means is being activated and maintained is
a method which has wide application in electrical systems
which are susceptible to a noisy electrical environment. A
subsequent command signal can be effectively applied to the
output means when the noise in the environment has subsided.
While hereinabove, an invention for a supervisory
control system and various subfeatures which have broader
scope of applicability beyond the supervisory control system
have been described, various other modifications and changes
may be made by those skilled in the art without departing
from the spirit and scope of the present invention.
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