Note: Descriptions are shown in the official language in which they were submitted.
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Introduction and General Discussion
The present invention relates to a transponder for
performing a plurality of measuring functions and more
particularly to a transponder whose functions are
controlled by a microprocessor.
One of the problems met by today's ever increasing
demand for electric power is the tremedous capacity
necessary to handle peak loads at particular hours of the
day. For example, if power consumption were to remain
constant during the entire day, the present electric power
generating faoilities would be adequate for many years
into the future.
It has therefore become important to be able to
measure the power consumption of individual dwellings on
an hourly basis with each hour being equated to a real
time hour in the day (time-of-day consumption). Once it
is possible to measure power consumption on an hourly
basis, it is possible to reward consumers for maintaining
a relatively low power consumption during peak load hours
and to penalize consumers who use a large amount of power
~ 20 during peak load hours. The present invention, in addition
to being able to measure accumulated consumption of the
electric power utillty, the water utility and the gas
utility, can measure and store the consumption of electric ~
power on an hourly basis. ~ -
The next step in moderating power consumption is for
the utility to be able to shut off non-essential ~oads in
the consumer's home when the power consumption for a given
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time period approaches a predetermined level.
A particular embodiment of the present invention is
capable of performing this load shedding function upon
receipt of the correct coded message from a central
computer.
Embodiments of the transponder are also capable of
continuously scanning a plurality of alarm inputs and
transmitting their status to a central location. Alarms
such as fire and illegal entry alarms are contemplated.
Prior art systems have contemplated the storage of
accumulated consumption data, peak demand data, and load
control on two-way power lines, single-way transmitting
systems and even telephone lines. ~owever, none of the
prior art systems have envisaged a combined system of
keeping track o~ accumulated consumption data, time-of-day ~
data and alarm data and performing load control over a ~`
; two-way communication link, for example, a telephone
system.
It is imperative to such a system that transmission
security be high. This high security ensures that only
the correct transponder is activated and valid data
transmitted to the central computer. No prior art systems
have provided this high security.
High baud rates necessary to accurately transmit
time-of-day data and load control verification are not
possible using power lines as the communication link.
Such baud rates are possible using two-way radio links,
; however, the cost of the necessarily large number of radio
transmitters is prohibitive. Such high baud rates can be
achieved using a telephone system as the communication
link.
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The system of the present invention combines all of
the above features into one system requiring transponders
of low power. This combined result provides an
economically feasible system.
In this disclosure the term "time-of-day consumption"
means that power units are monitored and stores on a
predetermined time basis over an extended time period.
For example, an hourly time-of-day memory stored total
accumulated power units consumed in a one hour time period
over an extended time, for example, 30 days.
Peak demand consumption means the maximum recorded
consumption at a particular time within a predetermined
time period.
A peak demand reading can be extracted from accumulated
time-of-day information.
The heart of the transponder is a custom microprocessor
which, under the influence of a clock pulse frequency,
cycles through a program. Instruction word sets are sent
from a central computer to the transponder. These
instruction word sets activate subroutines of the program
contained within the microprocessor so that specific
information is taken out of storage in the transponder and
;~ transmitted to the cental computer. When this program is
functioning without receipt of an instruction word set,
the transponder continues to operate in a "housekeeping" `
mode. In this mode, the transponder accumulates and
stores the current level of consump~ion of utilities
attached thereto. In addition, it enters the hourly
consumption rate o~ the electric power utility into a ~--
time-of-day memory unit. The transponder is also capable
of scanning the alarm inputs~ If an alarm exhibits a
valid alarm signal, this information is stored and
transmitted to the central computer the next time that the
transponder is scanned by the central computer. A11
transponders in the system contemplated by an embodiment
of the present invention are scanned approximately every
thirty seconds.
In order to ensure a low probability of error in the
receipt of instruction data sets and the transmission of
data word sets from the transponder to the central
computer a unique decoding and coding system has been
developed.
An instruction word set consists of five words each
having a start bit, ~ data bits, a parity bit and a stop
bit. The first word in the set is an alert word and
consists of all logic level "l's". The second word is an
identification code word. Each transponder, at the time
of its installation, has hard wired therein an identifi~
cation code. The microprocessor, upon receipt of an
instruction word set compares the second word with the
code hard wired therein and accepts the instruction word
set if and only if the identification words coincide. In
this way, a plurality of transponders can be connected to
the same telephone line and be distinguishable from one
another by the central computer. The third word in the
instruction word set is an instruction/control word which
modifies the program in the microprocessor to perform, in
addition to its "housekeeping" functions, some special
task. The fourth word in the instruction word set is a
data word. If, for example, the instruction word received
by the transponder requests the transponder to load data
into a specific time register, the data word would be the
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information loaded therein. The last word in the instruc-
tion word set is a block parity word.
The microprocessor checks each word for parity. In
addition, each word is checked to ensure that the entire
word is received in the correct time frame. Finally, the
entire instruction word set is checked for block parity
and framing.
The transponder forms a data word set for transmission
to the central computer. The first word is an alert word.
The second word is the identification code word of the
transponder. The third word is a customer identification
code word. Upon initialization of the transponder, the
central computer sends to the transponder a customer
identification code word. Unless this customer identifi-
cation code word is specifically removed from the
transponder by the central computer, the transponder
thereafter exhibits the customer identification code word ;
~; each time it is transmitting data to the central
computer. The customer identification code word is
necessary in the event that the telephone company
interchanges the telephone line in a particular cable.
The fourth to the (4 + N - l)th word represents data
stored in the transponder requested by the central
computer. The (4 + N)th word is a block parity word and
the (4 + N + l)th word is an end of transmission code
~ word.
;~ Using these unique instruction word sets and data word
sets, information can be exchanged by the central computer
and a transponder with a very low probability of error.
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Summary of the Invention
In accordance with an aspect of the invention there is
provided a transponder unit for use with a non-dedicated
communication link comprising: receiver means for receiving
external instruction signals from said communication link;
transmitter means for transmitting data via said co~muni-
cation link; a central processing unit (CPU) connected to
said receiver means and said transmitter means; a clock
generator means for controlling said CPU; a read only memory
(ROM) connected to said CPU, said ROM containing a program
for controlling said CPU; a real time clock connected to
said CPU for determining sequential pre- determined time
periods; three input terminals connected to said CPU for
receiving data to be stored in a random access memory (RAM),
one of said three input terminals having pulses impressed ::
thereon, the number of said pulses being representative of a
utility consumptionj said one of said three input terminals
; also being connected, via said CPV, to a time-of-day memory,
said time-of-day memory being comprised oE a plurality of
discreetly addressable registers, wherein said CPU
~20 correlates each addressable register sequentially with a
consecutive one of said predetermined time periods, so that
each register sequentially contains a count which is
representative of consumption during its associated time
period or any fraction thereof; wherein, upon receipt of one
of said external instruction signals, said CPU activates
said transmitter means to transmit data, said data beingj in
part, the contents of each register in said time-of-day
; memory transmitted in sequence; said unit further comprising
identification code word means connected to said CPU for
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setting an identification code word into said RAM, wherein
said CPU provides comparator means which compares another of
said external instruction signals with said identification
code word, a positive comparison validating that the correct
transponder unit has been selectecl~
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Introduction to the Drawings
The present invention will be described hereinbelow
with the aid of the accompanying drawings in which:
Figures 1 and 2 form a schematic diagram of a
particular transponder according to the present invention;
Figure 3 is a block diagram of a particular large
scale integrated circuit (LSI) used in the schematic
diagram of Figures 1 and 2 as a "communication" chip;
Figure 4 is a block diagram of a particular LSI chip
used in the schematic diagram of Figures 1 and 2 as a main
logic chip; and
Figure 5 is a detailed block diagram of the logic chip
shown in Figure 1.
Detailed Description of Preferred Embodment
Figures 1 and 2 form a single schematic diagram. It
should be noted that for example, line 1-20 in Figure 1 is
connected to line 2-20 in Figure 2.
Referring now in detail to the embodiment of the
; invention shown in Figures 1 and 2, it can be seen that
the transponder is powered by a voltage supply consisting
of a diode bridge 50 coupled to a low voltage AC source
51. The output is filtered and controlled and provides a
Vcc at terminal`52. This voltage Vcc feeds all of the
active elements of the transponder. A supply battery is
connected to terminals 53. The battery is always
connected to the circuit and is automatically activated
, when the regular power supply fails. The battery, being
connected in this way, is alwaya subjected to a trickle
charge so that it is immediately ready to take over in the
~ 30 event of a power supply failure.
,~
As was mentioned above, the transponder performs ;~
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several functions. Input terminals 54, 55 and 56 are
connected to electricity, gas and water meters,
respectively. The transponder maintains an accumulated
record of the consumption of these three utilities. In
addition, the consumption of the electricity utility is
recorded on an hourly basis in the time-of-day memory
stores 57, 58, 59, 60, 61, 62, 63 and 64.
Instructions are sent to and data is received from the
transponder via telephone lines 65 and 66.
One type of instruction sent to the transponder might
be a load shed instruction. In the event that an
electricity consumer was reaching some predetermined quota
during a peak demand time, a coded signal could be sent
via lines 65 and 66 which would activate any one or all of
load shedding relays 67, 68, 69, 70 and 71. These relays
~ would be connected to luxury items which consume large
- quantities of electric power, for example, an air
conditioner or an electric clothes dryer.
Each relay is fitted with a set of supervisory
20 contacts 72 which are connected to terminals 73, 7~, 75,~
: ~ ~
76 and 77, respectively. Four of the five terminals 73 to
77 may be connected to status input terminals 78, 79, 80
and 81. The central computer scans each transponder
repeatedly every short while and one piece of information
that the computer requests durlng such a scan is the
condition of the status terminals 78-81. Since the relays
are of a latching type the terminals 73 to 77 are either
at ground potential or at Vcc and these conditions are
,~ .,
relayed, during a scan, to the central computer via their
interconnection to status terminals 78 to 81. As a
result, when the central computer sends a command to load
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shed, the load shed is either correctly or incorrectly
performed and a positive indication is returned to the
central computer.
Terminals 82, 83, 84 and 85 are connected to alarms
for example, fire alarms and/or intrusion alarms. The
condition of the terminals 82-85 switch their logic level
voltage if an associated alarm is activated. This change
in logic level voltage is relayed to the central computer
when the computer scans the transponder. The voltage
appearing on an alarm terminal when an associated alarm is
activated can return to its deactivated level after a
short predetermined period of time. ~owever/ the internal
logic of the transponder will continue to transmit an
alarm condition when scanned until the transponder is
reset by a positive command from the central computer.
This is important when, for example, an intrusion alarm is
connected since a burglar may only activate the alarm for
;~ a short period of time.
The commands sent to the transponder and the
information sent from the transponder are transmitted as
mark and space frequency bursts on the telephone lines 65
and 66. The frequency of the mark and space signals can
; be, for example, 2225 and 2025 Hz, respectively in the
}`` direction from the central computer to the transponder and
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; 2225 and 1270 Hz for the mark and space frequencies in the
: direction from the transponder to the central computer.
'~.,
;~ The value of the frequencies of the mark and space signals
`~ are not important to the present invention. The circuitry
~:
of the transponcler may be adapted to operate on any
frequencies chosen within reason and the selection of the
frequencies does not form a part of the present invention.
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The telephone lines 65 and 66 have a gas discharge
device 86 connected thereacross. This discharge device
protects the electronic circuitry from large overvoltages
which could, by accident, occur across lines 65 and 66.
Capacitors 87 and 88 remove any direct current voltage
that might appear on the lines. The RC time constant of
capacitors 87 and 88 and resistor 89 limit the duration of
current of a 10KV pulse which may also appear on the
telephone lines 65 and 65. Internal zener protection
further reduces the incoming voltage to an acceptable
level.
The incoming mark and space signals and the outgoing
mark and space signals are processed in a communication
chip 90 which will be described in detail hereinbelow. At
present it is sufficient to say that the communication
chip 90 processes the incoming mark and space signals and
converts them to "high" and "low" logic level voltages for
use in the remainder of the electronic circuitry. This
:,
digital received data is output from line 91. The
communication chip 90 contains all of the actlve elements
used to process the incoming mark and space frequencies.
The vast majority of passive elements needed to perform
this function and others are contained in two passive
chips 93 and 92'. By using these passive chips for the
.
passive elements in the system NPO capacitors and 50-100
ppm resistors can be used. These elements are extremely
temperature stable and allow the use of narrow band
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techniques having very stable characteristics.
The control of various unctions of the transponder is
performed by a microprocessor which forms a portion of
C-MOS chip 92. Chip 92 will be described in detail
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hereinbelow with reference to Figure 4. Chip 92 decodes
incoming instruction signals to ensure that they have been
correctly received by the correct transponding unit. In
addition, the chip formulates and codes data to be sent
back to the central computer. The output from the chip to
be sent back to the central computer is in the form of a
synthesized mark and space signal and is fed to
communication chip 90 via line 93. Chip 92 continuously
stores the accumulated data from the three utility inputs
54, 55 and 56. In addition, the chip enters the `~
appropriate time-of-day data in the correct address of the
time-of-day memory units 57 to 64. The chip also decodes
and sends signals to the load shedding circuitry and
monitors the status points 78 to 81 and the alarm
terminals 82 to 85.
The program in the microprocessor is advanced b~ clock
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pulses generated by crystal controlled unit 94. The clock
is used in two locations in the transponder. One location
to which it is fed is chip 92 via line 95 and via line
96. Passive elements of the crystal oscillator are housed
in passive chip 97. The second location to which the
i ~ ~
~ clock pulse is fed is to chip 90 vla line 98. The load i -
`~ shedding relays 67 to 71~must be driven and the chip 92
~ cannot handle the appropriate power. As a result, chip
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100 is provided which receives signals from chip 92 and
accordingly drives the appropriate relay.
The output section of the communication chip 90 is ;
controlled by a modem enable signal fed to the chip 90 via
line 101 from the chip 92. This signal turns on the
output circuitry o~ the communication ch1p and delays the
initial transmission of data back to the central omputer.
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The system does not necessarily need a telephone line
connecting the transponder to the central computer. A
radio link can also be used. The radio transmitter, when
used, will have a finite "power up" time, i.e. a length of
time between its turn on and its ability to transmit
data. To ensure that all the data is transmitted, the
length of the delay of the modem enable signal is
programmable. When a telephone line is being used, the
delay is short, in the order of 50 ms. When the radio
link is being used, the delay is longer, in the order of
500 ms. The delay is programmable from 50 to 1500 ms.
The modem enable signal can be used to turn on the radio
transmitter and therefore the signal controls power
transistor 102 to selectively ground output terminal 103.
~ As mentioned above, the transponder, according to the
; present invention, is in constant two~way communication -~
with a central computer. The central computer sends a ~-
coded message to the transponder which, in addition to
performing a "housekeeping" program, decodes the message
,. ,
~ ~ 20 and-performs certain specific tasks, sending a reply ~
~,
message back to the central computer. It is important
therefore that the correct message be sent to the correct
transponder and that the transponder perform a certain
.,
specific function only when that correct message is
correctly received and decoded. The present invention has
a specific circuitry;built into it to test the quality of -
the received message to ensure that it has been correctly
sent, received and decoded.
The computer and transponder communicate with one
another using data words. Each data word consists of a
start bit, 8 data bits, a parity bit and a stop bit.
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The computer must send five words in an instruction
word set to the transponder before it will be activated.
The first word is an alert word which consists of all
logical "l's". For the purpose of clarity it should be
noted that a "high" logic level voltage, a mark frequency
burst and a logical "1" are the same and a l'low" logic
level voltage, a space frequency burst and a logical "0"
are the same. The next word sent to the transponder is an
identification code. This code contains 6 active data
bits and 2 inactive data bits. Jumper wires generally
indicated at 104 in Figure 1 are either connected or not
connected to 6 inputs of chip 105 to set the
identiEication code into the chip 92 at the time of
installation of the transponder. Once the identification
code has been set, the transponder will not be activated
unless it receives an identification code word from the
central computer which~has 6 active bits coinciding with
the 6 bit identification code entered into the chip 92 via
the jumper wires 104. Since 6 bits go to make up one
identification code it can be seen that as many as 64
~ transponders can be connected to a single telephone line ~
;~ pair and be individually actlvated by the central ~ -
computer. The jumper wires activate pull up resistors in
chip 105 which enter either a logical "1" or a logical "0"
into chip 92.
The third data word contains the instruction code and
the control bits. This word actually tells the transponder
which one of many functions to perform. The next word is
a data word and contains the data that the transponder
will need to perEorm its instruction. For example, if the
instruction was to load the time clock register, the
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fourth word would be the lnformation, i.e. the time to be
loaded into the time clock register. If no special data
is necessary Eor the transponder to perform a function
then the data word is filled with the baud rate that the
transponder is to return its stored data back to the
central computer. The central computer always sends
information and instructions to the transponder at a baud
rate of 150. The transponder can send information back to
the central computer at a baud rate of 1200, 600, 300 or
150. If, for example, the transponder was set to transmit
at a rate of 1200 baud and the computer did not, after
performing its data check, receive the correct -
information, it could request the transponder to resend
the informltion at a slower baud rate which might ciear up
the problem if the problem was, for example, a bad
telephone line.
The fifth word in the instruction word set is a block
parity word. The C-MOS chip 92 checks each of the five
data words to ensure that they have the correct word
~ 20 parity. Chip 92 also performs a framing check to ensure
: that the entire word is sent in a correct time period.
Finally, a block parity check and a block framing check is
performed. The parity of all five data words is checked
column by column. In this manner, the probability of a
transponder being falsely activated is extremely low.
; The computer, by sending a single instruction word set
consisting of flve data words, can perform all of the
interrogations and resettings necessary to operate the
transponder. The one exception~to this is the loading of
the accumulators. The data word (the fourth word) has
only a 2 digit capacity and the accumulator registers have
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6 digit capacity. Therefore, the fourth word cannot
completely define the entire accumulator register. As a
result, in order to load a single accumulator register,
the entire instruction word set must be transmitted three
times. The first time it is sent, the control bits of the
third word are set to indicate the loading of the first 2
digit positions of the 6 digit register and the data word
(the fourth word) contains the data to be loaded therein.
The second time the instruction word set is sent, the
control portion of the third word is set to lndicate the
loading of the second set of 2 digit positions of the 6
digit accumulator register in question, and so on until
the entire 6 digit register is loaded.
A listing of the instructions that the transponder is
capable of receiving are as follows:
Interrogate all three accumulators
Interrogate status word
Interrogate accumulators and status words
Interrogate time-of-day memory
,....................................................................... .
~ 20 Interrogate time-of-day memory, status word and
;~ accumulator
`~ Reset - Accumulator 1 and retransmit
Reset - Accumulator 2 and retransmit
Reset - Accumulator 3 and retransmit
; Reset - Time-of-day memory and Tx. status word
Reset - Alarm register and Tx. status word -
Load - Accumulator 1 and retransmit
Load - Accumulator 2 and retransmit
;~ Load - Accumulator 3 and retransmit
Load - Time clock register and Tx. status word
Load - Customer identification code and Tx. status word
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Control 1 and Tx. status word
Control 2 and Tx. status word
Control 3 and Tx. status word
Control 4 and Tx. status word
Control S and Tx. status word
Baud rate - set for 150 B.
Baud rate - set for 300 B. I and Tx. status word
Baud rate - set for 600 B.
Baud rate - set for 1200 B.
Tx. control delay - set for 50 ms
Tx. control delay - set for 100 ms
Tx. control delay - set for 200 ms
Tx. control delay - set for 300 ms . : :
; Tx. control delay - set for 400 ms
Tx. control delay - set for 500 ms
Tx. control delay - set for 600 ms
Tx. control delay - set for 700 ms and Tx. status word
: Tx. control delay - set for 800 ms
Tx. control delay - set for 900 ms
Tx. control delay - set for 1000 ms ~:
: Tx. control delay - set for 1100 ms
Tx. control delay - set for 1200 ms
Tx. control delay - set for 1300 ms :~
Tx. control delay - set for 1400 ms
~ : Tx. control delay - set for lS00 ms
: Diagnostic RAM test pattern Tx. results
It should be noted, from the above listing, that all
of the instructions require the transponder to ~ .
retransmit. In other wordst if an accumulator is reset,
: 30 the reset data is retransmitted to the central computer to
: ensure that the transponder has correctly carried out the
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reset. This is an important advantage since it provides a
positive indication of a requested action.
When the second interrogation listed above is
transmitted, four data words are transmitted by the
transponder back to the central computer. The first data
word is the baud rate at which the transponder was set and
the transmit delay time oE the modem enable signal. The
second word contains information concerning the four alarm
inputs 82 to 85 and the four status inputs 78 to 81 shown
in Figure 1. The third word is the time clock information
of the transponder. This information is compared with a
time standard at the central computer and must coincide.
The fourth and last data word sent back to the central
computer is the contents of the time-of-day memory.
The transponder sends a set of words back to the
central computer in a given sequence. This set of words
is known as a data word set. The first word is an alert
;~ word as defined above. The second word is the transponder
identification code word as mentioned above. The third
word is the customer identification code word. When the
transponder is initialized, the central computer allots a
customer identification code to the transponder which is
~; permanently stored thereafter. Each time the transponder
transmits, it must therefore transmit a customer
identification code word. ;~-
The fourth to the (4 + N - l)th words are data words
and represent the data stored in the transponder which has~;
been requested by the central computer. The data group,
i.e. word four to (4 + N - 1) could be very long, for -
example, when the central computer requested a read out of
the time-of-day memory. The (4 + N)th word is a block
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parity word. As a resultl it can be seen that all of the
data, no matter how long, is checked for both word and
block parity. The (4 + N ~ l)th word is an end of
transmission code word.
Communication chip 90 will now be discussed in detail
with respect to Figure 3. The tip and ring telephone
lines 65 and 66 are connected to the input of
communieation chip 90. The chip can be broken down into a
receiver section and a transmitter section. The receiver
section contains a high impedance operational amplifier
106. Its function is to isolate the telephone line from
the remainder of the receiver section of the chip so that
the receiver section of the chip appears electronically
"invisible" to the telephone lines. The output of the
amplifier 106 is fed to a narrow band active filter 107
which has a sufficient band width to handle both the mark
and space frequencies of the incoming signal. The output
of filter 107 is fed to a carrier detect circuit 108. If
this eireuit detects a mark frequency for a predetermined
minimum length of time it is activated and passes the mark
frequency along with subsequent space and mark frequeney
bursts on to~a mark and space detecting circuit 109. The
sine waves making~up the mark and space frequency bursts
entering the detecting circuit I09 are squared via, for
example, a saturated amplifier, and compared with two
clock frequencies which are precisely set at ~he desired
input frequencies of the mark and space signals. Tbis
;~ basic clock frequency is fed to the detecting circuit 109
from chip 92 in Figure 1 via line 98. The two internal
clock frequencies are compared with the squared mark and
spaee signals on a time and measurement basis. If the
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clock frequency representing the mark frequency is
correctly compared with the incoming squared mark
frequency, the detector 109 produces, for the length of
time of the squared mark frequency, a "high" logic level
voltage output on line 110. The clock frequency which is
; precisely equal to the space frequency is compared with
the incoming squared space frequency. If these two
frequencies coincide, detector 109 produces, for the time
duration of the squared space frequency, a "low" logic
level voltage output. The entire detector circuit 109 is
; in a quiescent state under normal conditions and is only
activated upon receipt of a mark frequency of a particular
duration of time from carrier detector circuit 108.
The detector circuit 109 has an adjustable tolerance.
.~ This tolerance is adjusted by lengthening or shortening
the "on" time of the clock pulses. By lengthening the
"on" time of the clock pulses, the circuit tolerance to
slight frequency alterations of the mark and space signal
is enhanced. For example, assuming a 2225 Hz mark -
frequency, if the "on" time of the clock pulse is 1
microsecond, the detector circuit will tolerate a +l Hz
alteration of the ~225 Hz mark frequency. By the same
token, if the "on" time duration of the clock pulse were
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lengthened to 5 microseconds, the detector circuit would ;
tolerate a +5 Hz alteration in the 2225 Hz mark
frequency. This toleration to slight changes in frequency
is necessary in order to correct for drift under severe ;~
temperature conditions in which the transponder may be
operating.
It should be noted that the above discussion regarding
;~ the tolerance of the detector~circuit is an example to
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illustrate the operation of the circuit. The figures used
do not necessarily represent those figures which would
result in an actual embodiment.
The detector 109, therefore, converts mark and space
signals into digital logic level voltages. These logic
level voltages are fed via line 110 to a noise error
detector circuit 111.
Circuit 111 is capable of ignoring high noise levels
of short duration which may be superimposed on the
detected mark and space frequencies. High noise levels of
short duration manifest themselves in short duration
signals of the wrong logic level voltage appearing in the
digital output signal. Circuit 111 counts the number of
such opposite logic level voltage bursts over a specified
period of time and ignores a predetermined number of them,
for example, three. If less than three such opposite
bursts occur in any predetermined time period, circuit 111
is designed to ignore them and produces a corrected
digital output signal on line 112. If the opposite bursts
are more numerous than the predetermined number in a
predetermined time period, erroneous data is produced and
the parity checking circuit in chip 92 will reject the
incoming data requiring a retransmission to the
transponder from the central computer.
The output data of the chip 92 for transmission back
to the central computer is in the form of synthesized mark
and space signals of frequencies of 2225 and 1270 Hz,
respectively. The synthesized slgnal produces an
approximation of a sine wave by the addition of a
plurality of unit step functions of the appropriate
polarity. This synthesized signal must be made smooth or
- 20 -
~'322~ "~
~ ~J
analog before it is transmitted. The transmitter section
of the communication chip 90 performs this function. The
synthesized signal is fed from chip 92 to wide band active
filter 113 via line 93. The wide band active filter 113
has a sufficient band width limitation so as to smooth out
the synthesized signal. The output of the filter 113 is
fed via line 114 to a tri-state power amplifier 115. The
amplifier, when it is turned off, presents a very high
output impedance to the telephone lines 65 and 66. When
the modem enable signal activates the power amplifier 115,
the impedance drops. As a result, when the transponder is
not transmitting, it appears practically electronically
invisible to the telephone line. As mentioned above, a
modem enable signal is generated in chip 92 and activates
the transmitter section of the communication chip
including both the active filter 113 and the power
amplifier 115. The modem enable signal is fed to the
communication chip via line 101.
The narrow band filter 107 has a band width that
strongly limits the injection of the transmitted mark and
space signals into the receiver section of the communica-
~ tion chip. The mark and space detecting circuit 109
;~ further rejects any remaining transmitted mark and space
signals because the signal would have the wrong frequency ~
content. ~ .
For the sake of convenience, the chip 90 has other
circuitry incorporated therein to be discussed below.
However, this additional circuitry does not in any way
affect the receiver and transmitter sections of the chip.
The operation of the C-MOS chip 92 will be discussed
; in detail with reference to Figure 4. A portion of chip
- 21 -
~3'Z~l~
92 consists of a random access memory (RAM) 316, central
processor unit (CPU) 207, and read only memory (ROM) 318.
The CPU 207 interfaces with the vast majority of other
circuitry of the transponder via input/output data
interfaces 317 and 410. The cyc]ic operation of the
transponder is completely controlled by a program
programmed into ROM 318. The accumulation of data from
the utilities, the storage into memory of the time-of-day
consumption in~ormation and the load shedding are all
controlled by the cyclic operation of the program stored
in ROM 318. The program is incremented ~rom instruction
to instruction via the clock frequency generated by
crystal 94 in Figure 1.
The program performs a complete "housekeeping" cycle
approximately every 1.5 ms. The "housekeeping" cycle can
be interrupted to receive I/O messages. These messages
are stored until the "housekeeping" cycle is completed and
are then processed by appropriate subroutines of the
program. For example, the "housekeeping" cycle scans the
alarm inputs and the meter inputs and updates appropriate
accumulators and the time-of-day memory. During this
cycle the transponder could receive a request to transmit
back to the central computer the contents of the
accumulators. The "housekeeping" cycle is temporarily
interrupted to decode this instruction. The instruction
is stored and the cycle resumed. When the cycle is
com~leted the program is sent to the appropriate
subroutine to carry out the instruction stored. Upon
completion of the instruction the !'housekeeping" cycle is
begun again.
~ Digital data from the communication chip 90 is fed
.;,'~
:::
- 22 - ~
, .
~3Z219
into a receiver section 319 of chip 92 via line 91.
Receiver section 319 and CPU 207 check word and block
parity, timing and framing. If all is in order, the CPU
207 executes the instruction at the end of the current
"housekeeping" cycle.
The transponder is capable of keeping track of the
electric power consumption on an hourly basis for a period
of approximately 42 days~ In additlon to being fed to an
accumulator register as described above, the pulses are
fed to time-of-day memory 57-64. During a 1 hour time
period a particular address in time-of-day memory 57 to 64
is continuously filled by pulses representing the power
consumed during that 1 hour. At the end of that time
period, C~U 207 increments the address of time-of-day
memory 57-64 so that subsequent pulses for the next time
period fill the next address location~ This hourly
incrementing of the time-of-day memory 57 to 64 begins
upon initialization and is repeated continuously until
.
being reset~ Upon reset the time-of-day memory 57-64 is
cleared and the above described sequence begins again~
When the transponder is initialized a real time clock :~
; 500 is set in the transponder~ As a result, the accumula-
tion of power consumed~during any fractlon of the first
hour is stored as well as power consumed during each
subseuqent;l hour time period. In other words, if the
real time clock is set on the half hour, and thereafter
the address locations in the time-of-day memory are
incremented each hour on the hour, the address for that
first consumption mesurement~will relate to~only one half
hour. The ROM 318 contains the initlal starting address
for storage of the time-of-day accumulations in the
~;
- 23 - ~ ~
"': ~~'' ~
22~9
time-of-day memory 57 to 64. This initial address i5
loaded into RAM 316. This initial address is incremented
for each subsequent time-of-day transfer to the time-of-day
memory 57 to 64. The first memory space in the time-of-day
memory is used for storing the size of the fraction of the
first hour after initialization or resetting. The second
memory location contains the quantity of power consumed
for this fractional time period. The next and subsequent
address locations contain the quantity of power consumec~
for each subsequent time period.
The transponder of this embodiment has a time-of-day
memory 57 to 64 in which each address location has an 8
bit binary count and so the largest number storable in any
1 hour time period is 256 units of energy consumed.
Lines 119 to 128 in Figure 1 are 10 address and memory
lines interconnecting the CPU 207 in chip 92 with the
eight memory units 57 to 64. Lines 126 and 128 are
connected to resistor chip 97 and are presently terminated
therein since there are ten address/data lines and only
eight memory units. Line 125 is also connected to a
resistive network in chip 97. Depending on the
termination of this line, chip 92 operates in the function
described above or in a telementry mode.
Lines 129, 130 and 131 are the read/write scan lines
which enable the CPU 207 to write into and read out of
various address positions within the time-of-day memory
units.
Memory and address lines 119 to 127 are also connected
to relay driver chip 100. Relay driver chip 100 contains
nine driving amplifiers which produce enough power to
; ~ activate relays 67 to 70 and one half of relay 71. Since
';
:
- 24 -
~3~Z~3
relay driver chip 100 contains only nine amplifiers, a
tenth has been placed in communication chip 90 to operate
the second half of load shedding relay 71 via lines 128
and 132.
When it is requested by the central computer to load
shed in a dwelling containing a transponder, the correct
logic voltage levels appear on lines 119 through 128. The
ten amplifiers must be turned on in order to activate
their associated relays. This is accomplished by a signal
appearing on MUX line 133. The signal is derived from
chip 92 on line 134 and is amplified in a MUX amplifier
contained in communication chip 90. Thus, simultaneously,
upon the generation of the MUX signal by chip 92, al] the
relays are switched in accordance with the logic signals
appearing on lines 119 through 128. It should be noted,
that since lines 129, 130 and 131 are inactive during load
shedding, signals appearing on lines 119 to 128 do not
affect memories 57 to 64.
The chip 92 also contains a transmit coder unit 335.
..
The coder unit is controlled by CPU 207 and produces a
.;~ ~: ~ : ,.
series of digital words upon receipt of the appropriate
instruction word set. The series of digital words is the
data word set and is comprised of an alert word, a word
representing the transponder identification code, the
~: ~
customer identification code, a series of data words, a
block parity word and an~end of transmission word.
Transmit coder 335 is connected to an FSK generator
336 which produces, as mentioned above, a synthesized
version of the sinusoidal wave mark and space
- ~ : .:~
frequencies. A "high" logic~level voltage representing a
"1" bit in the series of digital words to be transmitted
i; .
,:
:~
is converted into a burst of synthesized mark frequency.
A "low" logic level voltage representing a "0" bit in the
series of digital words to be transmikted is converted
into a burst of synthesized space frequency. The output
of the FSK generator is fed to communication chip 90 via
line 93.
Some of the input circuitry to the transponder may be
connected to mechanical contact type components which are
susceptible to contact bounce. The transponder according
to the present invention eliminates this contact bounce by
virtue of a debounce subroutine in the main program. The
mircoprocessor scans each utility input twice in two
consecutive passes. The same response must appear on more
than one pass before a valid pulse is stored or an
accumulator incremented. The debounce subroutine cycles
the scan of these utility inputs once every 15 ms and
since a contact bounce would be faster than that, the -
circuit is virtually immune from registering an incorrect
~; pulse due to contact boance.
The alarm inputs have devices connected thereto which
could produce momentary signals wrongly indicating a valid
warning. This problem is eliminated by comparing the
signal on each alarm over a 500 ms time period. If a
signal still appears as an alarm input after this time, a
valid alarm is ~assumed. The program scans the~alarm
inputs several times during the 500 ms time period.
` The program which controls the operation o~ the entire
system is stored in a ROM 318 and operates via a series of
subroutines. For the sake of economy, logic chip 92 is a
LSI chip and contains many logic elements. However, the
same results could be obtained using many interconnected
-26 -
-:
~13%2~
discrete integrated circuit components. Figure 5 shows in
detail the various components which go to make ~p a
particular LSI chip used in a particular embodiment of the
present invention. It should be noted that with respect
to Figures 4 and 5, lilce blocks have been given like
reference numerals.
The timing signals are generated by piezoelectric
element 94 ~Figure 1) and timing pulses enter the chip via
lines 95 and 96. Timing logic block 200 controls these
pulses and feeds them to the various components of the LSI
chip. Timing pulses are fed to program counter 205 which
conditions the ROM 318 to sequence it through the various
steps of the compu~er program stored therein. Program
statements from ROM 318 are fed to CPU 207 via an
instruction decode circuit 220.
Receiver logic 319 receives the decoded information
from communication chip 90 and upon instruction from CPU
207 transfers the correct information to CPU 207 which, in
turn, transfers it to RAM 316. Transmit logic 335
20 receives information to be transmitted from CPU 207, after ~
;~ transfer of the information from RAM 316. Transmit logic -
335 is capable of transmitting digital information
directly via lines 211 and 212. This logic sets up the
correct pulse train for transmission, i.e., it adds the
start, stop and parity bits and sets up the correct
framing. The digital information can also be fed to block
336 where it is translated into an FSK signal for
transmission via line 216.
Block 222 i5 the I/O bus interface between CPU 207,
the time-of-day memory and load control components. The
time-of-day memory 57-64 shown in Figure 2, is connected
::
'
~3~ 3
to block 222 via bus 232. Block 224 is the interface
between the CPU 207 and the time-of-day memory for
read/write strobe signals. These signals are transmitted
over bus 234. This block also generates the MUX signal
which is transmitted via line 236.
The CPU 207 handles the alarm inputs and the three
utility consumption inputs. Alarm input interface block
213 interfaces the various alarms with CPU 207. Utility
interface block 209 interfaces the inputs from the utility
meters with CPU 207. The addresses for interfaces 209 and
213 are actual memory locations in RAM 316~
The entire system can be sent through a logic test
program upon the activation of block 206. Logic test
: block 206 is activated by applying a high logic level
voltage to line 208. Not shown in Figure 5 are the X
register, the Y register and the X,Y address decode logic
which places the various data in the correct addresses in
RAM 316.
The computer program is hard wired into ROM 318 in
~ :
machine language. Each statement in the program consists
of a 12 bit data word. Bits 0, 1, 2, 3 and 8 are used for
direct addressing. Bits 4, 5, 6 and 7 are used for data
or for further instruction decoding. Bits 9, 10 and 11
specify the actual instruction group. In the program
~`~ listed below, the statement number and the value of bits
; 9, 10 and 11 ~re given.
:
:~:
~: :
- 28 - ~
~13~
In the program to follow, the various instructions are
given using the following notation.
L = contents of memory location L
P = literal data
CF = carry flag -- set if one is to be carried in AC
AC = accumulator
RM = contents of memory location indirectly accessed
via X and Y
R = literal data
1 0/1 I P I Lj = Skip the next instruction if the result
of "ANDing" the contents of location
0,L (l,L) with P is not equal to zero.
2/3 I P I L¦ = Skip the next instruction if the result
of "ANDing" the contents of location
0,L (l,L) with P is equal to zero.
L 4/5 I P I Ll = Skip the next instruction if the
contents of memory at location 0,L
(l,L) is not equal to P.
1 6/7 I P I L¦ = Skip the next instruction if the
contents of memory at location 0,L
(l,L) is equal to P.
8/9 I P I L¦ = Take the value of P and place it in the
location 0,L (l,L).
A/B I P I Rl = Set the program counter to the address
specified by 0,P,R (l,P,R).
C/D ¦ 0 ¦ L¦ = l Is added to the contents of location
L and then placed back in location L. -
If the result of the operation
generated a carry, CF will be 1.
L C/D ¦ 1 ¦ L¦ = The value of CF is added to the
contents of location L and then placed
~ back in location L. If the result of
I the operation generated a carry, CF
will be 1.
¦ C/D ¦ 2 ¦ LJ = Not a valid instruction.
¦ C/D ¦ 3 ¦ L¦ = Not a valid instruction.
C/D ¦ 4 ¦ L¦ = The value of the accumulator is placed
in location L.
-
,
- 29 -
:
~;32~
¦ C/D ¦ 5 ¦ L¦ = The contents of location L are "ANDed"
with the contents of the accumulator
and the result is placed back in
location L.
C/D I 6 I L~ = The contents of location L are
exclusive "ORed" with the contents of
the accumulator and the result is
placed back in location L.
¦ C/D ¦ 7 ¦ L¦ = The contents of location L are "ORed"
with the contents of the accumulator
and the result is placed back in
location L.
¦ C/D ¦ 8 I Ll = The contents of location L are placed
in the accumulator.
¦ C/D ¦ 9 ¦ L7 = Not a valid instruction.
¦ C/D ¦ A ¦ L¦ = Skip the next instruction if the
contents of location L are not equal to
the contents of the accumulator. ,
¦ C/D I B I Ll = Skip the next instruction if the
contents of location L are equal to the
contents of the accumulator.
L C/D I C I L¦ - Not a valid instruction.
C/D ¦ D ¦ L¦ = The contents of location L are "ANDed"
with~the contents of the accumulator
and the result is in the accumulator.
C/D I E ¦ Ll = The contents of location L are
exclusive "ORed" with the contents of
the accumulator and the result is in
the accumulato~.
¦ C/D ¦ F ~ L¦ =~The contents of location L are "ORed"
with the contents of the accumulator
and the~result is in the accumulator.
E/F ¦ ¦ ¦ = Take~the contents of the locatlon
specified by (X,Y) and add 1 placing
the result back into (X,Y) along with
~`~ 4 ~ the indicated carry.
E/F I 1 ¦ ¦ = Take the contents of the location ¦~-
specified by (X, ) and add the carry 1
placing the remainder back into (X,Y)
40 ` and CF.
E/F I 4 1 ¦~1 = Take the contents of the accumulator
~ and~ put it in location (X,Y).
;~ I E/F I 5 ¦ 1 = Take the contents of the location as
specified (X,Y) and "AND" it with the
contents of the accumulator and return
the result to the location (X,Y). -~
:
Z~
¦ E/F ¦ 6 ¦ ¦ = Take the contents of the location as
specified (X,Y) and exclusive "ORed" it
with the contents of the accumulator
and return the result to the location
(X,Y).
E/F I 7 ¦ ¦ = Take the contents of the location as
specified (X,Y) and "ORed" it with the
contents of the accumulator and return
the result to the location (X,Y).
I E/F I 8 1 1 = Take the contents of the location as
specified (X,Y) and put it in the
accumulator.
E/F I A I R¦ = Skip the next instruction if the
contents of location (X,Y) equals the
-~ contents in location R.
! E/F ¦ B ¦ R ¦ = Skip the next instruction if the
contents of location (X,Y) does not
equal the contents in location R.
E/F I C I R ¦ = Take the contents of location R and put
~ 20 it in the accumulator. -
:- I E/F I D ¦ ~ = Take the contents of location (X,Y) and"AND" it with the contents in location
R and put the result in the accu~ulator. ;
~;. ¦ E/F ¦ E I Rl = Take the contents of location (X,Y) andexclusive "OR" it with the contents in
I location R and put the result in the
accumulator~
E/F I F ~ = Take the contents of location (X,Y) and
oRil it with the contents in location R
and put the result in the accumulator.
~ ~ :, .,
`: :
~ .
:
., ,
:
:,
::
,~
~-: - 31 -
- 113~.''21~
The following is a computer program for the chip:
PROGRAM START
000 000
001 877
002 877
003 E40
004 846
005 E00
006 EA0
007 ACF
008 067
009 A16
0OA EAA
00B AOF
00C 217
00D EB6
00E A16
00F EC0
010 E40
: 20 011 C07
~ 012 667
: 013 A05
014 EC8
015 C74
: ~ .
~;~ PULSE INPUT
.
016 807
017 846
018 E80
019 C40
01A 210
01B A70
01C: 877
01D~ 856
01E EEF
01F C40
020 EEF
021 CB0
022 A60
023 CD5
024 C51
025 041
026~ A38
027 28F
:028 A2D
029 EC5
02A C64
02B 214
02C A36
02D 807
02E E00
02F EBA
030 A26
031 EC0
032 E40
033 C07
034 667
035 A25
.
~:~: : :,
- 32 -
1~3ZZ~L~
036 656
037 A3E
038 866
039 221
03A A2D
03B 876
03C 2:Ll
03D A2D
03E 466
03F A3B
040 ECF
041 C:E5
042 C41
043 C80
044 C45
TIME OF DAY CONSUMPTION PROGRAM
045 08F
046 41A
047 A60
048 084
049 A4F
04A DOA
04B DlB
04C DlC
04D EC3
04E D5C
04F D8A
050 C4D
051 D8B
052 C4E
053: D8C
054 C4F
055 91F
056 80D
057 80E
058:~: 284
059 92F
05A~ COD
05B:: ClE
05C 24
0:5D: 92E
05E~ ECl
:05F : C54
ALARM SENSE-PROGRAM :
060 38:4
g6612~ 874
063 817
064 ~E80
o6665 80
067 EA0
068 : 230
~069 A70
06A 877
06B EEF
06C CD3
:,:
~ : ~ 33 _ ~ :
'.-: :
:
: :. .. ,: . :: :::.: , ` :::: .: . ' .:, ::. ... . . :`'., .': '.
~L~3~9
06D C72
- 06E EEF
06F C43
RECEIVE MODE
070 60A
071 B3F
072 28F
073 B22
07~ 000
: 075 987
076 34B
077 A7D
078 D02
079 D13
07A 3E3
07B 904
07C BFF
: 07D 90E
07E 902
~ 20 07F 903
"~: 080 llF
081 A7B
082 D86
083 C68
084 D8E
:085 C69
086 D04
: 087 714
::~ 088: A8E
089 808
`~. ~: 08A ~ 809
~ : 08B 5F6
`~ ~ 08C 7FE
~; 08D 904
~: 08E~ BFF
. 08F 724
: : : 090 ~ A9B
: 091 : CEF
: 092 8CO
;~ 093 C70
094 6F0
: 095~ 8D
`~:~ :~: : : : ~ 096 D86
097 ~ DE7
098 ~ CB0
099 A8D
09A~ : BFF
09B 734
: : 09C AAl
~09D ~ :D49
:O9E D86
09F D48
:OA0 BFF
OAl : 744
OA2 AA7
:~ OA3 D41
~ : OA~ : D86
:: OA5 D40
~ OA6 BFF
:~ :: ~ : :
~ :34 -
. :: ~ :
~132;2~9
OA7 4F8
OA8 6F9
OA9 A8D
RECEIVE MODE EXECUTION ~'
OAA 719
OAB AAF
OAC D89
OAD D44
OAE B25
OAF 728
OBO ACE
OBl 509
OB2 A8D
OB3 3C9
OB4 ACO
OB5 EC4
OB6 - DF9
OB7 C46
OB8 807
OB9 ECO
OBA E40
OBB C07
OBC 667
OBD ABA
OBE: 914
OBF B25
OCO~ 749
OCl~ AC9
:~ :OC2 80D
OC3~ 80E
OC4: 8OF
OC5 91F
OC6 BED
OC7~ 924
OC8 B25
OC9 759
OCA A8D
OCB~ 802
OCC 9A4
:OCD B25
OCE:: 738
OCF AE3
ODO~ EC4
ODl DF9
OD2 C46
OD3~ 807
OD4 349
OD5 827
OD6 389
OD7 ~ 847
D8 ~ D80
DA C07
ODB D81
ODD ~: 657
ODE A8D
ODF 914
OEO : 446
- 35 ~
~ " ,,~
., : ~
2'~
OEl 924
OE2 BlF
OE3 748
OE4 AEF
OE5 846
OE6 509
OE7 AD7
OE8 719
OE9 A8D
OEA D80
OEB D45
OEC D81
OED D4D
OEE AEl
OEF D89
OFO 758
OFl AFB
OF2 C4D
OF3 D80
OF4 C4E
OF5 EC8
OF6 DFl
OF7 C4F
OF8 81A
OF9 902
OFA BFF
OFB 768
OFC AFF
OFD C4C
OFE: AC7
OFF 778
100 B03
101 C4B
102 AC7
103: 788
104 A8D
105 90A
106 90B
107 90C
108 D8A
109 C4D
lOA D8B
lOB C4E
lOC D8C
lOD C4F
lOE 91F
lOF D80
110 C4D
111~ D81
112 C4E
113 ` 92F
114 DOA
115 DlB
116 DlC
117 000
118 000
119 74C
IlA B08
llB : ` 9FA
IlC 9FB
~:
~ - 36
.. ,: : ':
., ~ :,.
: -''` ~ : , , , , .. . . ` - '
~L~3Z;~9 ~
llE 944
llF C8C
120 D40
121 04F
123 A75
124 974
125 08F
126 B36
127 8ED
128 8FE
129 91F
12A EC3
12B CDD
12C D40
12D C8E
12E C4B
12F 8FD
130 91F
131 C8D
132 D4A
133 C8E
134 D8B
135 90C
136 ECC
137 DF0
138 D47
139 902
13A 901
13B : ECF
13C D43
13E 82A
TRANSMIT MODE : : ii.
13F~: 61A
140`: B46
141 ~ D02
14~2: 792
143:: DFF
144 80F
40i ` : :145 ~ AEl
146~- ~: 62A
:1;47 B63
148 ~ AOB:
:149 B4D
14A:::: D01
4B 311
14C : BFF
14D SD2
14E ~ B51
14F ~ D02
150 BFF
151 : 7F3
152 ~ ~D03
153 : 5F3
154 B57
155 902
156 BFF
157 14F
lS8 18F
; ~ : . . :::
"i
37
,~: : - : : :
, . ,.,, , ,;, , . .. . ` ,,: :, :, ` ~ .. : . :. . ` .` ` .,
~3~Z~3
159 BFF
15A 84A
15B EC4
15C DFO
15D D47
15E 9FZ
15F 9F:E
160 8FB
161 8F9
io 162 BFF
163 EC4
164 DFO
165 D47
166 34F
167 BFF
168 64A
169 B79
16A ECF
16B DE7
: 20 16C D48
16D 939
16E ECF
16F CEF
170 D59
171 COA
172 D88
173 C68
174 D46
175 D89
:~ 30 176 C69
177 D4E
178 DFF
179 65A
: 17A B86
17B D85
17C D48
17D D8D
17E D49
17F 86A
~`~:` 40 : 180 504
181 87A
182~ 903
183 902
184 901
~: ~ 185 B72
186 66A
187 : BDE
188 114
189 B9F
18A : 502
18B 952
18C D82
: 18D C46
18E D81
~: 18F C47
190 E80
191 D48
`: 192 ~:C07
~ 193 : : E80
.~ 60 194 D49
~: :
., :
:
,~
~ : - 38 -
,;.
~13~2~9
196 D01
197 761
198 B72
199 D02
l9A 782
l9B B84
l9C ECE
l9D D54
19E B7F
l9F 124
lA0 BC6
lAl 701
lA2 BA9
lA3 C8C
lA4 D48
lA5 C8B
lA6 D49
lA7 D01
lA8 B72
lA9 846
lAA 711
lAB BBl
lAC 867
lAD EEF
l.AE D48
lAF C82
lB0 BA6
lBl 721
lB2 BB9
lB3 847
lB4 E80
lB5 D48
lB6 C07
lB7 E80
lB8 BA6
lB9 D8A
lBA C4D
lBB D8B
:lBC C4E
lBD D8C
lBE C4F
lBF : 91F
lC0 C8D
lCl : D48
lC~2 C8E
lC3 D49
lC4 EC4
lC5 B9D
lC6 D81
lC7 : C4D
lC8 D82
lC9 C4E
lCA D83
lCB C4F
lCC ~ 9lF
lCD C8D
:lCE~ D48
lCF : C8E
lD0 D49
lDl D83
lD2 DBC
; ~ , j
,,
"
~ - 39 ~
: ` : : :
, .:
:: :
~13Z;~L9
lD3 BDA
lD4 D82
lD5 DBB
lD6 BDA
lD7 D81
lD8 DAA
lD9 B71
lDA DOl
lDB D12
lDC D13
lDD B72
lDE 67A
lDF BE5
lEO C88
lEl D48
lE2 C89
lE3 D49
lE4 B71
lE5 68A
lE6 BEA
lE7 9E8
lE8 9E9
lE9 B71
lEA 38F
lEB 8OA
lEC A7B
lED 846
lEE 847
lEF E80
lFl 857
lF2 E80
~lF3 C4E
lF4: 92F
lF5 91A
lF6 90B
lF7~ 90C
lF8: 8lD
lF9~ 80E
lFA : 91F
:lFB 80D
lFC~ 92F
lFD AC7
lFE~ 000
lFF : 856
DONE
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