Note: Descriptions are shown in the official language in which they were submitted.
~L3~3
MODEM ~ITH AUTOMATIC PORT RECONFIGURATION APPARATUS
Background of the Invention
The subject invention relates generally to digital data
communications and more particularly to apparatus employing multi-
plexing to combine a plurality of digital data channels for
transmission over a single transmission path. The invention
provides apparatus for automatically varying the channel config-
uration and is particularly useful in conjunction with digital
data modems.
In the prior art, digital data modem apparatus is known
for interfacing with data processing apparatus at either end of
a transmission channel such as a telephone line. Multiport
modems are also known which provide a plurality of channels for
communication with a similar plurality of channels of the
associated data processing apparatus. The multiple channel
information is multiplexed for transmission over an individual
line. Multiplexing is typically accomplished by l'D~ (time
division multiplexing) with bit-by-bit interlacing of channels.
Of course, many methods of multiplexing are ]cnown and could be
used according to the invention.
In initiating communication across a transmission line
between modems, it is generally known in the prior art to provide
a sequence of initializing signals, in what is sometimes referred
to as a "handshaking" operation. Such signals may indicate when
a data source actually wants to transmit data or wants a channel
at its disposal ready for transmission An example of the former
alternative currently in use is RTS (request to send or ready
for sending). An example of the second alternative is DTR (data
terminal ready) or DSR (data set ready). RTS is present only
while a transmission is in progress, while DTR will be present
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throughout the time that the data source i5 engaged in inter-
active comrnunication with a device such as a CPU. It is also
known to provide DCD (data carrier detect) and RLSD signals
(receive line signal detect). It is known not only to provide
DCD in the presence of a data carrier from a communicating modem
but also to set DCD low upon receipt of a coded inverse of the
RrS signal (RTS). One commercially available modem incorporat-
i~g~the use of signals as described above is the Milgo 9~ MM
(trade mark). Such signals may be particularly taken advantage
of in accordance with the invention as will be presen-tly
described.
Known multiport modems contain the necessary circuitry
for switching between various port configurations in response
to commands set manually by an operator. Such channel allocation
or port reconfiguration is useful when data traffic patterns
differ relatively infreque~kly in a known manner. It is then
possible to set up a mode switching schedule which requires the
intervention of an operator from time to time to effect mode
changes. Moreover the actions of two operators, one manually
operating a modem at each end of the transmission line, must
obviously be coordinated. To make more efficient use of the
expensive telephone channels, it would be desirable to have a
dynamic port reconfi~uration capability wherein the date processing
apparatus and modem system would cooperate to reconfigure ports
rapidly and automatically without operator intervention.
Summary of the Invention
.
It is therefore an objec~ of the inv~ntion ~o recon-
figure modem port configurations without manual intervention.
It is another object of the invention to automatically
coordinate mode switching at two modems linked by a transmission
path.
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It is a further object of the invention to enable
dynamic port reconfiguration, allowing a modem or multiplexer to
~; adapt to changing traffic patterns flexibly and in an unscheduled
manner so as to obtain the optimum use o.f available bandwidth at
i. .
` any given time.
I~ accoxdance with the present invention there is
! provided a modem system comprising a master modem, a slave modem
; and a transmission path therebetween, each modem including multi-
plex means, a plurality N of data ports and a line port coupled
1 to said transmission path and operating in multiplex relationship
with said data ports, each modem further including selection
means operative to assign channels occupying together a given
bandwidth to different combinations of N and less than N of said
data port~ in corresponding different modes, said mast~r modem
further including a plurality N of demand terminals for receipt
of externally imposed demand signals corresponding to said data
ports respectively, mode switching means responsive to said demand
signals on said demand terminals to control said mode selection
means of said master modem for automatic selection of modes
in accordance with the demand signals actually present, and
control means for transmitting to said slave modem control signals
indicative of demand signal changes at said master modem, said
slave modem including status latch means responsive to said con-
trol signals to store further demand signals corresponding to said
~ demand signals at said master modem, and mode switching means
responsive to said further demand signals to control sald mode
selection means of said slave modem for automatic selection
of modes in accordance with the further demand signals actually
present.
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In a preferred apparatus of the invention when an
apparatus having ports providing data input/output channels to
a first da-ta modem requests a chanye of port (channel) configura-
tion, the request is detected, held and an indication thereof
sent across a transmission path to serve as a port reconfiyura-
tion request to a second, cooperating modem. After a suitable
delay to allow the second modem to switch to the proper port
configuration, the first modem, originally presented with the
port reconfiguration request by the data processing apparatus,
switches to the new port configuration. The data modem or
multiplexer at the end of the line where the request for a new
port configuration originates is treated as the master unit
while the multiplexer modem at the other end of the line is the
slave. Port configuration mode switching is made demand-dependent
so that when a data source does not demand a channel, its channel
is reallocated to the active data sources.
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According ~o another feature of the invention, a modem
user can take advantaqe of master clocks in controlling data
processing apparatus at two modem sites to synchronize operation
between the two modems. Direct software synchronization i~ thu~
made available, removing the need to transmit synchronizlng infor-
mation.
Another important aspet of the invention is the
provision of a sequencing teohnique for switching from one poxt
configuration to the next utilizing handshaking signals prese~tly
employed in communicatio~ systems employing modems. Hardware
simplification is thereby greatly facilitated and problems
enco~ntered in adding and deleting channels are overcome.
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~ ~ . BRIEF DESCRIPTION OF THE DRAWINGS
, ~ _ _
~he preferred embodiment and best mode contemplatcd for .
. i~plementing the just summarized invention will now be d~scribed : .
. in conjunction with the drawings of which:
Fig. 1 is a simplified block diagram illustratiny the
:~ ~ . apparatus of the preferred embodiment of the invention.
I Fig. 2 is a block diagram of channel allocation cir-
I cuitry D .
Fig. 3 illustrates a port configuration s.election
¦ sequence according to the preferred embod.iment of the invention.
1 1 Fig. 4 is a flow chart illustra~ing the operakion of
¦ the preferred em~odiment of the in~ention in dropping channels
¦ from active to inactive status.
Fig. 5 illustrates the operatio~ of the pxeferred
¦embodiment of the invention i~ adding cha~nels from an inactive
to an active status.
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Fig. 6 is a generalized bli~ck d~agram illustrating a
poxt co~figuxation selection oircuit according to the preferred
embodiment of the invention.
Fig. 7 is a schematlc diag:ram illustrating a port
reconfigura~cion circuit for use at either the master or the slave
modem a-cording to ~he preferred embodiment of the invention.
DETAII.ED DESCRIPTION OF THE PRE~ERRED EMBODIMEMT
FigO 1 illustrates a pair of moclems 11, 13 communicating
across a transmission channel 15. Each modem 11, 13 interface~
with a data processing apparatus SUi-~ as zl central processor, data j
terminal or other peripheral. For exampl~, modem 11 may inter
face with a plurality of ports o a i~entr~l processing ~nit (CPU)
12 while modem 13 interfaces with a plurality of ports of some fon~
o~ data terminal equipment (DTE) 14. As known in the prior art,
a mul~iport modem multiplexes a pluralîty of channels outputted
~y associated proces~ing apparatus for conimunication over a
transmission line. For example, a multiport modem may multiplex
four port~ 16, each transmitting at 2400 bits per second for an
overall data rate of 9600 bits per second The cooperating modem
demultiplexes the sihgle channel information. Typically a four
wire line, two-way transmission system is utilized such that
multiplex and demultiplex operations are performed at both ends
s the transmission line.
In practice, it is often desirable to reconfigure ~he
channel or port arrangement~ For example, if two channels of a
our port device are not currently necessary for transmittin~
data it is desirable to`be able to effectively dii~able those two
channel nd allocnte their bandwidtb to channels which are
actively transmitting. In this manner, more efficient data
transmission is achieved.
As alluded to earlier, known multiport modems contain th~
necessary circuitry for switching between various port con~ig-
urations in response to manually set comm~nds. A typical method
of data encoding for a multiport ~ransmitter is indicated in ~ .
While Fig. 2 is somewhat simplified, those skilled in the art will
readily recognize the manner of implementation of this ~ircuitry.
As shown in Fig. 2, the bandwidth allocation in a four
channel system may be determined by a multiplexer clock selection
~ircuit 101 which selects clock signals to be fed to ~our mul~i-
plexer~demultiplexers 103. The clock selection circuit 101 is
driven from a ~lock 105 and includes frequency dividers and log~c
circuits which deri~e four divided clock signals interlaced with
one another in a cyclic four phased clock se~uence ~ 2~ ~3
~4. In response to a code, manually set in the prior art, the
clock phases are selectively gated to the multiplexer/demultiplexer 3
103. The phased outputs of the multiplexe~r~demultipl~xers are
combined into a 9600 bits per second signal on a single line by an
OR gate 104. The OR gate 104 suppli~s the 9600 bits per se~ond
data to modem transmitting circuitry 106 ~here that data is
modulated according to known methods~
For exampler if only two channels A, B of four channels
A, B, C, d are required to transmit data, two clocX phases
~are gated to the multiplexer for tho.~e respective channcl~ A, ~
thereby doubling the bit rate output on tho3~ two channels A, B
while the other two chamlelc C, D are 1naFtive, ¦
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A mannex for lnterlacing the data bit~ at ~ar.ious
speeds is illustrated i~ the following ta'ble:
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T~LE A
Channel
. Speed Mode Data Rate Data Framing .
. 9600 2 4800 4800 ~ ,BorAlrBl~A2~tA3~ 3
.~ : . ~4~B4~A5~B5'~6'B6~A7' 7
:~ . 9600 4 2400 2400 2400 2400 . Aa~Bo~corDotAl~E3lrcl~Dl~
A2'B2'C2'D2'~3'B3'C3' 3
; : 9G00 4 7200 2400 ~1),Al,A2,Bo~A3~4~5~ lt
: A6~A7rA8~B2~9~0~
0' 0' 1' 0' 2' 1' 3' 1' 4'
¦ . .B2,A5~C2~A6~B3~A~tc3
¦ 7200 2,4,5 4800 2400 ; ~ Ao~Al~BorA2~A3tBl~Al~A5~2
. ¦ ~ . B2'A6'A7'B3
: ¦ 7200 3 2400 2400 2400 ~ Ao~Bo~c~Al~Bl~cl~A2~B2r
. ~ C2~P3~B3~C3,
~80~ ,3,$ 2500 2400 - _ o~3~A ~ A2~2,~3~A3,
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In accordance with the preferred embodiment of the
invention, a modem 11 op~rating as a mast~!r modem recei~es a
port configuration or channel allocation request in coded form
from cooperating data processing apparatus such as a CPU 120 Th~
present port con~iguration is controlled by a code supplicd by
a mode shift register 17 or other storage device. The codc pro~
vided by the shift regi~ter 17 selects the port c:onfiguration .
as does the code provided by manual selection in prior art
multiport modems. A comparator 19 continually ~or[~pares: the .
port configuration request of the CPU 1~ to that indicated by
the mode shift register 17. .~hould the CPU request a different
port configuration than that indicated by the shift register 1~,
th~ - comparator 19 generates shift register control signals r
indicative of a new mode code to be provided by the registe~ 17.
After a suitable delay provided by timing apparatus 21, the
shift register control information is used to change the mode-
indicating code in the shift register 17, thus establishing a
n~:w port c:onfiguration in the multi port mc: dem 11.
The delay provided by the timiny apparatus 21 serves
to provide a ~ufficierlt interval for the second~ or slave modem 13
to respond and set up a port configuration corresponding to the
newly requested port configuxation in the master modem 11.
Durlng this time interval, the master modem 11 transmits si~nals
to the slave modem 13 which are in~expreted as a transmitted port
confiyuration request by the modem 13. ~pparatus functionin~ .
s~laxly to tha~ at the master m~d~m 11 is then used to set the p~rt o~nfig-
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uration of the sla~e modem 13. In particular, comparison appara~
tus 23 detects the new port configuration request by comparing
the request code to the mode indicated by the shift regi.ster 25.
A~ain the comparator 23 generates shift r~gister contro]. informa-
tion, which after a suitable delay adjust~l the mode indi.cation
pxovided by the shift register 25 in order to alter the port
configuration of the modem 13.
In implementing the apparatus just described with
re~erence to Fig. l, it is found very advclntageous to ec;tablish
a channel priority and reconfiguration discipline in order to
simplify the oircuitry and utilize existing modem line disciplin~
. ¦ Thus, a poxt configuration mode selection sequence i~ established .
¦ acc~rding to the preerred embodiment of ~he invention, as
: I illustxated in Fig. 3 and Table I below: -
. I TABLE I
¦ RE SUI,TANT
i _SPEED PC)RT RES)UEST ~U3SULTANT PO~I COYrlC~;R/~TII~
I
. 9600 l X X 1 3 24 24 2~ ~4
I X 1 0 5 ~8 24 2
: ~ . 1 0 0 ~ or 72 24
Il . 0 0 0 l 96
I
1 7200. l X l X 3 24 24 24
.1 I I 1 0 5 48 24
0 0 .. l 7~
4800 l l X ~ 3 . 2~ 24
l l 0 - . ~ .48
~.
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Table I ~llustrates various exemplary port configura-
tions at various data rates. By way of example, the ensuing
description will consider the 9600 bit per second speed. The
tabl~ indicates the mode code consisting of four bits representa-
tivc of four ports or channels ~, B, C and D. The codc consists
of l's, O's and "don~t cares" indicated by the character "X". The .
poxt configuration corresponding t9 a parkicular mode code lies
. in the same row as the mode code. Additionally, each mode is
given an arbitrary numberf 1 through 5.
As T~ble I illustratest in mode 3~ each of the channels
¦¦ A, B~ C and D is transmitting at 2400 bits per second. In mode
¦¦ 5, channel D is dropped as`indicated by the "0" in the mode code
¦ channel under column "D". Channels B and C transmit at 2400 bit~
. ~ per second, while channel A operates at 4800 bits per second when
1 chann~ls A and B are operative, one of two ~odes 4 or 2 may be
! selected. In mode 4, the channels A, B are selected to operate
¦¦at 7200 bits per second and 2400 bits per second, while in mode
1,2 they operate at 4800 bits per second and 4800 bits per second,
!I respectively. Finally, in mode 1, the mode selection code
:- !indicates that only channel A is to be operative and that channel
¦A operates at 9600 bits per second. `
Thus, according to the preferred embodiment as illus-
¦trated by Table I, the channels are given a priority descendiny
~¦from A to D. The lowest priority channel which is operating dic-
,ta~es the mode. For example, mode 3 is determined solely by
¦whether channel D is operating and is not dependent upon whether
channels B and C are indicated as being operative or inoperativc.
ICh.~nncl A is the mos$ favored channel, and its rate of tran3mls~ion
I Icontinuously increases a~ o~her channels drop out.
!
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As alluded to above, the automatic port configuration
circuit of the preerred embodiment of the invention compares the
channels r~quested by the newly presented request code vs. the
channel ac~ive signals. ~f ports have to be added or deleted,
the proper signals are generated to force the remote (slave)
modem to switch in the same manner as the local (master) modem.
Both master and slave modems are controlled to go thro~gh the
sa~e sequence in order to arrive at the proper port configuration.
Accordi.ng to the preferred embodiment, th~ sequence is determined
according to the flow shown in Fig. 3. According to this
sequence, a modem operating ln any of the modes 5, 4/2 or 1 may
add the channels necessary to return directly to mode 3. However,
to move up the sequence to any other mode, for example, from modc
1 to mode 5 requires that an intermediate return to mode 3 be
made before progressing to mode 5. In addition, progressing down
the sequence from a higher level mode to a lower lever mode
requires stepping through any intermediate modes. This technique
of sequencing proves to be advantageous in facilitating the
signaling technique used to communi.cate mode changes to the slave
or r~mote modem.
This si~naling technique is the use of a DCD
~data oarrier detect) dr~p in the slavb modem to cause the port
configuration circuit at the slave to drop channels to achieve
a new mode. According to the scheme already explained, it i5
always the least significant port which determinas when the slave
is to fall back. Because a channel ~hich has been dropp~d i~
no longer beiny used at all, there i~ no easy way of returning
directly to a mode where that channel is again active because the
time dirision 510t or thut ~hannel has be~n reassigned.
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Thereore, to reactivate a channel accord.~ng to the pre~erred
embodiment, the port configuration circui~' retuxns to mode 3
wherein all channels are active and proceeds to remove active
channels until the desired state is reached~ Since channel A is
always active, the DCD drop code for that channel (denoted ADCD)
is used to signify and initialize a return to the highest mode,
mode three. From mode three, the normal l)CD channel dropping
sequence i~ used to fall back to the proper configuration.
` An example of the just described sequencing tezhnique
is illustrated in Figs. 4 and 5. In this example, DT~ ~data
terminal ready) is used as the control co~e at ~he master site,
which is oxiginally configured in mode 3 i~nd then changes to mode
l and then to mode 5.
Fig~ 4 illustrate~ the dropping o~ channels from mode
3 to mode l. Initially, the master modem is in the norm~l idle
state of mode 3 wherein the DTR signa1s for channel A and channel
D ~re logical ones according to the logi conventions of Table I~
Similarly, th~ slave modem is in the ldle state o~ mode 3, the
DCD levels of channel A and channel D rep:resenting logical ones.
A change to mode l is initiated by the master when the DTR level~ :
for ohannels B, C, and D drop to zero at ~he same time. A
delay of 200 milliseconds (ms) ens`ues, during which the DCD dxop .
out code for channels B, C, and D is transmitted to the slave
modem. A timed delay of lO0 ms is provided in the slave modem
for the slave to detect the DCD drop and start the change through
mode 5 and 4 eventually reaching mode l. Preferably, the interme-
diate mod~s, such as 5, 4 are passed through rapidly as indicated
by the .4I6 msec time in Fig. 4. Due to the longer delay at th~
master~ the slave is se~ up in mode l before the mas~er falls
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back to mode 1. In this manner, it is assured that the slave
is xeady for the operation of the new master configur~tion. ~n
a similar manner, any number of active ports can ~e dropped. When
the mastex falls back to mode 1, normal transmission at 9600
bits per second is resumed on the single A channel.
~ ig. 5 illustrates the process of adding ports as the
system goes fr~m mode 1, where only channel A is operative, to
mode 5, wherein channels A, B, and C are operative. Initially
the master modem is in mode 1 with the DTR signal for channel A
being positiveO Similarly, the slave modem is in mode 1 with
the DCD signal for ~hannel A being positive. The change to mode
5 is initiated when the DTR signals for channels B and C go high.
d~lay of about. 20.0 ms is then provided during which the ma3ter
transmits all marks to the slave, indi~ating the drop of thc DCD
signal for channel A. A delay of 100 ~9 is then provided at the
slave af~er the dro.p-out detection during which time the slave
¦switches into mode .3 wherein all four channels are operative, .¦
Again, the slave reaches m~de 3 before the master switches int~ ¦
mode;3 due to the arrangment of the delay timings. I
Once the master is in mode 3, it detects that mode 3
is still impropex because the D channel DTR signal is low. The
¦procedure of Fig. 4 is then essentially repeated to d~op channel
to return to mode 5. The DCD drop code for channel D is
transmi~ted to the slave, which drops to mode 5 after a delay.
A longer delay is provided at the master so that the master
switches to mode 5 after the slave and res~mes noxmal transmission
ovcr ch~nnel ~ at 4800 bits per second, ch~nnel B at 2400 blt~
per second, and chan~el C at 2400 btt~ per secondd Thus, Fig. 5
¦illustrates the ~echnique o~ returning to the mode wherein all
channels are active ~n order to add port~.
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In the above discus~ion~ the use! of the DT~ and ~CD
signals has been employed because they are! typical signals
recognized in transmission between modems. However other
signals could be used to provide mode code!s to the master and
slave modemsc For example, the signal known as RTS trequest to
send) may be used at the master to indicate the mode code as w211
1 as the DTR level described above.
¦ As already mentione~ a demand signal may indicate when
a data source actually wants to transmi~ data or wants a channel
at its disposal ready for transmission. ~n example of th~ '
¦ former alternative currently in use i~ RTS. An example
¦~f the second alternative is DTR (data term~nal ready)
Which signal is used ~s the demand signal
. ~ from any data source will depend largely ~pon the nature of the
¦ source. If the source is of th'e ki.nd, e.~ a tape reader, which
predominantly tran~mits in lengthy blocks of some minutes
¦ duration alternating with similarly l~eng~hy,quiescent periods,
it will normally be satisfactory to use RTS as the demand signal~
RTS is present'only while a transmission is being effected and
¦ the use of RTS will allow a bandwidth reallocation to be useful~y
¦ made in the lengthy periods when the data source is not trans-
¦ mi~ting and RTS is absent.
' 1 Such a procedure will normally be inappropriate when the
' Idata source is an intera~tîve source, such as a data processing
,,~t~rminal, because an interactive source tends to switch rapidly
! bct~en transmitting and quiescent states and concomitant rapidmod~ switching is undesirable. In this case thP demand signal can
bC DTR which will be present throughout the time that thc data
I' ~ , .
sourcc i~ engaged in intexactive communlcation with th~ dcvicc~
such ~s a CPU (central processing unit) at the slave end of the
line. Bandwidth reallocation will then only occur when the data
source drops DTR because ît no longer wants ~o be in communication
with the CPU.
~ s also alluded to above, it is known not only to
provide DCD in the presence of a data carrier from the master modc~
but to set DCD low on receipt of coded ~TS. A conventional form~t
for coded RTS is a train of all ones for a predetermined interval
which may be about 200 ms in the case of channels B, C and D,
although it is also poss.ible for a specific diyital cvde word
to be assigned to coded RTS.
The slave modem detects cbded RTS in channels B, C and
D. ~s described a~ove, this action is delayed to ensure reliable
detection ~otherwise detection could arise falsely from a
longish ~rain of all ones arising dul-ing ~ormal data transmissi~n1>
Fig. 6 illustxates a simplified block diagram of a
generalized circuit providing port configuration control in a
mastex or s la~e modem accordi~g to the sequencing and coding
technique just described in connectiQn with Figs. 3 through 5.
This circuit includes a magnitude comparator 31, two timers 33~
35 and a mode-indicating shift xegister 37. The magnitude com-
. ¦parator 31 compares the inverse of the channel active signals
B, C, and D provided by the mode-indicating shift register 37 to
¦the inverse of the port DTR signals (master~ or the port DCD
signals (slave~ . The channel. activ~ signals are supplied by
tr~nslating the shit register output code in a decoder 36~ The
inputs to the magnitude comparator 31 are labeled collcctivcly X
and Y, r pectiyely.
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The relation o X and Y indicate~s the nature of thechanne~ reconfiguration required. For example, if it ls
necessary to go from mode 1 to mode 5, the input ABCD to X
will be 0111 whereas the inputs ABCD at Y will be 0001. In
this case, X > Y, the shift register is automatically loaded with
the mode 3 indication. The load mode 3 signal is delayed by the
timer 35 which times out an interval as discussed above with
respect to Fig. 4 and 5. On the other hand, if X is less than Y
the indication is that a channel needs to be deleted. In this
; case, the shift register 37 is merely stepped to the next mode
code, after a suitable delay provided by the timer 33. I~ after
one step, the comparison X < Y is still true, the shift register
~1 37 will be again stepped to attain the next mode. When X finally
equals Y, an idle state exists wherein the~mode requeste~ is
¦equal to ~he active channel configuration (channel actiYe mode)~
!Of course, it will be appreciated that in this discussion, the
limportance of the comparison function i8 to determine whether
,channels need ~ be added or deleted Various logical schemes and
~conventions may be derived to provide this indication from the
pertinent channel codes without departing from the scope of the
invention.
¦- Fig. 7 illustrates in detail a ~ircui~ according to the
- I preferred embodiment of the invention which may operate as
¦ either the master or slave reconfiguration control. The master/
¦slave selection is made by a control strap which controls multi-
plexers, as will be discussed below.
¦ }n the master mode, the control signals, for example the
~TR signals from four ports 16t are prese~ted to a four b~t l~tch
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39. ~ c contents of this latch 39 are transmitted by a multi- ¦
plexer 41 to least significant port control logic 43 and then to
a comparator 45. The comparator compares the channel active
signals at input X to the ouptut of the least significant port
control lo~ic 43 and provides output control signals to a shift
timer 47 or a load timer 49. The shift timer and load timer 49
are connected through a multiplexer 51 to control a mode-
indicati.ng shift register 53. The equivalent X ~ Y or i~le output
of the comparator 45 i.s fed back to latch control logic 55 which
controls operation of the latch 39~
A control strap 57 selects betw~!en the master and sla~e
modes of operation of the circuit. In the! mastex mode of opera-
tion, the multiplexer 41 is caused tol~trarlsfer the output of tho
four-bit latch 39 to the least significant: port ~ontrol logic 43.
In the slave mode, ~he multiplexer 41 gate!s the DCD signals from
a bus to the least significant porl: control logic 43. The
control strap also causes the multiplexer 51 to gate the 200 ms
output of the shift timer 47 and the 200 ms output of the load
timer 49 to the mode shift register 53 in the ~aster mode. In
the slave mode, the lO0 ms outputs o~ the load and shift timers arc¦
selected by the multiplexer 51. The multiplexers unction as
gating switches and are well-known in the art~ .
In the mastex mode, the latch 39 is normally sampled at
a high rate. Howe~er, when a change in c~ndition is detected such
that the idle output o the comparator 45 no longer indicates that
X = Y, the latch control logic 55 cause~ khe latch 39 to hold or
latc~ the new requested mode ndicatlon.
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¦ The latch control logi~ 55 incllldes an AND gat:e S9, a
¦ NAND gate 61 and a delay, ~lip-flop 63. The AND gate S'' receivP3
an input indicating X ~ Y and an input indicating the master mode
¦ has been selected. Assuming these conditJ.ons are satisl.ied the
I output of the AND gate 59 is high as is the output of the normally
¦ reset delay flip-flop 63. In this event, the NAND gate 61
¦ produces a low output which indicates the latch condition and
¦ disables the sample clock via an AND gate 65. As may be noted,
¦ when X ~ Y or the mas~ex mode is not sele$ted, the output of the
¦ N~ND gate`61 will be high indicating the ~ample mode for the
I latch 39.
The delay flip-flop 63 is provicled to assume proper
operation when mode three is selected. In this event, ADTR will
I change (go low as here discussed) t:o signcll the slave modem.
¦ To prevent the comparator from erroneously detecting inequality
l andllatching the lQw ADTR signal, t:he deldy ~lip-flop responds
to a~ load command to inhibit latching unti.l ADTR resumes its
original (high) st~te. As shown in ~ig. 7, this operation i~
accomplished by clocking the delay flip-~lop at the baud rate,
supplying its D input with the load command and its reset input
j with the ADTR signal~ .
The latch 39 thus functions to prevent any interxupts
! or change in inputs until the port-con~iguring circuit has
¦completely processed previous changes. In this manner, control
¦!siynals may be generated.and sent to the slave and completed
¦~before new interrupts ~or new port allocation reqeusts are honore~.
Il . ' ' ' ` . .
Il !
3~
,,
The code selected by the multiplexer 41 i3 thcn tran~-
mitted ~o the least significant port control logi~ 43 wherein the
least significant channel is given priority. The least signii-
c~nt zhannel present will force the more significant channel
information to the active state, e~sential.ly filling in thc
"don't care" states in Table I. Channel P. information is not
af~ected by this ~ircuit. The operation and str.ucture of the
least slgnificant loigc gating is represented by the following
Table II.
T~BLE II
~93~ _ ~ ; Dn~ 150 ~r ~3MP)~
A B C D A B C D
¦ A X X 0 ~ A 0 0 0
¦ . A X 0 1 . A 0 \ 0 1
¦ A 0 ~1 1 . A 0
¦ . A 1 1 1 ; A 1 1 . 1
I .' ,.
*NOTE: NEGATIVE ~OGIC I
As mentioned earlier, the ~agnitude comparator~ which
!may be a standard digital comparator provides X > Y, X < Y and
IX = Y outputs. ~hese indicate respe~tively that a channel mode
requested is that which is currently configured. The idle or
! X = Y output of the comparator 45 is retur~ed to control the latch
¦lcontrol logic 55.` The condition X ~ Y initiates the latch opera- .
¦,tion. The X ~ Y output goes to the ~hift timer 47, which providos
i a shift command to the mode shift register 53 after a time dura.
tion s~l~ct~d by the multipl~xer 51 a~ explain~d abov~. Thc
I - 20 - ~
I ~
I , .. . ..
~3~ 3
.,`
X ~ Y load indication triggers a load timer 49 which cause~ the
mvde 3 code to be loaded into the shift reglstex 53 aftcr the
period of time selected by the multiplexer 51. The shift timer
and load timer may both be conventional counter circuits.
Upon receiving a shift command from the shift timer 47,
the shift register rapidly shifts through its output states until
equality is detected by the comparator 45. This function is
represented logically in Fig. 7 by an AND gate 50, which in
xesponse to the shift signal from the tlming apparatus 47 gates
a clock to ~he shift register until the IDLE output is produced
by the comparator 45. If, upon loading mode 3, equ~lity does not
resultO the X < Y output of the comparator 45 iB activated,
instituting the shift sequence just described.
. When not in the shift or load state3, the mode shi~t
register 53 simply holds the mode :indication at its outpu~s. The
mode indication may be applied to a suitable strap to select
either mode 2 ~r mode 4.
Thus, in overall operation in the master mode, when a
new channel configuration is requested, the comparator 45 outputs
either a shift or a load comm2nd. These commands are suitably
delayed by the timers 47, 49. During thi~ delay, signals are
sent across the channel to the slave mode~0 In particular,
channel drops are detected from the output of the four:~it latch
39 -and the appropriate dxop code sent. AE~paratus for sending the
drop code is fed with the latch output vict lines 40, and i~ woll-
kn~wn in thc art. When it 19 nece~s-ry t load rode 3, tho code
-21- ' `
Il . . ,
~i 3,~
sent to the slave modem is sent upon detec~tion o the load indi-
cation rom ~he comparator 45 on line 42. At the end of the
timing cycle as determin~d by the ti~exs 47, 49 the proper shift
or load command is sent to the shift register 53. The mode of
the shift reglster is then returned to the comparator 4S to
determine whether another change in the shift register conten~ is
I re~uired or whether a~ equal condition has now been achieved.
In the slave configuration, the latch,39 is switched
out by the multiplexer 41. The basic circuit operation is still
the same with the exception th~t the DCD signals are presented to
the least significant bit logic and the comparator 45. The tîme~
multiplexer 51 selectes a sho~ter ~ration and a DCD com~and must
¦be present fox the duration of the timing cy¢le in order for tho
¦ circuit to react.
¦ According to the invention, other methods may be usod
¦to synchronize the port configuration switching at physically
¦separated modem sites. One'such method is to provide,an FSK
¦ (frequency shift keyed) secondary channel or a totally indepen- ,
dent data path for transmitting the synchronizing information. '
Such a channel path can be provided internally to the data set '
or by exter~al equipment. '
In another method the modem user can synchronize two
, ¦systems by requiring port configuratlon simultaneously at pre-
viously determined times. For example, at the end of the day the
lapparatus cooperating with each physically separate modem ~uch
I.as a computer or data terminal (DTE), may assign a partlcular
¦ch~nncl for a specific transfer of data. Since the mod2m~
controlling apparatus at each site has a master alock 7
. ' ,~
, , - 22-' 1
!
.53
.~. I
synchronization in accordance with these master clocks is a
simple matter. Because of the synchronized master clocks at
¦ each modem site, ther~ is no need for signalling between the two
¦ data setsO The data sets are each strapped to follow the requcst
¦ presented at the data terminal equipment (DTE) interface. Since
¦each modem is under master control, this ~nychronizing tech~ique
is called master/master~ By operating in the master/master mode,
a user can effect direct softwar~ control of the port configura~
tion by ~upplying his own synchronization codes.
As is apparent from the above discussion, many modifi-
cations and alterations may be made in the above described
¦ prefe; ~ed embodiment without departing from the scope and ~pirit
¦ of the lnvention. Therefore it is to be understood that, within
the scope of the appended claims, t:he invention may be practiced
¦~other thar as specifically described hereln.
: I . , , '~ ,
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