Note: Descriptions are shown in the official language in which they were submitted.
~3f~;~9~ ~:
BACKGROUND OF THE INVFNTION
~ `
This ;nvention relates to MOS~T devices and _ ;
more specifically rclates to a novel struc~ure for a
~IOS~ET dcvice which permits i* to be used in high power
applications with a relatively high reverse voltage and
with an exceptionally low on-resistance. T}-e major ad-
vantage of the bipolar transistor over the MOSFET
transistor is that t~e bipolar transistor has a very
low on-resistance per unit conductive area. The MOSPET
*ransistor has numerous advantages over `the bipolar
transistor including very high switching speed, very
high gain and lack of the secondary breakdown character-
istics e~hibited by a minority carrier devlce. However,
because the MOSFET transistor has high on-resistance,
its use in higll power s~ri*ching applications has been
limited.
BRI~P DESCRIPTION OP ~HE INVENTION
The present inven*ion provides a novel high
po~er MOSFET device which has a low forward resistance
so that the device b~ecomes more competltive with bipolar
devices in a s~itching type application wllile retaining
all of the numerous advan*ages of the MOSFET over the
bipolar device. In par*icular, with the present
invention, the ~or~ard resistance per unit area of the ~-
. .
L3~iZ~
- 3 -
device has been reduced by at least a Eactor o two,
compared to t~e limiting resistance per unit area
previously existing in a MOS~ET-type device.
In one embodiment of the invention, two
sources are placed on the same surface of a sernicon- -
ductor wafer and are laterally spaced from one ano~her.
A gate electrode, depos~ted on a conventional gate
oxide, is disposed be-twecn the sources. Two p-type
conduc*ion channels are disposed beneath the gate and
are spaced -~rom one anot~er by an n-type bulk region.
Current ~rom each source can flow through its respective-
channel (after the creation of the inversion layer
defining the channel~, so that majority carrier con-
duction can flow through the bulk region and across
the wafer or chlp to the drain electrode. The drain
electrode may be on the opposite surface of the ~aer
or on a laterally displaced surface region ~rom the source
electrodes. Th~s configuration is made using the desirable
manufacturing techniques of the D-~IOS device~ which
permits precise allgr~ent of the various electrodes and
channels and permlts use of extremely small channel
lengths. Whlle the above con~iguration device may have
been previously described ~or a ~IOSFET signal-type device,
the structure is not that of the commonly used signal
MOSFET.
The device is basically formed in an n(-~ sub-
strate which has the relatively h;gh resisti~ity which is
.
,~: ,' '
36;~:91
- 4
necessary to obtain the desired reverse ~oltage capability
o~ the device. For example, for a 400 volt device, the
n~-~ region will have a resistivity of about 20 ohm-
centîmeters. However, this same necessary high
resistivity characteristIc has caused the on-resistance
of -the ~IOSFET devlce, ~rhen used as a po~er switch, to
be relatively high,
In accordance with t~e present invention, it
has been found that in the upper por~ion of the central
bulk region ~o which the t~o inversion layers feed
current in the path to the drain electrode, the central
region immediately beneath the gate oxide can be a
relatively low resistivit~ material formed, for example,
by an nC+l diffusion in that channel reglon3 ~iithout
affecting the reverse voItage characteristics of the
device.
More specifically, and in accordance ~rith the
invent~on, this co~mon~channel l~ili have an upper
portion beneath the gate oxide and a lower bulk portion
extending toward the drain electrode. The lo~er portion
has the high resistivity desired to produce high reverse
voltage ability-, and will have a depth dependent on the
~.
desired reverse voltage for the device. Thus, for a
400 volt devIce, the lower n~-l region may have a depth
o about 35 mierons, wllile for a 90 volt device it ~ill
have a depth of about ~ microns. Other deptlls ~ill be
selected, depending on the desired reverse Yolta~e o:E the
- 5 - -
device to provide the necessary thicker depletion reglon
required to prevent punch-through during reverse voltage
conditions. The upper portion of the common channel is
made highly conductive (n~) to a depth of from about 3 to
about 6 microns. It has been found that this does not
interfera with the reverse voltage withstand a~ility
of the de~ice. ~owever, it decreases the on-resistance
per unit area of the deviice by more than a factor of two.
The result~ng device becomes competitive with conventional
high power blpolar switching devices since it retains
all of the advantages of khe ~IOSFET deYice over the
bipolar device but now has the relatively low fon~ard
resistance which was the major characterizing advantage
of the bipolar device.
The present in~ention also provides a novel
high po~er ~IOSFET device with low forward resistance -
where, however, a very high packing density is available
and whLch can be made with relatively simple masks. The
device further has relatively low capacitanc~.
Each o-f the individual spaced source reg;ons,
in accordance with a preferred embodiment o *he invention,
IS polygonal in coniguration and is preferably hexagonal
to ensure a constank spacing along the major lengths
of the sources disposed over the surface of tlle ~ody.
An exkremely large number o small hexagonal source
elements may be formed in the sa~e sur-~ace of the semi-
conductor body for a given device. By way of example,
6,600 hexagonal source regions can ~e ormed in a ch;p area
. - .
... .
. ` ' : ' . ' : : , ' .' " . :' ,: ' , : :,,:
~316Z9~
- 6 -
having a dimension of about 100 by 140 m;ls to produce
an effective channel width o about 22,000 rnils, thus
permitting very high current cap~city or the device.
The space between the adjacent sources may
contain a polysilicon gate or any other gate structure
where the gate structure i:s conltacted over the surace
of the device by- elongated gate contact fingers wh;ch
ensure good contact over the full surface of the device.
Each of the polygonal source regions is con-
tacted by a uniform conductire layer which engages thexndi~idual polygonal sources through openings in an
insulation layer covering the source regions, which
openings can be formed by conventional D-MOS photolitho-
graphic techniques. A source pad connection region is
then provided for the source conductor and a gate pad
connection region is provided for the elongated gate
fingers and a drain connection region is made to the
reverse surface of the semiconductor device.
~ plurality o~ such devices can be for3ned from
a single semiconductor wa~er and the individual ele3ne3lts
can be separated ~rom one another ~y- scriblng or any
other suitable 3nethod.
In accordance wit~ another feature of the
present invent~on, the p-type region ~Yhich deines the
channel beneath the gate oxide has a relatively dceply
di~fused portion beneath the source so that the p-type
diffusion region will have a lar~e radius of curvature
.
: ~, . . .
- 7 -
in thc n~-) epitaxial layer forming the body of the
device. This deeper diffusion or deeper junction has
been found to improve the voltage gradient at the edge
of ~he device and thus permIts the use of the device with
5 h;gher reverse voltages, '~
B~IEF DESCRIPTION OF THE DRAWINGS
Figure 1 is a plan view of a hi~h po~er MOSFET
chip which incorporates the present invention and
particularly illustrates the metalizing pattèrns o
the two sources and the gate.
Figure 2 is a cross-sectional view of Figure 1
taken across the section line 2-2 in Figure 1.
Figure 3 ~s a cross-sectional vlew similar to
Figure 2 sho~Ying the initial step in the process of
manufacture of the~chip of ~igures 1 and 2 and parti-
cularly shows the P(~l contact implant and diffusion
step.
Figure 4 shows the second step in the manu-
facturing process and shows the n(~ implant and dif~
fusion step.
Figure 5 sho-~s a further step in tha process
of manu-~acture of the chip of Figures 1 and 2 and shows
the channel implant and diffuslon step.
'
L3~%~
.. .
Figure 6 sho~s a further step in tlle process
of manuacture and illustrates the source predeposition
and diffusion step. This preeedes the last step in which
the gate oxide is cut for the metalization step which
produces th~ device of Figure 2.
Figure 7 is a plan view of the metaliz;ng
pattern of a second em~odiment 'of the lnvention.
Figure ~ is a cross-sectional -vie-~ of ~igure 7
taken across the section line 8-8 in Figure 7.
Figure ~a is a view sim;lar to F;gure 2 and
shows a modi~ied source contact configura*ion.
Figure 9 shows the shape of forward-current
charac~erist;cs of a device like that of F;gure 2 where
the region 40 beneath the oxide is n(-?.
Figure 10 shol~s the shape of the characteristic
o a de~ice identical to that o~ ~igure 2 where the
region 40 has hlgh n(+l conductivity.
Figure 11 is a plan view of a completed element
on a semiconductor wafer prior -to the separation of the
element away ~rom the remainder of the wafer.
Pigure 12 is an enlarged detail o the gate
pad to illustrate the relationship of the gate contact
and the source polygons in the region of the gate pad.
P;gure 13 IS a detailed plan view o a small
portion of the source region during one stage o;~ the
manufacturing process of the device.
.
": :
- 9
Figure 14 is a cross-sectional view of Figure 3
taken across the section line 14-14 in ~igure 13.
Figure 15 is similar to Figure 14 and shows the
addition of a polysilicon gate~ a source electrode means --
and drain electrode to the wa~er.
DETAILFD DESCRIPTION OF TIIE DRAWINGS
A first embodiment of the novel MOSPET deviceO e the present invention is shown in ~igures 1 and 2
which show a chip of monocrystalline silicon 20 ~or
some other suitable material2, with the device electrodes
~ollowing the serpentine path 21 best shown in ~igure 1
in order to increase the current-carrying area of the
device. Othe,r geome~ries could be used. The device
illustrated has a reverse voltage of about 400 volts
and an on-resistance less than about 0.4 ohm with a
channel width of 50 centimeters. Devices having reverse
voltages of from 90 to 400 volts have been made. The
400 volt devices have car~ied pulse currents of 30
amperes. The 90 volt devices have had for~ard on-
resistances of about 0.1 ohm with a channel ~idth of50 centimeters and have carried pulse currents up to
about 100 amperes. Higher and lower voltage devices
can also be made Wit]l varying channel widths.
Presently kno~n ~IOSFET devices have much highsr
on-resistances than the above. ~'or example, a 400 volt
~OSFET compara~le to that described below but made with
1'' , ' ' ' ,: . . :
``` ~L13~
- 10 -
prior art techniques would normally have an on-resistance
much greater than abou~ 1.5 ohms, as compared to an on-
resistance less than about ~.4 ohm in a device made ac-
cording to this invention. Moreover~ the MOSFET switching
device o~ the present invention will exhibi~ all of the
desirable advantages o the MOS~`ET device, since it operates
as a majority carrier device. Tllese advantages ;nclude high
switching speed, lligh gain and avoidance of the secondary
breakdown characteristics which exist in m;nority carrier
devices.
The device o-f Figures 1 and 2 has two source
electrodes 22 and 23 which are separated by a metalized
gate electrode 24 which is fixed to but spaced from the
semiconductor de~ice sur~ace by a silicon dioxide layer
25. The serpentine path followed by gate oxide 24 has
a length o 50 centimete~rs and has 667 undulations, but
is shown more simply in Figure 1. Oth~r channel widths
can be used. Source electrodes 22 and 23 can be later-
ally extended as shown to serve as field plates to help
spread the depletion region created during reverse
voltage conditions. Eac~l of source electrodes 22 and
23 supply current to a common drain electrode 26 which
is fixed to the bottom o the wa-fer. The relative
dimensions for the device, particularly in thickness,
have been grossly exaggerated in Figure 2 for purposes
o$ clarity. The s;licon chip or wafer 20 is formea on
an n~) substrate which may have a thickness o-f about
14 mils. An n(-~ epitaxial layer is deposited on
3~
su~strate 20 and will have a ~hickness and resistivity
depending on the desired reverse voltage. All junctions
are formed in this epitaxial layer which can have a
relatively high resistivity. In the embodiment dis-
closed, the epitaxial layer has a thickness of about 35microns and a resistivity o about 20 ohm-centimeters.
~or a 90 volt device~ epitaxial layer 20 ~ould be about
10 microns thick and would have a resistivity of a~out
2.5 oh~-centimeters. A channel width o 5Q centimeters
is also used ~o provIde the desired current carrying
capacity for the device.
In a preerred embodiment o~ the invention J
there is an elongated serpentine P(+l conductivity
region beneath each of the source electrodes 22 and 23
which thus extends around the serpentine path shown in
Figure 1. These P~l regions are sho~n in Figure 2 as
the p~) regions 30 and 31~ respectively, and are
similar to those of the prior art except that the
maximum P~i reg~on depth is greatly exaggerated in
order to form a large radius of curvatur-e. This allows
the device to withstand higher reverse voltages. By
ay of example, t~e depth of re~ions 30 and 31 is
preferably about 4 microns at the dimension X in Figur~ ;
2 and about 3 microns at the dimension Y in Figure 2.
By using D-~IOS abrication techniques~ two
n~) regions 32 and 33 are formed beneath source elec-
trodes 22 and 23, respectively, and define, with the
~ ~ ~ 3~%~
- 12 -
p(-~) regions 3~ and 31, n-type channel rcgions 34 and
35, respectively. Channel regions 34 and 35 are dis-
posed beneath the gate oxide 25 and can be ;nverted by
the appropriate application o a biasing signal to the
gate 24 in order to permit conduction fro3n the sou~ce
22 and the source ~3 through the inversion layers into
the central region disposed beneath the gate 24 and
then to tlle drain electrode 26. Channels 34 and 35 may
each have a length o~ a~out 1 micron.
It has previously been thought necessary that
the central n(-l region between channels 34 and 35 (and
between p(~) regions 30 and 31~ should have a high
resistivity in order to permit the de~ice to withstand
high reverse voltages. However, the relatively high
resistIvity n(-) material is also a significant con-
tributing factor to the high for~Yard on-resistance of
the device.
In accordance with the significant feature of ~:
the present invention, a signi~icant portion o:E this
central conducting region is ~lade relatively highly
conductive and consists o~ an n(~l region 40 disposed
immediately beneath the gate oxide 25. The n(~ region
40 has a depth of about 4 microns and could range from
about 3 microns to about 6 microns. While its exact
conductivity is not kno~n, and varles ~ith depth, it is
high relative to the n( ) region beneath it. More
particularly, leglcn 40 has a high conductivity ~hich
,, ~
36;2~
- 13 -
~ould be determined by a total ion implanted dose o-E
from about 1 x 10l2 to 1 x 1014 phosphorus atoms/cm2
at 50 kV followed by a dif-fusion drive at from 1150C
to 1250C for rom 30 mînutes to 24Q minutes. It has
been found that by making this reg;on 4Q relatively
highly conductive nC~ material through a diffusion or
other operation, the device character;stics are
s;gn;ficantly improved and the forward on-resistance
o~ the device is reduced by a -factor greater than t~o.
Moreover, it has been ~ound that the provision of the
high conductivity region 40 does not interfere with
the reverse voltage characteristics of the device.
Accordingly, by making the region beneath the gate oxide
25 and between channels 34 and 35 more highly conductive,
the for~ard on-resistance of the ultimate high po~er~
switching device has been significantly reduced and the
~OSFET device becomes far more competitlve ~ith an
equivalent junc*ion-type device while still retaining
all of the advan~ages o$ the MOSFET majority carrler
operation.
In the above description of Figures 1 and 2,
it has been assumed that the conduction channels 34
and 35 are o~ P(~l material and are, accordingly, inverted
to an n-typ~ conductivity to provide a majority carrier
conduction channel from sources 22 and 23 to the central
region 40 upon the applicat;on of an appropriate gate
voltage. Clearly, ho~ever~ all of these conductivity
... .
, - - , ::, . ;: , :: ,, ; : ;:
3629
- 14 -
types could be reversed so that the device could work as a '
p-cllanncl clevice rather than an n-channel de~ice as
disclosed.
One process by which the device oE Figures 1 ,
and 2 could be constructed is shown in Figures 3 to 6.
Reerring to ~igure 3, the base wafer 20 is shol~n as an
n(+) material having an n(,-~ epitaxially deposited
region on top thereo. ~ thick oxicle layer 50 is
formed on waEer 20 and windows 51 and 52 are opened
10 therein. The open windows 51 and 52 are exposed ko a ;,~
beam of boron atoms in an ion implanting apparatus to
form p(~ regions. Thereafter the implanted boron
atoms are caused to di-~use deeper into the waEer to
form the rounded pt+~ concentration region shown in ~,
Pigure 3 which might have a depth of about 4 microns.
During this diffusion operation, shallow oxide layers
53 and 54 grow over th~ windows 51 and 52.
~s is next sho~n in Figure 4, windows 61 and
62 are cut in the oxide layer 5Q and an n(+) implant takes
place to implant the n(,+) regions 63 and 64 into the
(-l epitaxial layer. This n(~l implantation can
be carried out with a phosphorus beam. Thereafter~ the
implanted reglons are subjected to a di-ffusion step to ~ -
cause the regions 63 and 64 to expand and deepen to a
depth of a~out 3-1/2 microns with a concentration
determined by an implantation dose of l x 1012 to ~ -
- l x 1014 phosp]lorus atoms/cm2 ollowed by a drive for
1136Z9~ ~
30 m;nutes to 4 hours at from 1150C to 1250C. As will -
be later seen, regions 63 and G4 produce the novel n(-~)
region which substantially reduces the on-resistance
of the device.
It should be noted that the n~) regions 63
and 6~ could, i desired, be epitaxially deposited and
need not be dif~used. Similarly, the resulting device
being described herein could be manu-Eactured by any
desired process as would be apparent to those skilled
in the art.
The next step in the process is shown in
Figure 5 and is the channel implantation and diffusion
step in which the P(+l regions 71 and 72 are formed
through~the same windows 61 and 62 that were used for the
n(+~ implantation for regions 63 and 64. The P~-~?
regions 71 and 72 are formed by implanting with a boron
beam to a dose o about 5 ~ 1013 to 5 x 1014 atomslcm2
ollowed by a diffusion drive for 30 to 120 minutes at
1150C to 1250C.
Thereafter, and as shown in ~igure 6, steps
are carried out for the source predeposition and the
difusion of the source regions 32 and 33. This is
carried out by a conventional and non-critical phosphorus
difusion step where the diffusion proceeds t]lroug]l the
windows 61 and 62 so that the source regions 32 and 33 are
automatically aligned relative to thc other preformed
.' ~.
L3~
- 16 -
regions. Thus, the wa~er is placed in a furnace and
exposed ~o POC13 suspended in a carrier gas for from 10
minutes to 50 minutes at a kemperature of from 850C to
1000.
~Yhen this step is completed, the basic ~:
junction configuration required in Figure 2 is formed
with short p~+~ regions disposed beneath the oxide 50
to serve as the conducting channel for the ultimately
constructed device and with an n(+) region filllng the
area bet~e2n the channels 34 and 35 and between p~
regions 30 and 31. The manufacturing process then ;~
cont;nues from the step of Figure 6 to the device shown
- in Pigure 2 wherein the oxide surfaces on top of the
chip are suitably stripped and the metalizing patterns
for contacts 22 ? 23 and 24 are formed to establish
electrical contacts to the de~ice. The drain contact
26 is applied to the device in a subsequent metaliz;ng
operation. Thereafter, the entire device may be appro-
priately coated with a suitable passivation coating and
~.
~ire leads are connected to the source electrodes 22
and 23 and the gate 24, The device is then mounted
within a suitable protective housing, witll the drain
electrode fixed to the housing or other conductive
support l~hich serves as a drain connection.
The device sho~n in Figures 1 and 2 utilizes
a serpentine path for each of the source regions and
gate regions and a drain on the surface of the ~afer
Z~
- 17 -
opposite *o the source electrodes. Other configurations
can be used. Figures 7 and 8 illustrate a planar con-
figuration which is a simple rectangular arrangement
having a ring-shaped gate 80 ~hich is disposed between
S a first source electrode 81 of ring shape and a central
source 82. The device as shown in Figure 8 is contained
witllin a base ~af2r of p( ) monocrystalline silicon 83
~hich may have a buried n~l region 84 to reduce the
lateral resistanca of the various current paths of the
device leading to the laterally displaced drain
electrode 85 whlch surrounds source 81.
A ring-shaped n(+) region 86 is formed within
the device as sho~n in ~igure 8 and, in accordance with
the present invention, the ring-shaped region 86 is o~
much higher conductivity than the n(-~ epitaxially deposited
region 87 which contains all of the junctions o~ the device.
The ring shaped region 86 extends from the reglon beneath
the gate oxide 88 and adjoins the ends o-f the t~o con-
ducting channels formed between the ring-shaped p(~
region 89 and the central p~ region 91 disposed ~eneath
the ring-shaped source 81 and central source 82 9
respectively.
~ It ~i11 also be noted in Figure 8 that the ~ ;
outer periphery 90 of the p(~) ring 89 has a large
radius to assist the device in ~ithstanding high reverse
voltages.
~3~
- 18 -
An n~+) region 95 in Figure 8 is provided to
ensure good contact to drain electrode 85. Drain
electrode 85 is widely laterally spaced from source 81
(by greater than about 90 microns~ The drain con*act
85 is surrounded by a PC~ isolation dif:fusion 96 to
isolate ~he device from other devices on the same chip
or l~afer.
In the arrangement of ~igure 8, like that of Figure 2,
current flow from source 81 and 82 goes through the width
of epitaxial region 87, through the region 86. The
cllrrent then flows laterally outward and then up to the
drain contact 85. As in the embodiment of ~igure 2,
device resistance is greatly reduced by the relatively
highly conductive region 86.
In carrying out the a~ove invention, it .
should be noted that any type of contact material can
be used to make the source and gate contacts. By way
of example, aluminum could be used for the source
electrodes while a polysilicon material can be used for
the conductive gate 80 in ~igure 8 or the conductive
gate 24 in ~i~ure 2.
Nu~erous other geometries can be used to make
the device of the învention~ including a plul-ality of
pairs of straight, parallel source elements with
respectivel~ interposed gates and the like.
9 ~ 3~%~
- 19 -
The source electrodes 22 and 23 have been
sho~n as separate electrodes which can be connected to
separate leads. Clearly, the sources 22 and 23 could
be directly connected as shown in Figure 8a where
compollents s;.milar to those of ~igurc 2 have been given
similar identiying numerals; In ~igure 8a, hol~ever,
the gate electrode is a polysilicon layer 101 ~in place
of aluminum~ deposited atop gate oxide 25. The gate 25
is then covered Wit}l oxide layer 102 and a conductive
10 layer 103 connects the two sources 22 and 23 together
to form a single source conductor wh;ch is insulated
from gate 101. Connection is made to the gate at some
sultabl.e edge portion o~ the ~afer.
Figures 9 and 10 show the shape of measured
curvas wh;ch demonstrate~ the reduction in for~Yard
: resistance when the region 40 is made highly conductive
~; (n~). In Figure ~, the devlce tested had a region 40
which had the n~-) resistivity oE the apitaxial region.
Thus~ the forward resistance is characteristicàlly high
~0 at di~ferent gate biases as sho~Yn in ~igure ~.
In the device of the invention ~Yhere region 40
is of n(~) conductivity,: there is a dramatic decrease
in the on-resistAnce as sho~n in Pigure 10 -for all gate
voltages before velocity saturation o the electrons
occurs.
, :
~3~
- 20 -
I'he polygon configuration of the source regions
o the present invention is best shown in Figures 13, 14
and 15 wIIich are first described.
Referring irst to Figures 13 and 14, t}Ie de~ice
is shown prior to the application o:E th~ gate, source and
drain electrodes. The manufacturing process can be of
any desired type including the D-~IOS fabr;cation techniques
and ion implantation techniques previously described
for the formation of the junction and placement o the
electrodes in the most advantageous way.
The device IS described as an N channel
enhancement type device. It will be apparent that
the in~ention will also apply to P channel devices and
to depletion mode devices.
The devIce of Figures 13 and 14 has a plurality
o~ polygonal source regions on one sur~ace of the device~
where thes_ polygonal regions are preferably hexagonal
in shape. Other shapes such as squares could have been
used but the hexagonal shape provides better uniformity
of spacing between adjacent source region peri~eters.
In Figures 13 and 14, the hexagonal source
regions are formed in a ~asic semiconductor body or
wafer which can be an N type wafer 120 of monocrystalline
silicon which has a thIn N~-) epitaxial region 121 deposited
thereon as ~est s~Iown in ~igure 14. All junctions are
formed in epitaxial region 121. By using suitable
masks, a plurali-ty of P type regions such as regions 122
~3~
- 21 -
and 123 in Figures 13 and 14 are formed in one surface of
the semiconductor wafer region 121, where these regions
are generally polygonal in configuration and, preferably~
are hexagonal.
A very large number of SUC]I polygonal reg;ons
are formed. For example, in a device having a surface
dimensions of 100 by 14~ mils, approximately 6600 poly-
gonal regions are ormed to produce a ~otal channel
width of about 22,000 mils. Each of the polygonal regions
may have a ~idth measured perpendicular to t~o opposing
sides of khe polygon o about 1 mil or less. The regions
are spaced from one another by a distance of about 0.6
mil when measured perpendicularly bet~een the adjacent
straight sides of adjacent polygonal regions.
The P+ regions 122 and 123 will have a depth d
which is prcferably about 5 microns to produce a high
and reliable field characteristic. Each of th~ P regions
has an outer~shelf region shown as shalf regions 124 and
125 for P reglons 122 and 123, respectiYely, having a
depth s of about l.S microns. This distance should be
as small as poss;ble to reduce the capacitance of the
deYice. :
Each of ~he polygon regions including polygonal ~`
regions 122 and 123 receive Nt polygonal ring regions
126 and 127, respective]y. Shelves 124 and lZ5 are
located beneath regions 126 and 127, respectively. N~
L13~
- 22 -
regions 126 and 127 coopcrate with a relatively conductive
N~ region 128 which is the N~ region disposed between
adjacent P type polygons to define the various c~lannels
bet~een the source regions and a drain contact ~hich will
be later described.
The hIghly conductive N~ regions 128 are
formed in the manner described
or the precedin~ embodi~ents
and produce a very lo~ forward resistance
for the device.
In Pigures 13 and 14, it will be noted that the
entire surface of the wafer is covered with an oxide
layer or combined conventional oxide and nitride layers
which are produced for the formation of the various
junctions. Thls layer is shown as the insulation layer
130, The insulation layer 130 is provided with polygonal
shaped openings such as openings 131 and 132 immediately
above polygonal regions 122 and 123. Openings 131 and 132
have boundarles overlying the N~ type source rings 126
20 and 127 for the ragions 122 and 123, respectively. The
o~lde strips 130, which remain after the formation of the
polygonal shaped openings, de~ine the gate oxide for the
device.
Electrodes may then be applied to the device
as sho~n in Figure 15. These include a polysilicon
grid ~hich includes polysilicon sections 140, 141 and 142
~hich overlie the oxide sections 130.
,
- 23 - . . .
A silicon dioxide coating ls then deposited .
atop the polysilicon grid 140 shown as coating sections
145, 146 and 147 in Figure 15 which.insulates the poly~
sili.con control electrode and the source electrode which
is subsequently deposlted over the entire upper sur-face
of the wafer. In F;gure 15 the source electrode is sllo~n
as conductive coating 150 which may be of any desired
material, such as aluminum. A drain electrode 151 is
also applied to the device.
The resulting device o~ Figure 15 is an N
channel type de~ice wherein channel regions are formed
between each of the individual sources and the body of
the semiconductor material which ultimately leads to
the drain ele~ctrode 151. Thus, a channel region 160 is `.
formed between the source ring 126, ~rhich is connected
to source elec-trode 150, and the ~+ region 128 which ~:
ultimately leads to the drain electrode 151. Channel
160 is inverted to the N type conductivity upon the
application of a suitable control voltage to the gate 140.
In a similar manner, chann~ls 161 and 162 are ormed
between the source region l26, whic]l is connected to the
conductor 150, and the surrounding N+ region 128 which
leads to the drain 151. Thus, upon application of a
suitable control voltage -to the polysilicon gate (including
finger 141 in Figure 15~ cha~nels 161 and 162 become
conductive to permit majority carrier conduction from .
the source electrode 150. to the drain 151.
~,~,3~?
- 24 -
Each of the sources form parallel conduction
paths wllere, for example, channels 163 and 164 beneath
gate element 142 permit conduction from the source ring
127 and an N type source strip 170 to the Nf region 128
and then to the drain electrode 151.
It is to be noted that Figures 14 and 15 illus-
trate an end P type region 17] which encloses the edge
of the wa~er.
The contact 150 of Figure lS is preferably an
aluminum contact. It ~ill be noted that the contact
region for the contact 150 lies entirely over and in
alignment with the deeper portion of the P type region
122. This is done since it was found that aluminum used
for the electrode 150 might spike through very thin
regions of the P type material. Thus, one feature of
the present invention is to ensure that the contact 150
lies principally over the deeper portions of the P
regions such as P regions 122 and 123. This then permits
the active channel regions defined by the annular
2~ shelves 124 and 125 to be as thin as desired :;n order
to substantially reduce the device capacîtance.
Figure 11 illustrates one completed device
using the polygonal source pattern of Figure 15. The
completed device shown in Figure 11 is contained within
25 the scribe regions 180~ 181, 182 and 183 which enable the
breaking out of a plurality o~ unitary devices each having
a di-nension of 100 by 14Q mils from the body of the wafer.
.~.. . .
: .. : . :. . . .
.. ... , . : . . : :
L3~
- 25 -
The polygonal regions described are contained
in a plurality of columns and rows. By way o:E example,
the dimension A contains 65 columns of polygonal regions -.
and may bs about 83 mils. The dimallsion B may contain
100 rows of polygonal regions and may be about 148
mils. Dim2nsion C, WhiC}l is vdisposed bet~een a source
connec-tion pad 190 and a gate connection pad 19l, may
contain 82 ro~s of polygonal elements.
The source pad 1~0 is a relati~ely heavy
metal sec~ion which is directly connected to the alum;num
source electrode 150 and permits conveniant lead connection
for the sourca.
The gate connection pad 191 is electrically
connectGd to a plurality of extending fingers 192, 193,
lS 194 and 195 which extend symmetrically over the outer
surface of the area contain~ng the ~olygonal regions and
make electrical connection to the polysillcon gate as
~ill be described in connection with Figure 12.
Fina~ly the outer circum~er~nce of the device
contains the P~ deep diffusion ring 171 which may be
connected to a fiald plate 201 sho~n in Figure 11.
Figure 12 S]lOWS a ~ortion o~ the gate pad 191
and tho gate fingars 194 and 195. It is desirable to
make a plurality of contacts to the polysilicon gate in
ordar to reduca the R-C delay constant o-f the device.
The polysilicon gate has a plurality of regions including
regions 210, 211, 212 and the like ~hich extend out-~ardly
~3~
. ~ ;
- 26 -
and receive extensions of t]le gate pad and the gate pad
elements 194 and 195. The polysil;con gate regions may
be left exposed during the formation of the oxide coating
145-1~6-1~7 i.n Figure 15 and are not coated by the source
electrode 50. Note that in Figure 12 the axis 220 is the
axis o:E symmetry 220 which is that shown in Figure 11.
Although the present invention has been
described in connection with a preferred embodi~ent
thereof, many ~ariations and modifications will now become
apparent to those skilled in the art. It is preferredS
therefore, that the present invention be limited not by .
the specific disclosure herein, but only by the appended
claims~
- ' . ' ;
