Note: Descriptions are shown in the official language in which they were submitted.
~13~194
The present invention relates to a hierarchical-
structure plant control system including at least one host
computer and a plurality of sub-loop controllers, and
particularly to backing up the sub-loop controllers by the
host computer.
There has been proposed a system in which a plant
control function of computer is dispersed to a plurality
of microcontrollers, and these microcontrollers are
controlled by a host computer. Such system has a merit
that as compared with other systems using a single,
high-processing-capability computer for performing all the
arithmetic operations, a failure occurrence in the system
will almost damage to local portions only.
One example of this system is disclosed in Japanese
Laid Open No. 143989/1975. In this example, there are
provided a plurality of microcontrollers for the control
of operation terminals and in addition thereto auxiliary
microcontrollers for backing up these controllers. A
newest control information from the microcontroller for
the control of the operation terminals is always stored in
a register within the host computer. If even one of these
microcontrollers breaks down, one of the auxiliary
microcontrollers is selected and the newest control
information stored in the register is transferred to the
~ ,~ F
113719~
selected microcontroller, which then operates to back up
the defective microcontroller.
Thus, a redundant controller provided in the
hierarchical-structure plant control system will increase
the reliability of the system. However, the above system
requires transfer of information until the auxiliary
microcontroller starts backing-up operation, and thus
provides a complicated procedure of starting backing-up,
requiring much time for initiation of operation.
Accordingly, it is an object of the invention to
provide a hierarchical-structure automatic plant control
system having a new backing-up system which requires no
transfer of information upon switching to the backing-up
system.
It is another object of the invention to provide a
hierarchical-structure automatic plant control apparatus
having a few switching elements for the backing-up
operation, and which therefore has a simplified circuit
arrangement, thereby making it inexpensive with high
reliability.
According to the invention, there is provided a
hierarchical-structure plant control system comprising: a
master controller for computing a plurality of control
command signals which are provided respectively correspond-
ing to a plurality of operation terminals of a plant; a
plurality of sub-loop controllers each connected to the
master controller through a system bus, and each of which
is supplied with the corresponding one of said plurality
-- 2 --
1~37194
of control command signals to produce a control output for
controlling the positions of the corresponding one of the
plurality of operation terminals on the basis of stored
control program; a host computer for storing a part of the
control programs for the plurality of sub-loop controllers
and, if one of said plurality of sub-loop controllers
breaks down, producing command which permits the position
of the corresponding operation terminal to change in place
of the broken-down sub-loop controller; a plurality of
analog memories respectively corresponding to said
plurality of sub-loop controllers and connected to said
host computer through a common signal line, each of which
stores a value of a control signal from the corresponding
sub-loop controller upon a first operation mode, and
increases or decreases the stored value in response to the
command from the host computer upon a second operation
mode; and transmitting means for, when one of the
plurality of sub-loop controllers breaks down~
transmitting the failure occurrence information to said
host computer, supplying an output of the analog memory
corresponding to the broken-down sub-loop controller to
the corresponding operation terminal in place of the
output of the broken-down sub-loop controller, and
changing the operating mode of the corresponding analog
memory into the second operation mode.
- 2a -
113~194
The above and other objects may be more apparent from
the following description take in conjunction with the
accompanying drawings in which:
Fig. 1 is a block diagram of the whole arrangement of
one embodiment of the invention;
Fig. 2 is a detailed block diagram of part of Fig. l;
Fig. 3 is a detailed circuit diagram of the block 62
in Fig. 2;
Fig. 4 is a timing chart showing the operation of part
of Fig. 3;
Fig. 5 is a sequence diagram of a specific example of
the wired logic 9 in Fig. 2; and
Fig. 6 is a block diagram showing the function of the
block 91 of Fig. 5.
Fig. 1 is a block diagram of an embodiment of the
invention. For a large scale object to be controlled it
is necessary to parallel control several kinds of process
amounts which are related to each other. A master
controller 2 as shown in Fig. 1 generates a demand signal
for each of the process amounts related to each other.
~ n the other hand, a plurality of sub-loop controllers
3a, 3b, ... 3n as shown are supplied with the demand
signals from the master controller 2 to control for the
respective process amounts. As illustrated, the sub-loop
controllers 3a, 3b, ... 3n serve to control the degree to
which control valves 14a, 14b,....14n open so that the
amounts of flow which amount-of-flow transducers 15a, 15b,
... 15n receive are respectively equal to the values of
-- 3 --
~13715~4
the demand signals supplied from the master control 2.
The number of sub-loops depends on an object to be
controlled, and accordingly the number of sub-loop
controllers is changed in a control system.
A process signal controller 4 receives process signals
necessary for controlling and monitoring an object to be
controlled and performs a signal processing such as
arithmetic operation for correction, and computation of
average value. The detection terminals for process
signals are, for example, a pressure transducer 16, a
temperature transducer 17 and the aforementioned
amount-of-flow transducers 15a, 15b ... 15n.
Either of the master controller, sub-loop controller
and process signal controller is a kind of computer mainly
including a 16-bit large-scale integrated microprocessor,
that is, comprises a central processing unit including the
microprocessor, a memory for storing a program and data,
and an input/output unit. These controllers are connected
to a host computer 1 by a system bus 10.
Analog memories 6a, 6b, .... 6n as shown serve to back
up the sub-loop controllers 3a, 3b ... 3n, and normally
store continuous values of the control signals from the
sub-loop controllers 3a, 3b,.... 3n. If change-over
relays 5a, 5b .... 5n are operated to be in the position
of analog memory side, the outputs of the analog memories
6a, 6b, ... 6n are applied to electro-pneumatic converters
7a, 7b, .... 7n in place of the control signals from the
-- 4 --
1137194
sub-loop controllers 3a, 3b, ... 3n. Since the valves
stored in the analog memories 6a, 6b, ... 6n can be
decreased or increased by operator, manual operation at
the operation terminals can be performed through the
analog memories 6a, 6b, ... 6n. The analog memories 6a,
6b, ... 6n are connected to the host computer 1 by common
signal lines 12 and 13. The host computer 1 is able to
back up the sub-loop controllers 3a, 3b or 3n by using the
analog memories 6a, 6b or 6n.
A selector station 11 as illustrated specifies an
operation mode for each of the analog memories 6a, 6b, ...
6n and in association therewith includes relays for
specifying an input to the change-over relays 5a, 5b, ...
5n. If one of the sub-loop controllers 3a, 3b, ... 3n
breaks down, this failure is detected by the master
controller 2 or the defective sub-loop controller itself,
and transmitted by a wired logic 9. Then, a relay
included in the selector station 11 operates so that the
computer 1 starts the back-up operation.
Before start of back-up operation, since the host
computer 1 stores all the control programs for the
sub-loop controllers 3a, 3b, ... 3n and the analog
memories 6a, 6b, ... 6n also store control results (the
degree to which the control valves open) until switching
is performed, it is unnecessary to perform such data
transfer as has been practised in the conventional system.
.
1137.t~4
Moreover, the host computer 1 is able to supply
increase or decrease command through the same signal lines
even when backing up any one of the sub-loop controllers,
and thus this system has its switching part simplified and
has high reliability with low cost.
The arrangement and operation of the analog memories
will be described below.
Fig. 2 is a more specific diagram of part of the
embodiment of Fig. 1. As shown in Fig. 2, the analog
memory 6a includes a comparator 61, a logic circuit 62, a
çlock oscillator 63, a binary counter 64 and a digital to
analog (D/A) converter 65.
The operation mode of the analog memory 6a is
specified by relays 111, 112 and 113 which the selector
station 11 has. The relay 111 selects the automatic
tracking mode. The relay 111 is actuated to
-- 6 --
~ '
11371~
1 supply an automatic tracking mode command to the logic
circuit 62, and at the same time to permit the change-
over relay 5a to select the line _. Then, the output
of the sub-loop controller 3a is applied to the electro-
pneumatic converter 7a, thus the degree of openingof the controller valve 14a is controlled by the sub-
loop controller 3a. When the automatic tracking mode
command is applied to the logic circuit 62, the output
voltage Eo from the analog memory 6a follows the
input voltage Ei, or the output of the sub-loop cont-
roller 3a. This tracking mode is effected by the
fact that the binary counter 64 counts in accordance
with the output of the comparator 61 which compares
the output Eo and the input voltage Ei. In other words,
if Ei >Eo, the comparator produces "1" level ou~put
during the period of which the binary counter 64 is
supplied at its up-terminal with a pulse in synchronism
with the clock signal from the clock oscillator 63.
On the contrary, if Ei ~ Eo, the comparator 61 produces
"0" output level, during the period of which the pulse
from the logic circuit 62 is applied to the down-terminal
of the binary counter 64. Therefore, the count of
the binary counter 64 is converted to an analog
signal by the D/A converter 65 to tha~ the output E~
of the converter 65 will follow the input Ei. The output
Eo of the analog memory 6a is applied to the sub loop
controller 3a, where the voltage Eo from the analog
memory 6a is compared with the control signal resulting
-
-- 7 --
1137194
1 from the self computation. If the difference is
deviated from a certain value, the analog memory 6a
is decided for its automatic tracking operation to
be abnormal.
The relay 112 specifies the mode of the
host computer. When the relay 112 is actuated, the
relay 111 is deenergized to permit the change-over
relay 5a to switch to the line _. At the same time,
the analog memory 6a stops tracking operation to hold
the value at that time. The logic circuit 62, when
supplied with the mode command from the host computer 1
upon actuation of relay 112, generates a pulse in
accordance with the increase or decrease command from
the host computer 1 through the signal lines 12 and
13 and applies it to the up-input or down-input of
the binary counter 64. Consequently, the analog memory
6a is controlled by the command from the host computer
1 to produce output Eo~ which then controls the control
valve 14a to open.
The relay 113 selects the manual mode.
When supplied with the manual mode command from the
relay 113, the logic circuit 62 applies a pulse to the
up-input or down-input of the binary counter 64 in
response to the on-off operation of an increase
25 contact 114 or decrease contact 115. Thus, the increase
contact 114 and decrease contact 115 are operated ~o
open and close the control valve 14a, respectively.
The logic circuit 62 for such switching of
the modes as described above can be realized with the
circuit arrangement o~ Fig. 3, in which NAND gates Gl,
2 3~ 4~ Gs~ Gfi~ G7 and G8 cOnStitute a
selector. The gates G7 and G8 produce outputs the
level of which depends on the output of the comparator 61
when the level of the automatic tracking mode command from
the relay 111 is "1", the signal levels on the signal
lines 12 and 13 when the host computer mode command from
the relay 112 is "1", and the on-off operation of the
increase contact 114 and decrease contract 115 when the
manual mode command from the relay 113 is "1".
NAND circuits Gg to G12 constitute a synchronizing
circuit. Fig. 4 is a timing chart showing the
input-output relation of the synchronizing circuit. It
will be seen from the chart that if the output level of
G7 is "1" at a rising edge of the clock signal from the
clock oscillator 63, the gate G14 produces an inverted
clock signal which is counted up step by step at its
falling edges by the counter 64. If the output level of
G8 is "1", the gate G20 produces a pulse, which the
counter 64 counts down at its falling edges step by step.
Shown at 67 in Fig. 2 is a switch for changing the
oscillation frequency of the clock oscillator 63. In this
embodiment, 200-Hz clock signal is selected for the
automatic tracking mode, and 20-Hz clock signal for the
host computer mode and manual mode. Since the binary
counter 64 is of 10-bits, about 40
_ g _
. ..
1137194
1 seconds are required to change the output Eo to full
scale in the host computer mode and manual mode.
On the other hand, for automatic tracking mode, the
output Eo follows the input Ei at the rate of about
5 seconds per full scale and thus the automatic tracking
can be performed with little delay.
The logic circuit 62 has a single step
specifying terminal 621 as shown in Fig. 3. If "O"
level is supplied to this terminal 621, the gates G
and G22 are closed to block the input clock pulse.
Under this condition, the outputs of the gates G7 and
G8 are reversed and transmitted to the gates G14 and
G20. Thus, the outputs of the gates G7 and G8 are
counted directly by the binary counter 64. If a circuit
is connected to supply "O" level to the terminal 621
in the manual mode, the output of the analog memory
6a is increased or decreased by one step by one action
of closing and opening the increase contact 114 or
decrease contact 115. In the host computer mode, if
a circuit is connected to supply "O" level to the
terminal 621, the host computer 1 is able to produce
an increase command or decrease command by a pulse
train of its own period.
The switching sequence for backing up will
be described below.
The relays 111, 112 and 113 for selecting
the three kinds of operation modes in the analog
memory 6a as described above are driven by a logic
-- 10 --
1137194
1 circuit as shown in Fig. 5. This logic circuit is
only a part of the wired logic 9 in Fig. 1, relating
to switching of analog memory 6a, and hence the same
logics are used for the other analog memories.
Referring to Fig. 5, numeral 90 represents
a self-examining function which is included in ~he
master controller 2 and which shows that the master
controller 2 is normal. Numeral 91 denotes another
examining function provided in the master controller 2.
This function indicates that the sub-loop controller
3a is abnormal. The sub-controller 3a includes a self-
examining function 92 which shows that the sub-controller
3a is abnormal, and a monitor function 93 for tracking
operation of analog memory 5a. Shown at 94 is a
function for producing output of "normal" when there
are no both "abnormal" outputs from the functions 91
and 92, or when the sub-loop controller is normal.
The selector station 11 has switches for
selecting manual and automatic control of the degree
to which the control valve 15a opens. Numerals 95
and 96 show the conditions in which the switch for
selecting the manual control is turned on and the
switch for selecting the automatic control is turned on,
respectively. Numerals 97, 99, 102, 105 and 108
represent AND logics, 98, 101 and 103. ~R logics, 100
a time release timer, and 104, 106 and 107 N~T logics.
It will be understood from Fig. 5 that
when the following three onditions are satisfied,
', ' ,
i~' ~ . ,
1137194
1 the AND logic 102 selects a host computer mode 202:
a) The sub-loop controller 3a is abnormal.
b) The automatic tracking operation of the
analog memory 6a is normal.
c) The automatic control mode has been selected
in the selector station. The host computer mode 202
continuates until the condition a) or c) is released
from. The relay 112 in the selector station 11 operates
under such condition, where the host computer 1 controls
the control valve 14a by using the analog memory 6a
in place of the sub-loop controller 3a.
When the automatic control mode is selected
but the above condition a) or b) is not satisfied,
the automatic tracking mode 201 is held at all times,
under which the relay 111 is operated. At this time
the control valve 14a is controlled by the output of
the sub-loop controller 6a.
Even in either of the above two modes, once
the condition 95 is satisfied, or manual mode is
selected, the "l"-level input to the OR logic 103
permits the AND logic 105 to produce "l"-level output
and thus the manual mode 203 is held. The relay 113
operates under this condition.
As described above, in the embodiment, the
switching from the automatic tracking mode to the
host computer mode, that is, the initiation of
backing up by the host computer 1, is made only when
the analog memory correctly follows the output of
- 12 -
'' : ,
'
-
113~94
the sub-loop controller. Therefore, upon switching, the
degree to which the control valve opens is not suddenly
changed, and thus smooth switching is performed.
For self-examination of the master controller and
sub-controller as shown at 90 and 92, there are employed
known methods of checking rate of change and upper and
lower limits of the output. The examination of sub-loop
controller by master controller as shown at 91 is
performed as shown in Fig. 6. In the master controller 2,
a control demand consisting of a command signal 21 and a
preceding signal 23 is applied to the sub-loop controller
3a. A subtractor 30 in the sub-loop controller 3a
produces a difference signal representing the difference
between the command signal 21 and a feedback signal from
an amount-of-flow oscillator 15a. The difference signal
is applied to a P.I adjuster 32 where PI operation is
performed to produce a correction signal 33. The
correction signal 33 and the preceding signal 23 from the
master controller 2 are supplied to an adder 34, which
then produces a control output 35. In the master
controller 2, a subtracter 26 produces a signal represent-
ing the difference between the correction signal 33 and
the control output 35. The difference signal from the
subtracter 26 and the signal 23 are supplied to a monitor
24 which monitors whether or not these signals are equal
to each other. If agreement is not achieved, addition
- 13 -
~r~
~ .. ..
11371~
1 by the adder 34 is not performed normally and thus
the operation of the sub-loop controller 3a is examined
to be abnormal.
The blocks 24, 26, 30, 32 and 34 as shown
are logics for executing a program.
In this embodiment, in addition to the self-
examination of computer which is common practice in
the prior art, the sub-loop controller is examined
by the master controller, and thus failure detection
precision is high.
The soft ware of each controller will be
described below.
In this embodiment, the host computer 1,
master controller 2, sub-loop controllers 3a, 3b, 3n,
and process signal controller 4 are all provided with
a common, fixed processing program for operating
elements of No. 1 to No. 22 as shown on Table 1. The
operation by each element is tarbulated on the column
of "Function". The elements of No. 1 to No. 7 perform
logic processing, and those of No. 8 to No. 22 perform
analog processing.
- The control program in each controller is
built up in the form shown on the column of "Table
specification". That is, the control program is
formed of part showing one of the elements of No. 1
to No. 22, and the other part showing an object ~o be
computed (or related connection), set values, upper and
lower limits and so on.
- 14 -
1137194
l The host computer l stores all the control
programs of the sub-loop controllers 3a, 3b, 3n in the
form of "Table specification". If one of the sub-loop
controllers breaks down, the output of the "abnormal"
detection means as described previously is transmitted
to the host computer l, which starts backing-up operation
by initiation of the corresponding control program.
- 15 -
1~3719~
_
XZ XZ ~
U~ U~ o
. U~ . .,~
.
~ C ~ ~ "
~ ~ Z ~ Z
X ~ X,
X~ Z
_, ~ _ :,
D ~ L ~
rt~
-- 16 --
~137~94
_ _
-
O \ O H \ OH H H
~1 ~ \ ~1 ~I C~
Q Z_ X 1~ _ X X H
- _
T ~
E~ P~ ~
O H O
Z ~
:~ ~ L~ t
-- 17 --
11371~4
o ~ o
o
~ ~ ~ o C~ ,
~ V ~ ~ .
~ ~ o o
E~ 11 c~
.____ X H H H H
X ~ 3
~- _
E~ ~
_ _
?~1
_ _ _
_ _
_ _.__.. _
- 18 -
1~371~4
_ ~ O ~ l ~ a~ _
H E~
_ _ . _ ~ _ ~1 ~ O ~1 ~,
~ '' a a ~ a
X X ~-- All V a . . .
_ V ~
_~ X ~ ~ H H H E~ E~
~ - _
r
X ..
_ _
a
' -
1137194
--1--1 O' ~1 0 _
~ E~o~ o ~ ~
_. ~ " " " , ~
, ,, " ~ V o
,_, O ~ c~
C) V
H a ~ H H 0
E~ 3
~ -l 1l ,. .. -,, 1l o
1 1 H H H
~ . _ .
O~\~ O ~ H ~ H
3 ~ ~ X H
;~
._ ~
-- 20 --
1137194
_ _ _
~ ~ o ~ o
,. ..
3 11 :3
U~ X
S 3
.,1 rl
_, ~
_ _
3.~ -
Z U2
_ _
-- 21 --
~13 ~194
_ _
~ C~
X V~ V~ V
C5, ~ Vll C ~, C ~ C
Z Wll ~ 3 3
_ rl ~ _
O ~ H ~ H ~ ~ H ~
~1 ~J :Z ~i t~l Z ~J -1
~ E~
_ ~
.
-- 22 _
1~3~ 4
_ Q ~l? -~ ~ _
~n QO
D ~ n ~ c~
0 ~ n ~ v~ ,
~ Z
_ _
-
Z E~ Z _~o '`O __ ^Z _
~ O H ¢ m ¢ m ¢ m
cd ~ ~. ~t _ ~ ~ .......... ~ ~ ,'
~ L~
Z o
o ~
H ¢
3 ~
o
1137194
_ . _
C) Vll ~ ^ ~ l
11 X " X "
,, X~ X
V \ _~ E~ \ E~ __ _~ _~
\ ~ ~ \ , Z Z U~ ~q
H ~ O U~ ~ O H H ~_ ~_
U2 ::~ C~ , ~ ~ W W L`~ ~ ,
O
~ ~ X
z ~ ¦ H ¢
~3 Z Z
H ~ O
U~ ~:5 ~ ~:
_ .~_,_ _
, _ ~, . . . I . . _.
- 2L _
1~371 94
a~ o ~
~ V ¦ H 11 ~ ~1
~ + ~ ~0 ~ ~
V X (I) O
3 H I W 11 3 X ~`J
~I x E~ N
~_ 11 11 ~, H
--` ~ H H
~::) _, ~ Q ~ _
~ . \ E~ _~ _ ,_ ~ ,_ ~ ~ __ ,_ _~
V \ O H H H ~ X ~_ ~ H ~ ~
~ ~ V V ~ 3 ~ H ~J H
LL~
~ X
I ~,
- P~ V _
_ ~ _
:
- 25 -
i
1137194
_ _
a)
a) a
z ~ a~ o
3 H ~
11 0 ~ o
^I ~ ~ ~ ZZ ~ ~5
C) ~ ^--~ 3 3
^ H ~~4 H ~ O O J~
O ~~ ~ ~ C 5:
O
~ C ~~ ¢ ~ ~ ~ O C~
¢ v~
11 X ~r~ ~1 ~1 ~ ~ ~,
:>~ + 11
~ 11 ~ ^ ^ ~ ~ C)
3 3 ~ ~ 3 3 3 H
V~ O ~
C~ ~: Z
^ ^ O O O
m - ~
_ . = _ . .
\ ~ ~ _ ~ ~ ~ ~
~ \ ~ Z U~ ~ ~ ~ ~ ~ ~
S:\ O H ct: ¢ H ~1 ~ ~C ~1
C~ \ ~ `_ _~ ~_ ~ Z ~ _~ _~
_~ \ ~ ~ 3 P~ 3 E~ t~
D . '¢ H u~ u~ :~ a _
_ _
",~ O ~a
l l
¢ ~ ~0
C~
O X
~ S
Z ~
¢ ~:
~1
- 26 -
11371 94
- V'~ ~ _
H ~: a ) H ~1
+ C~ . ~ C~ l
C~ H
(~1 H H H ~
1~1 + H E~ ~ N V
:~ ~ O .,~ ,~ 1~
H I ~ H X rl All
1~ X ~ o ~ ~
s:: E~ 11 11 X ~ ~
3 1l V'l V~'J 3 3
:~ H H --`
rl ~ ~
_
E~ _~ _ _ ~ ~ _~ _ .
\ ~ Z ~ ~ D~
O \ O H H H E~ E~ ~ ~1
V \ ~ `_ _, _, _, _, ~ ~
_. \ ~ ~ ~ ~ ~
_ _
¢ 3 ~ E~ ~
I ~ 1
xl
_ _
~ I
H Cl
.' U2 ~
_ ~ _
~ _ ~ .. _
- 27 -
.
1137~94
_ ~ , _
,1 C> V
I H H
rl ~ ~_
I a
.
~C
v~ o
~ ~: + ~ ~ V
vll l E~ l
~1 ~1 ~ J~
I ~rl
.,~
~, ~ ~ ~ .
Et~ vn
11
X
~ ~ ~ r~
_, r~ ~
_ . ~ ~ _
~ _
\ ~ _ ~_ _~ ._ _~ ~ ~_ ~_
\ ~ Z ~ i> r~
O \ O H H H E~ X ~ ~ ~:1
V \ ~_~_ _~ _, ~ `_ ~ ~_ ~,
~_ \
D ~ _ X H v E~ X E~ c~
_ _
I ~
P~: ¢
I:d H
E~
Z
H ~
_ _ _
. ~D
~ _
- 28 -
~13t~94
_ ,z _
X ~ l
. XZ ,
. ~
~ ~, .
X X~ ,
.
?~
-
~ _~ _~ ,_ ,_ ~ ~ _ æ
J~ E~ ~ ~ Z ~ Z :z ~
O Z O H H H Z O H H H
_, ~1 ~\J Z; ~1 ~I Z
~1: _ X X X ~ _X X ~X
_ ~ _
Q C ~
o o
~ l
C~ ~ 3
H ~1 O
I~ ~i U2 _
,, ,, ~ i
- 29 -
~137~94
X X ~ ~ ~ ~ C~ .
Vll ,1 Vll " ^~ " l
~ ~ ?~
X
~ v a~
S 3 3 i
ra ~ _
O \ ~ ~,
~d ~;xr~
_ ~ ¦ H
. _
- 30 _
1~37~94
_ ~.~
N ~q J~
I ¢ N C~
N
1~ ~ ~ 11 ~ 11
5~ 3
~: ~ 3
r~ ~ rJ
~ ~ ~_
~ _
\ _~ _ N _~ ,_ ,_ _~ ,_ _~
O \ ~ Z '~; O ~ ~ O ~
C) \ O H H X C~ ~:5 ~ ~ ~
\ H N O a ~ ~ O N ~1
n ~ _ x x X c~ c~ ~ ~ ~
_ __ _ _ _ _
_ ~ _ ~ __
_ _
_ _
- 31 -
1137~9~
.
$~ ~
~ ~a ~ .
C~
H ~ H
+ +
H ~ ~ ~ ~ +
~ H ~
3 11 V V X ~ H
~ H H
r~ rl
~ ~1
_
~ ~ E~ ~ ~ ~ ~ ~_ ~ _
\~) 2: ~ ~ ~ ~1 ~ H
\ O H H H ~ ~ ~1
O \ _~ _~ _~ ~_ _~ ~_ ~ _~
\ ~1 (U ~ ~1 H
_ _ X O C~ E~ _L ~
E~ -
. \
_
X
E~
H
c~ H
~ __.__ ___
-
_ .. ,_ ___._______ _ .
32
