Note: Descriptions are shown in the official language in which they were submitted.
1137340
~.~CRG~<OU~D OF THE I~`;VEI~TIO~
FIELD OF T~iE I~TENTIOI`~
This invention relates to a bass note generation
system for an electronic musical instrument, especially an
electronic orsan. The bass note generation system provides an
output seuence of bass notes forming a bassline to accompany
the combination of keys depressed on the chord section cf the
manual by the organist.
~hile the present invention is described herein with
reference to particular embodiments, it should be understood
that the invention is not limited hereto. The bass note
generation system of the present invention may be employed
in a variety of forms, as one skilled in the art will recognize
in light of the present disclosure.
PRIOR ART
Automatic bass note accompaniment systems are well-
known in the electronic organ industry. Electronic organs
commonly have keys arranged in one or more manuals and a
separate clavier of pedals. In general, the organist plays
the melody with the right hand upon the upper manual, the
chord with the left hand upon the lower manual and a bass
accompaniment upon the pedal clavier with the left foot. The
left hand chord performance and the left foot bass are the
accompaniments for the melody performance played with the
right hand. The left hand chord accompaniment is usually
played in consonance with the ri~ht hand melody and the
left foot bass accompaniment is played at a selected rhythm
li3~7340
pattern different than the left hand chord accompanirment. Of
course, to play the bass accompaniment, it is necessary to
rhythmically depress appropriately selected pedals while the
left hand chord is being played. The actual performance of
S the left hand chord and bass accompaniment in conjur.ction ~ith
the right hand melody requires a high degree of coordination
and proficiency. Thus, the beginnins organist and in certain
circumstances, the experienced organist utilizes an automatic
bass note accompaniment system. to facilitate playing a musical
piece.
The bass accompaniment should be musically related
to and complement the chord being played by the organist. This
musical standard requires some degree of chord recosnition to
properly relate the bassline to the chord being played. The
lS chord recognition devices common in bass accompaniment systems
require the organist to play the notes of a chord in a specific
sequence so that the recognition process operates correctly.
Other chord recognition devices dedicate logic circuits to
recognize certain musical note combinations representins
specific alphabetic chords. The amount of logic circuits
necessary to recognize a representative number of chords is
extremely large and correspondingly costly. The lir.ited number
of chords recognized and the playing restrictions placed upon
the organist are significant deficiencies of these systems.
1137340
In the automatic bass note systems in co~mon use, the
choice of bassline accompaniment is frequently limited to the
corbination of notes actually depressed by the organist. This
lir..itation severely restricts the for.mation of a musically
acceptable bassline pattern.
It is therefore a general object of this invention
to overcome the problems cf such prior art devices.
Ancther object is to provide a precomposed bass-
line or a root/fifth bassline routine to accompany a recognized
chord played by the organist.
Another object is to provide a scanned bassline
composed of a fixed routine and a selection of notes from
a~.or.g the keys actually depressed by the organist when the
depressed keys do not form a recognized chord pattern.
lS Another object is to provide a low~high bassline
routine composed of the lowest and hishest frequency note
selected from the keys actually depressed by the organist
when the depressed keys do not form a recognized chord
pattern.
Ar.other object is to provide a bass note generation
system including a chord recognition section for detecting
normalized chord pat-terns corresponding the keys depressed
by the organist and for trac~ing the root note for recognizable
chord patterns.
Another object is to provide a bass note generation
system including a chord recognition section for recognizins
norm21ized chord patterns including inversions and logically
restricting pattern identification to eliminate conflicts
in recognizable patterns.
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~i373U~0
Another object is to provide a bass note generation system
including a memory for storing a plurality of normalized bassline pat-
terns which are selectable depending upon the recognized chord pattern
and the root note of the recognized pattern.
Another object is to provide a bass note generation system
including a selectable bass rhythm pattern input for modifying the
musical bassline output.
Another object is to provide a bass note generation system
which resets to the first beat of a two bar phrase either upon receiving
entirely new chord input data for assuring that the root note of a re-
cognized chord is the first note played for each precomposed bassline
pattern or upon receiving a reset signal from a two measure rhythm unit
assuring that the accompaniment is periodically synchronized with the
rhythm unit.
Another object is to provide in the scanning mode the appro-
priate note selected from the keys depressed on the manual for the position
in the fixed bassline routine corresponding to the time interval of the
two bar phrase at which ihe input data representing keys depressed is
received by the system.
Yet another object is to provide as an alternative to the
automatic bass note generation system a continuously scanning high select
pedal generator for providing bass notes.
According to a broad aspect of the invention there is provided
an electronic organ having at least one keyboard, a keyer circuit, a
plurality of keying lines connecting said keyboard to said keyer circuit,
a bass note generation system connected in parallel to at least some of
said keying lines and comprising: a chord recognition circuit receiving
input data from at least some of said keying lines for identifying if
said input data is arranged as a normalized chord pattern and providing a
default output signal representing that said input data does not form a
normalized chord pattern; a scanning bassline circuit responsive to said
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11373~0
default output signal for providing a bass note value output at a fixed
bassline and composed of notes selected from among said input data; and,
a decoder-keyer circuit responsive to said bass note value output for
providing a bass note musical output.
Other objects will be apparent from the following summary
and detailed description.
-4a-
1137340
BRIEF Dl~:SC~I~TIG`; OF THE DR~liI'.~GS
FIG. 1 is a block diasram of the bass note generation
system including optional features and standard orsan circuits
~hich provide inputs to the system;
rIG~ 2 is a block diagram of the digital bass note
value generator portion of the system;
FIG. 3 is a partial block diasram of the input data
register of the digital bass note generator which includes the
chord recosnition circuit;
FIG. 4 is a detailed logic circuit of the control
logic circuit of the input data register;
FIG. 5 is a detailed logic circuit of the output
sender of the digital bass note value generator;
FIG. 6 is a block diagram of the decoder-keyer circuit
portion of the system which includes the high select manual
pedal bass note generator;
FIG. 7 is a block diagram of an alternative reset
circuit for the digital bass note value generator; and,
FIG. 8 is a schematic diagram of the connection of
the optional one finger chording system to the bass note
- generation system.
~1373~0
~U~lr~R~'
The present invention is directed to a bass note
generation system to provide a musical bassline accorpaniment
for an electronic musical instrument, namely, an electronic
organ. The system is connected in parallel relationship to
the ~eying lines of an electronic organ between the keyboard
and the standard organ keyer circuits. The bass note generator
system has four modes of operation providing distinct types of
musical bass note output routines in addition to the optional
features which are separately describe2 hereinafter.
In the first mode of operation the bass note
generation system provides a precomposed or preprogrammed
musical bassline output depending upon the type of recog-
nizable musical chord played by the organist, the alphabetic
note or tonic note of the chord and the timing of a beat or
measure counter. The precomposed or programmed bassline out-
put may be modified by the instrument player selecting one of
a plurality of rhythm patterns which are referred to hereinafter
~ as k2ss rhythm patterns by closong a switch or tab on the
instrument console. In the second mode of operation
the bass note generation system provides a root/fifth
output routine depending upon the alphabetic or
tonic note of a recognizable chord played by the
organist and the timing of a beat or measure counter.
The root/fifth bass note output routine may also be modi-
fied by the instrument player selecting one of a plurality
of bass rhythm patterns by closing a s~7itch on the instru-
ment console. In the third mode of operation, the bass ncte
-- 6
~137340
generation system is ufiable to identify the key combination
depressed by the instrument player as a recognizable
chord pattern and provides a scanned bassline musical
outpu, in accord with a fixed routine and ~.ith notes
selected directly from the sequence of keys depressed
by the instrument player. The scanned bassline musical
output may also be modified by the instrument player
selecting one of a plurality of bass rhythm patterns
by closing a switch or tab on the instrument console.
In the fourth mode of operation, the bass note generation
system fails to identify the key combination depressed by
the instrurient player as a recognizable chord pattern and
provides a low-high output routine selected directly from the
sequence of keys depressed by the instrument player. The low-
high musical output routine may also be modified by the instru-
ment player selecting one of a plurality of bass rhythm patterns
by closing a switch or tab on the instrument console. In
addition, the instrument player can directly select the scanned
bassline or lo~J-high modes of operation resardless of ~hether
the keys depressed form a recognizable chord pattern by
closing a switch or tab on the instrument console.
~ selected number of keys from the chord section
of an organ keyboard are connected via their respective
keying lines to the data input lines for the bass note
generation system. ~s an option, the input to the
system may be from a one finger chording system which
~137340
are well-known in the art. ~he in?ut data lines are received
by a shift register in the chord recognition portion of the
system. The sequence or pattern of all received data l-nes
are compared to a progran~ed logic array to determine if the
keys depressed by the instrument player form a recognizable
pattern. ~ach musical chord type, such as a major chord, has
a set mathematical relati~nship between the notes forming
the chord and is therefore identifiable if the mathematical
pattern is detected. In addition to recognizing the chord
pattern in the root position, since the organist may play
a chord in an inverted position, that is, some of the
alphabetic notes raised an octa-~e, it is desirable to
recognize the chord pattern in the root position and all
inversions. The programmed logic array detects the major,
minor, sixth, major seventh and dominant seventh chord patterns
in all inversions, the major sixth chord pattern in the root and
first inversion and the minor seventh in the root and third
inversion. The major sixth anZ minor seventh chords are
restricted in the patterns identified to eliminate an over-
lapping or conflict wherein the same alphabetic notes arearranged in different sequences in both chord patterns.
If the input data from the keying lines does not form
a recognizable chord pattern, the register repositions the
data by shifting the data in the first bit position to the last
bit position and similarl~ shifting all other data bits do~n-
ward one bit position. The shifted data is comparea to the
progra~ed logic array to match the ne. data positions
1137340
with the normalized chord patterns. The shifting and comparing
continues until a pattern match is identified or every possibility
is e~hausted. A root counter tracks the number of shifts or
data transpositions necessary to locate an identifiable chord
type pattern in the input data. The value of the counter
represents the alphabetic note of the chord pattern identified.
The identifiable chord patterns are further reduced
in a logic circuit to major, minor and dominant seventh output
signals. These output signals together with the value of the
root counter are used as addresses to a bassline pattern
memory. In the preferred embodiment, the memory contains four
groups of precomposed basslines and each group has three
bassline variations and each bassline has sixteen notes.
Each of the major, minor and dominant seventh address sisnals
selects one o~ the four groups of precomposed basslines, the
fourth group being selected as hereinafter set forth. The
output value of the root counter is reduced to three ranges of
output signals, 0 through 3, 4 through 7 and 8 through 11.
Each of the range address sisnals selects one of the three
bassline variations within the selected group. Each
precomposed bassline is stored in the memory with nor-
malized bass note values and the precomposed bassline chosen
is related to the type of chord pattern recognized and the
number of shifts necessary to obtain the pattern recognition.
~37340
The digital value output of the bassline mer,ory
is applied to an output device. The value of the root cour.ter
is a2plied tc the output device and serially aaded to the
digital value output of the bassline memory. The addition
5 of the disital value of the root counter to each digital note
value from the bassline nemory trar.spcses the note value into
the key in wnich the orsanist played the recosnized chord.
The serial addition occurs under control of the
enable memory. A beat counter which is coupled to a tempo
clock provides an output signal at each one of sixteen half
beats in a two measure phrase. The two measure phrase is
determined by the rhythm unit of the organ which resets the
beat counter at the termination of each two measures. Each
signal from the beat counter is applied to the pattern
memory to select one of the sixteen normalized digital note
values in the precomposed bassline. The beat counter signal
is also applied to an enable memory. In the standard or
unmodified bassline, the enable memory provides an enable
output at each even signal of the beat counter. The beat
counter is also reset by an input from a standard organ
key-down detector which provides a signal output for each
new key depressed if no other keys are held down. Thus,
the first note of each precomposed bassline corresponcs to
the root note of the recognized chord even if a new chord
is selected in the middle of a t~Jo bar phrase determined by
the rhythm unit of the organ. Of course, other sources of
reset inputs can be applied to the beat counter to obtain
dif~erent resetting secuences.
-- 10 --
1~37340
The ena~le signal fro~ the memory begins the serial
addition and is applied by a decoder-~eyer circuit to synchronize
the receipt of the serial data. The decoder-keyer circuit
receives the serially addea digital signal and converts it into
parallel binar~ signals. The parallel binary data is applied
to a multiplexer which also receives twelve fre~uency signals
from twelve top octave generators. The value of the binary
signal selects one of the twelve frequencies. The selected
frequency is received by a stanaard frequency divider chain
which reduces the top octave frequency to the bass note range
and applies the output of the divider to the standard keyer
circuit to provide a musical bassline output.
The precomposed bassline played by the decoder-keyer
circuit is modifiable by the ir.strument player. The instrument
player may select one of a plurality of bass rhythm patterns
by closing a switch on the organ console. ~n input signal
representing the selected bass rhythm pattern such as samba
is applied to the enable memory as an address signal. The
selected bass rhythm pattern alters the occurrence of the
enable signal from the enable memory thereby blanking certain
time slots in the measure in which the digital note value from
the pattern memory and the digital value of the root counter
would be serially zdded and applied to the decoder-keyer circuit.
In addition, if the instrument player selects either the
beguine, afro-latin or tango bass rhyt~,m pattern, an input
~ signal is provided to the bassline pattern memory to over-
riae the chord pattern recognition address. The beguine,
1137340
afro-latin or tango bass rhythm,line or BAT line selects
the fourth sroup of basslines stored within the pattern
memory. ,he root counter value selects the variation of
the bassline within the fourth group 25 described above.
The BAT line and digital value of the root counter address
the enable memory and select a preprosrammed time sequence for
the enable signal. The digital value output of the pattern
memory and the digital value of the root counter are serially
added in the output circuit and applied to the decoder-keyer
circuit under control of the enable memory.
If the instrument player selects a root/fifth bass
routine by closing a switch on the console, the normalized bass-
line pattern memory is disabled. The chord recognition portion
remains operative to identify the chord played by the instru~ent
player. A root/fifth memory provides a signal on line root
enable to the output device when the root note is to be played.
The digital value of the root counter is also applied to the
output device. If a root note is to be played in a certain
time interval or slot, the enable memory provides an output
enable signal which applies in serial from the digital value
of the root counter which represents the root of the
recognized chord played by the organist to the decoder-
keyer circuit. The decoder-keyer circuit operates as
described above to provide a musical output.
- 12 -
.
1137340
If the rootjfifth memory provides an output
indicating that the fifth is to be played and the enable
memory provides an enable signal, the digital value of the
root counter is serially added to the binary value of seven
in the output circuit. The musical fifth is mathematically
seven half steps above the root thus the addition of the
binary value seven to the value of the root counter converts
the root value into the fifth value. The decoder-keyer circuit
receives a disital value representing the fifth of the recognized
chord played by the organist. The root/fifth routine may be
modified in the same manner as described above by the instrument
player selecting a new bass rhythm pattern.
If the chord recognition system compares every
possible arrangement of input data patterns with the pro-
grammed logic array without recognizing a normalized chord
pattern, the system provides a fi~.ed bassline routine
comprised of selected notes from among the keys actually
depressed by the organist. In the scanned bassline routine,
the shift register moves the received data in one direction
until the data corresponding to the first input line with a
signal representing a key depression is placed to the first
data bit position. The root counter then provides a digital
value e~ual to the number of shifts necessary to the output
sender. The output sender receives an enable signal from
the enable memory at each even value of the beat counter and
- serially applies the digital value of the counter to the
decoder-keyer circuit. The decoder-keyer circuit operates
as described above to provide a musical output signal.
` - ~137340
The shift resister con~inues to shift in the
same direction to move each of the next four reccived data
bits into the lowest bit position of the register, repeating
the receivea data bits if necessary. The root counter
provides to the output sender circuit the digital value
of the number of shifts necessary to move each data bit
into the lowest bit position of the shift register. The
remainder of the system continues to operate as described above.
The shift register now reverses shifting direction to move each
of the next four data bits into the lowest bit position of the
register. The root counter which tracks the shift register
provides a digital value corresponding to the number of shifts
necessary to move each data ~it into the lowest bit position
of the register. The re~ainder of the system continues to
operate as described above. Thus, the keys actually depressed
by the organist are scanned in a fixed routine and selected ones
of the notes corresponding to the keys depressed comprise the
bassline with the same note forming the first note of each
two bar phrase.
If the system is placed into the scanning bassline
routine during the t~o bar phrase of the beat counter controlled
by a reset input from the rhythm unit, the note corresponding to
that time position in the fixed bassline is played. ~he shift
register moves the received input data following the same down
or up scanning sequence as described above. A note counter
connected to the shift register sequences a binary value of two
for each data bit shifted to the lowes~ position of the register.
1137340
The binary value of the note counter is compared to the
binary value of the beat counter and if a predetermined
comparison criterion is not satisfied, a control circuit
forces the register to continue shiftins cata into the lo~est
data bit position until the criterion is met. The root
counter which tracks the shift register supplies the binary
value of the number of shifts necessary to the output circuit.
The remainder of the system continues to operate as described
above. Thus, the fixed bassline routine in effect catches
up with the beat counter before a note is played.
A low-high bassline routine is provided if the
instrument player selects the root/fifth routine and the chord
recognition portion does not identify the input data as a
normalized chord pattern. The resister shifts in one direction
until the first data bit received reaches the lowest bit position.
The root counter provides to the output circuit a binary value
equal to the number of shifts necessary to move the data to the
lowest bit position. The remainder of the system operates as
described above to provide a musical output corresponding
to the lowest frequency note actually depressed by the
organist. The control circuit now forces the register to
shift in the opposite direction until the next input data
bit which corresponds to the highest frequency note depressed
by the organist is moved into the lowest bit position. The
root counter tracks the number of shifts and provides a digita~
value to the output sender. The remainder of the system operates
as described above and thus provides a low-high bassline routine
composed of the lowest and highest keys actually depressed by
- the instrurent player.
.
1137340
As an option to providing any of the four automatic
bassline routines described above, the system provides a manual
high pedal select bass note output. The serial aata received
by the decoder-~eyer circuit from the output sender is not
used. Instead, a multiplexer receives as inputs each of the
pedal lines from the standard pedal cl2vier of the orsan.
A scanner circuit interrogates each of the pedal lines
received by the multiplexer starting at the highest frequency
pedal. The scanner sequences to each pedal line until a pedal
line with a signal representing a depressed pedal is detected.
Once the match is located, the digital value of the scanner
is loaded into a selection multiplexer with latching capabilities
and the scanner is reset to the highest frequency pedal line
and scanning continues. As the scanner is searching for the
next pedal note played by the organist, the digital value
received by the selection multiplexer selects one of a
plurality of top octave frequency generators. The frequency
of the top octave generator selected is applied to a divider
chain to lower the frequency into the bass note range. The
output of the divider chain is applied to a standard ~eyer
circuit to provide a musical output signal corresponding to the
depressed pedal. The instrument player can thus provide a
manually selected bassline by operating the pedal clavier
instead of utilizing the automatic bassline routines.
- 16 -
~1373~0
In the preferred embodiment, the digital circuitry
for the above-described bass note seneration system including
the optional one finger chord system. and the optional manual
high pedal select system is in_orporated in a large scale
integrated circuit system.
1137340
DETAILED DESCRIPTION
FIG. 1 is a block diagram of the bass note generation system
for an electronic musical instrument including an optional one finger
chording system and an optional high select manual pedal system. The
bass note generator system has four modes of operation providing dis-
tinct types of musical bass note output routines. The type of bassline
musical output routine depends upon the combination of keys depressed
by the organist, the bass rhythm pattern selected by the organist and
the value of a beat or measure counter.
If the organist depresses a group of keys on the lower manual
12 of a two manual organ, a voltage signal corresponding to each de-
pressed key is placed on a respective keying line. In the preferred
embodiment, 20 keys of the lower manual 12 are associated with the bass
note generation system, however, it should be apparent to one of ordinary
skill in the art that the number of keys may be increased or decreased
without departing from the scope of the present invention. Each D.C.
level signal on the respective keying lines Dl through D20 is applied
both as the data input to the digital bass note value generator 14 and
to the standard organ keyer circuits, not shown. As an alternative
embodiment, the keying lines Dl through D20 are connected to a one finger
chording system 16 such as the one described in our Canadian application
Serial No. 303,615 filed May 18, 1978. The bass note generation system
is connected in parallel across the keying lines Dl through D20 and the
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1137340
standard organ keyer circuits. The optional one finger
chording system is connected in series ~ith the bass note
generation system. The entire bass note generation system
including the optional features is designed for z large
;'5 scale integrated circuit system.
One finger chordins systems are well~known in the
electronic musical instrument field and such devices enable
,' the instrument player by the depressio~'of a single key on
the organ manual to play a predetermined chord. If activated
by the orsanist, the one finger chording'system réc~eives the
D. C. level signal on the keying lines-Dl through D20 corres-
ponding to the key depressed by the instrument player and
determines which additional notes are necessary to
` complete a predetermined chord. The one finger
,~15 chording system places a D. C. level signal on-'-t~e
respective keying lines corresponding to the additional
; selected notes. The D. C. keying lines co~ected to
the standard organ keyer circuits thereby-have a D. C.
level signal due to the manual depression--of a key by
- 20 the instrument player and additional D. C. level signals
corresponding to the selection of addi'tional notes by the
one finger chording system. If the instrument player closes
a switch on the organ console, the optional one finger chording
is operative and both types of D. C. level siynals are applied
to the input of the bass note generation system as fully
explained hereinafter. However, if the optional one finger
chording system is not activated, only the D. C. level voltage
` -- 19 --
~37340
signals on ~eying lines Dl through D20 corresponding to keys
actually depressed by the instrument player are applied to
the input of the bass note generation system. mhus, the
digital bass note value generator 14 receives at its input
either the keying lines connected directly to the organ manual
12 or connected through an optional one finger chording
system 16.
Regardless of the source of the input data signals,
the digital bass note value generator 14 attempts to recognize
the structure or pattern of the input data as one of several
types of musical chords. The number of musical steps between
the notes forr~ling the various types of musical chords is constant
regardless of the alphabetic key in which the chord is played.
~he chord recognition system of the digital bass note value
generator 14 normalizes the chord identification process to the
key of C by receiving the input data information on keying
lines Dl through D20 into a multi-bit shift register and
comparing the outputs of the shift register with a
program logic array to determine if the outputs of the
shift register are in a recognizable chord pattern.
If no pattern is recognized, the register shifts the
relative position of the input data within the register
and attempts to recognize a chord pattern in the shifted
data. A counter parallels the operation of the shift
register to retain the numerical value of the number of
shifts necessary before a chord pattern is recognized. If
the original input data or the data in ar.y shifted position
- 20 -
,
` " 1~3734~
.
is in a recognizable chord pattern the type of chord pattern
, and the number of shifts necessary to recognize the chord
pattern or structure, provides an address to a programmable
pattern memory to select a digital value representing a
, 5 precomposed bassline or bass note sequence. A timing
control circuit in the digital bass note value generator
- 14 receives tempo timing information from the rhythm section:
~-~ 22 of the organ on line m~ 1 and provides an enable signal to
u serially add the digital value of the preprogra~ed bassline
from the pattern memory and the digital value of the number
;~ of shifts necessary to recognize a chord pattern and to apply
the serially added digital bass note value to the decoder-keyer
circuit 18. The timing control circuit includes a beat counter
which receives a reset sisnal on line T2 either when the rhythm
unit 22 co~,pletes a two ~easure interval or the instru~ent
, player releases all depressed keys and depresses a new key or
; combination of keys so that the first note in each new bassline
is the root note. However, it should be apparent to those of
ordinary skill in the art that the beat counter of the digital
bass note value generator 14 may receive a reset signal generated
by a different source. The decoder-keyer circuit 18 converts
the serial data from digital bass note value generator 14 into
parallel data. The parallel data addresses a multiplexer and
selects the appropriate frequency input signal from twelve
top octave generators referred to as MDD circuit 20. The
- selected top octave frequency is applied to standard divider
circuits to lower the frequency to the bass note range. The
output from the dividers is applied to the standard organ
keyer circuits to generate a musical output signal.
'
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- 21 -
1137340
The instru~ent player can modify the digi.al
note value information determined by the digital bass note
value generator 14 by selecting one of a plurality of rhythm
bass patterns from the rhythm unit 22. ~ach of the rhythm
bass patterns are applied to an enable memory of the timing
control circuit in the digital bass note value generator 14.
The enable memory also receives the output of the beat counter
and deletes selected time slots at which a bass note value is
normally sent to the decoder-keyer circuit 18. The decoder-
keyer circuit 18 receives the digital note value informationnot 2eleted and performs in the same manner as described above.
The instrument player may close a switch or tab 24
on the instru~.ent console which provides a signal input on
line 25 to digital bass note value generator 14 to select the
second mode of operation. In the second mode of operation,
the bass note generation system provides a root/fifth bass note
routine. In this root/fifth or second mode, the keys depressed
by the instrument player are identified in the chord recognition
portion of the digital bass note value generator 14 as
described above. However, since the root or tonic note
is also the alphabetic note which is determined by the number
of shifts necessary to identify a chord pattern or structure,
the binary value of the counter indicates the root note.
Furthermore, since the musical fifth is always seven musical
half steps above the root, the addition of a binary value of
seven to the binary value of the number of shifts needed to
find a chord pattern match corresponds to the muscial fifth.
- 22 -
- 1.1373~)
The output of the bassline pattern memory of the digital ~ass
note value generator 14 is disabled in the root/fifth mode of
operation. ~ root/fifth memory in the bass note value generator
14 provides a signal to the output circuit to deter~ine if the
root or fifth note is appropriate.
The timing control circuit provides an enable signal
to the output circuit of the bass note value generator 14 to
serially add the value of the counter ar.d the binary value
seven if a fifth bass note is re~uired and to apply the
serially added digital value to the decoder-keyer circuit 18
or if a root bass note is required to serially apply the digital
value of the counter to the decoder-keyer circuit 18. The
decoder-keyer circuit 18 functions as described above. Simi-
larly, the instrument player may modify the root/fifth bass
note routine by the selection of one of a plurality of bass
rhythm patterns from rhythm unit 22 which affect the timing
control circuit and the root/fifth memory to alter the time
slot at which the digital bass note value corresponding to
the root or fifth bass note is applied to the decoder-~eyer
circuit 18. The decoder-keyer circuit 18 functions as
described above to provide a modified musical root/fifth
routine output.
If the instrument player depresses a group of
keys on the lower manual 12, and the chord recognition
system of the digital bass note generator 14 is unable to
- identify the depressed keys as a chord structure or pattern,
- 23 -
373~0
then the entire bass note generation system defaults to 2
scanning bassline or third mode O r operation. In this scan
default mode of operation the keying lines Dl through D20
are scanned and selected ones of the notes among the
keys depressed are used to compose a fixed bassline
pattern. In the scan default mode, the preprogrammed
bassline pattern ~emory of the digital value bass note senerator
14 is not utilized. The digital bass note value generator 14
scans the data inform,ation received by the shift register and
provides to the decoder-keyer circuit 1~ a disital note value
according to the nu~.ber of shifts necessary to obtain the first
data bit from the register, then the number of shifts necessary
to obtain the second data bit from the register and so on until
the fixed bassline pattern is completed. The shift register
shifts in one direction to the next data bit for the first four
even counts of the beat counter then the shift register shifts
in the reverse direction for the remaining four even counts of
the beat counter. Thus, a predetermined fixed bassline pattern
with the notes corresponding to selected keys actually depressed
by the instrument player is provided to the decoder-keyer
circuit 18 to provide a musical output signal. The
scanned bassline pattern may be modified by the
selection of one of a plurality of bass rhythm patterns
from rhythm unit 22 as described above.
- 24 -
1137340
If the instrument player selects a root/fifth
mode of operation via closing switch 24 and the group of
keys depressed by the instrument player are not recognized
by the chord detection portion of the bass note value
generator 14, the system defaults to a scanning lo~J-high
or fourth mode of operation. The shift register moves the
first received data bit down to the lowest bit position and the
digital value of the number of shifts determined by the
counter is applied to the output sender of the digital bass
note value generator 14. The timing control circuit provides
an enable signal to apply the digital note value to decoder-
keyer circuit 18. The shift register then reverses direction
and moves the data bit corresponding to the highest freauency
input keying line up until it recirculates back to the lowest
data bit position. The counter value of the number of required
shifts is applied to the output circuit. The timing circuit pro-
vides the enable signal to apply the digital note value to the
decoder-keyer circuit 18. The 2ecoder-keyer circuit 18 continues
to operate as described above and provides a musical bassline
output routine composed of the lowest and highest frequency
note keys dPpressed by the instrument player. The low-high
bassline pattern may be modified by the selection of one of
a plurality of bass rhythm patterns from rhythm unit 22 as
described above.
- 25 -
- 1~373~0
The bass note generation system has an optional manual
pedal input circuit 26. The output of digital bass note value
generator is not used and the input to the decoder-keyer
circuit 18 is from the pedal clavier of the orsan. A D. C.
level value is placed on the ped~l lines corresponding to the
pedal depressed by the instrument player. The decoder-keyer
circuit 18 continuously scans the pedal input lines to
determine the highest frequency pedal line with a D. C. level
signal. Once the highest pedal line with a D. C. level
frequency is detected, the digital value corresponding to
that line is used as the address to a multiplexer for selecting
the appropriate top octave frequency from ~DD circuit 20 fro~
lines Fl through F12 and the scanner is reset to again begin
scanning of the pedal lines from the highest frequency peda~
line downward. The selected ~lDD frequency is applied to a
standard divider circuit to lower the MDD frequency to the
bass note range. The output of the divider is applied to the
standard type keyer circuit and the decoder-~eyer circuit 18
provides a bass note output corresponding to the selected
pedal note.
FIG. 2 is a block diagram of the bass note value
generator 14. FIG. 3 is a partial block diagram of the
input register 30 of the bass note value generator 14.
The input data register 30 receives keyir.g signals on
lines Dl through D20 and attempts to recognize the input
data as a chord pattern. If the input data is recognized
as an identifiable chord pattern, the input data register
30 provides three signals to control the operation of the
1137340
remainder of the digital bass note value generator 18. The data re-
gister 30 provides a first signal on line PF indicating that the input
data received from keying lines Dl through D20 matches a recognizable
chord pattern, a second signal on one of the lines, M, W or S indicating
that the pattern is a major chord, minor chord or seventh chord pattern,
and a third signal on line DMC indicating the alphabetic note of the
chord. In response to these signals as well as others fully explained
hereinafter, the remainder of the bass note generation system 14 provides
a digital note value representing a preprogrammed bassline or root/fifth
musical routine to the decoder-keyer circuit 18 which generates the
corresponding musical output. If the input data on keying lines Dl
through D20 is not recognized as an identifiable chord pattern then the
input data register 30 provides a signal on line SD indicating that the
input data does not coincide with any recognizable chord pattern and the
entire bass note generation system defaults to a scanning bassline or
low-high musical routine output.
The shift register 32 in FIG. 3 of the chord recognition
portion of the input data register 30 receives input information either
directly from the keying lines Dl through D20 connected to the keyboard
or from a one-finger chording system such as the system disclosed in
the abovementioned Canadian application Serial No. 303,615. The shift
register 32 has
-27-
~,," ~
..~,
1137340
twenty-four input lines Il through I24. ,~ D, C. level
signal is present at the input lines Il through I20 if
a corresponding keying line has a D. C. level signal
representative of a manual key depression by the
instrument player or the output of a one-finger chording
system. The remainir.g input lines I21 through I24 are con-
nected in common to a voltage source representative of
no input signal on these lines since in the preferred
embodiment only twenty keys of the lower manual of
an electronic organ are connected to the bass note
generation system.
In the preferred embodiment, the first key from
the lower manual associated with the bass note generation
system is a C note and the respective keying line Dl for
this key is connected to input line Il and to the lowest or
first position in the shift register 32. The last or the
twentieth key connected from the lower manual is a G note in
the next octave above the first key and the respective keyir.s
line D20 for the twentieth key is connected to input line
I20. It should be apparent to one of ordinary skill
in the art that the number of keys of the lower manual
connected to the bass note generation system, as well
as the selection of keys, can be modified without departin~
from the scope of the present invention. The alternative
connection between a one finger chording system and the bass
note generation system is e~plained with reference to FIG. ~.
- 28 -
1137340
The one finger chording system described in the abovementioned
Canadian application Serial No. 303,615 is connected in series circuit
by the modification illustrated in FIG. 8. The same numerals are used
to illustrate the operation of the circuit but are used herein with a
prime symbol. Only the operation of the modification of the circuit is
set forth herein for the sake of clarity. The input signal received at
line 13' of FIG 8 is applied directly on line 60' to transfer device 220.
The source of transfer device 220 is connected to the common ground GND
and the logic l at the gate applies the ground to the drain terminal. The
logic 0 on the drain terminal of transfer device 220 is applied to the
gate of depletion pull up device 222 which normally maintains the input
to inverter 224 at a logic 1. The input to inverter 224 is now at a
logic 0 state and the output line OFC is at a logic l state. The line
OFC is applied to the input of the bass note generation system, specific-
ally to input line 13 of the register 32 of the digital bass note value
generator 14.
If the circuit in FIG. 8 receives a signal from the remainder
of the one finger chording circuit on line ROM 3a a logic 1 signal is
present at the gate of transfer device 226. The source of transfer
device 226 is connected to ground and the logic 1 at the gate applies
the ground, logic 0, to the drain terminal. The drain terminal is con-
nected to the gate terminal of depletion pull up device 222. The logic 0
at the input to inverter 224 provides logic 1 state output on line OFC.
Thus, the bass note
-29-
~'
1137340
generation system rcceives as inputs the signals directly
fror,l the manual depression of keys by the instru~ent player
or the signals from the one finger chording system. Of course,
each of the twenty circuits of the one finger chording circuit
similar to the circuit illustrated in rIG~ 8 are modified
in the same manner to interface with the bass note
generation system.
The control losic circuit 34 receives a load pulse
on line 35 from a legato detector, not shown. A legato
detector is a standard circuit in an electronic organ which
produces an output pulse of finite duration upon the depressicr.
of any key on the lower manual of a t~o-manual organ resardless
of how many prior keys are depressed and retainec do~n.
It should be apparent to one of ordinary skill in the art
that other means to produce a pulse output signal for each
key depression coul2 be used in place of the legato detector.
When the load pulse on line 35 is gone, the control circuit
34 provides a signal to the shift register 32 on line L to
load the signals at the input lines Il through I20 as
is well-kno~n in the art. The signal on line L is also
applied to the reset input of counter 36. The control
logic 34 is illustrated in Fig. 4 and is referred to
through the description of the operation of the bass
note generation system.
The output lines Sl through S24 of the shift
register 32 are connected to a progra~ed logic array or
read only memory 38. The logic array 38 is programmed in a
~anner well-known to those of ordinary skill in the art to
receive the outputs Sl through S24 and to determine ~hich
- 30 -
~3734~)
outputs or ~hich combination of outputs has a D. C. level
sisnal. The programmea logic array 38 provides an out?ut
signal on one of thc lines Al through A7 to indicate that the
output lines S1 through S24 of the shift rec;ister 32 are
in the musicially structured format or pattern of a major
chord, a major seventh chord, a major sixth chord, a minor
chord, a minor seventh chord, a minor sixth chord, or a
dominant seventh chord.
The musical pattern relationship between notes
forming a specific type of chord are uniform. ~hese patterns
are not altered if the chord is played in a different key.
Therefore, all chord pattern identification is normalized
to a single key and in the preferred em~odiment the key of
C is selected. The musical structure for a major triad chord
is the root (alphabetical note), a major third (up four half
steps from the root), and the fifth (up seven half steps fro~
the root.) A half step is the interval between any key and the
adjacent key. The frequency ratio between any t~o notes a half
step apart is 1:1.059. A minor triad chord consists of the root
note, a minor third (up three half steps) and the fifth. .~ dor,i-
nant seventh chord consists of the root note, a major third, thefiftn and the flatted seventh. A major seventh chord consists
of the root note, a major third, the fifth, and the seventh.
A minor seventh chord consists of a root note, a minor third,
the fifth, and the flatted seventh. A major sixth consists
- of a root note, a major third, the fifth, and the sixth. ~ minor
sixth consists of the root note, a minor third, the fifth, and
the sixth. The code for the programn:able logic array 40 ~ith
the numbers indicating the output lines Sl through S2~ of
shift register 32 ~hich have a logic 1 output signal is as
follo~s:
i~373~V
CI'~T 1
C~30RD TYPI::: P.~TTLI~J I~LCOG`JITIG~J CODI::
-
major chord (1 + 13) (5 + 17) (8 + 20)
major seventh chord (1 + 13) (5 + 17) (8 ~ 20) (12 + 24)
major sixth chord (1 + 13) (5) ~8) (10)
minor chord (1 + 13) (4 + 16) (8 + 20)
minor seventh chord [(1) (~) (8) + (13) (16) (20)] (11)
minor sixth chord (1 + 13) (4 + 16) (8 + 20) (10 + 22)
dominant seventh chord (1 + 13) (5 + 17) (~ + 20) (11 + 23)
10 The remainir.g output lines from register 32 not numerically
included in the respective equations or formulas must be
at a losic 0 state and this requirement is to be considered
part of each of the above equations.
ln accord wit`n the above code, a major chord patterr
is detected on line ~1 if, for example, the shift register 32
has an output signal on line Sl, line S5 and line S8. ~he
entire code of the prosram logic array 38 specifies that a
major chord is recognized if the data register 32 has ar
output signal on the first (Sl) or thirteenth (S13) line and
the fifth (S5) or seventeenth (S17) line and the eighth (S~)
or twentieth (S20) line. ~his mathematical pattern is necessary
since it is possible for the instrun~ent player to play a chord
inversion and the code of the program logic array 38 for a major
chord pattern also identifies inverted chords. In a similar
manner, the major seventh chord, the minor chord, the minor
sixth chord, and the dominant seventh chord are progra~ed for
recognition through the above pattern code which includes all
of their inversions. 3~3Owever, the major sixth chord and the
minor seventh chord are not detected through all of their
inversions according to the above pattern codes, since if all
inversions are attempted to be recognized a conflict occ~rs.
- 32 -
113734~
~ y a conflict, it is meant that the same letter
note combinations are yossible for certain specific major
sixth and minor sevcnth chords. Therefore, a selection
decision has been made and programmed into the logic array
38 so that when such a conflict in letter note combinations
occurs, one musical structured chord combination takes priority
over the other. One specific type of chord contradiction
occurs bet~-een a C major sixth chord with the alphabetic note
com~ination of C, ~, G, ~, and an A minor seventh chord ~ith
the note combination of ~, C, ~, G. Thus, it is clear that
for both the C major sixth chord and the PA minor seventh
chord, the same combination of alphabetic notes are played
with merely the alphabetic notes beir.g rearranged in a
different sequence. This contradiction in chord recognition
based upor. the musical structure or patterr. of the various
chords precludes the ability to recognize a major sixth
and all its possible inversions. Therefore, in the code
for the programmable logic array 38 as set forth above, the
decision has been made to exclude the possible contradiction
by restricting the identification criterion for the major
sixth chord and ~inor seventh chord. In the preferred
embodiment, the major sixth chord is identified only in
the root position and first inversion position of the chord
and the minor seventh is identified only in the root and
third inversion of the chord.
- 33 -
~37340
The outputs of the progra~a~le logic arr2~ 38 on
lines Al through ~.7 are connected to the chord losic circuit 40.
The lines .~ 2, and ~3 representing a major, major si~th,
and major seventh chord are rcceived by the ~0~ ~ate 42, the
output lines A4, ~5, and .~6 representing a minor, minor sixth,
and minor seventh chord are received by the ~IOR sate 44 anc the
output of A7 representing a dominant seventh chord is receive~
by inverter 46. If a signal is received at any of the
inputs to the i~OR gates 42 or 44, the respective output
line changes logic state. The output of ~OR oate 42,
~;0~ gate 44, and inverter 46 are connected to the inputs
of ~A~D sate 48. Furthermore, the outputs of ~.0~ gate 42,
~OR gate 44, and inverter 46 are respectively connected to
inverters 50, 52 and 54. Thus, if the major chord pattern
is detected, a logic 1 state signal on line Al is present
at the first input to ~OR gate 42, the output of ~OR gate
42 changes from a logic 1 state to a logic O state. The
output of inverter 50 on line rl is at a logic 1 state
indicating a ~ajor ehord pattern. In addition, the first
input to ~iA~D gate 48 from the output of ~OR gate 42 is
at a logic O state and the output line PF of the 2~A~D gate
48 ehanges to a logic 1 state indicating that a ehord
pattern is identified.
Thus, if the signals at output lines Sl throush
S24 of shift register 32 form a major chord pattern identi-
fiable by the programmed logie array 38 the chord logic circuit
40 provides an output signal on line ~ and an output signal on
- 34 -
1137340
line ~r. I the program logic array 3~ identifies a ~,inor chord
pattern on line ~4, a minor si~:th chord pattern on line ~.5 or a
minor seventh chord pattern on line ~.6, the line 1; in~icatirg a
minor chord has a logic 1 output. In the same manner as described
for a major chord pattern, the output of I.Ar~D gate 48 changes
state to a logic 1 indicating that a chord pattern match is
found. If the programmed logic array 38 identifies a dominar.t
seventh chord pattern on line ~7, the output line S indicatins
the dominant seventh chord is at a logic 1 state output and the
output of I;AND gate 48 changes state to a logic 1 indicating
a chord pattern is found.
The signals on lines M, ~? or S are applied as a
partial acdress to the bassline pattern memory 70 in FIG. 2.
The signal on line PF is applied as a control to the output
sender 140 in FIG. 2 and as an input signal to control logic
eireuit 34 in FIG. 3.
If no chord pattern according to the above logic code
is detected, the shift register 32 under direction from the
eontrol logic 34 shifts the input data, if any, in the first bit
position into the twenty-fourth bit position and any aata in the
second bit position downward into the first bit position and
similarly throughout the register 32. ~'0~?, the data information,
if any, whieh was received at input line I2 to the shift register
32 is in the first bit position as if it were reeeived on line
Il. The output lines Sl through S24 of shift register 32 are
now compared to the chord pattern combinations of the Frosra~ ed
logic array 38. If no chord pattern is recognized in the shifted
1137340
data, the register 32 ag~in shifts all the data information
one ~it position and the comparison is repeated. Therefore,
regardless of what key a chord is played in by the instrum.er.t
player, the chord recosnition portion of data register 30
recognizes the musical structure unique to the type of chord.
The above-described shifting of register 32 is
controlled by the line SR and line D from the control logic
circuit 34 of FIG. 4. The inputs to A.JD gate 102 are ~D and
PF indicating that the system is not in the scan default mcde
and no chord pattern is found. The output of ~ D gate 102
on line 103 is at a losic 1 state and is connected to ~oth CP~
gate 114 and CR gate 128. The output of OR gate 114 on line D
is a logic 1 state and controls the downward direction of shift
register 32. The output of OR gate 128 on line SR is at a 105ic
1 state and controls when the register 32 shifts. The 105ic
discussed throughout the specification is dynamic phased cloc~
logic which is well-known to those of ordinary skill in the
art and hence for clarity of description no specific reference
is made to the clock signals inherent in the system. Thus,
when the chord recognition portion of the data register does
not recognize a chord pattern in the output lines of the
register 32 and the system is not yet in the scan default
mode of operation, the output lines D and SR of the control
logic circuit 34 force the register 32 to shift the respective
positions of the input data. After each data shift, if no
pattern match is found and the system is not yet in scan
default the input ~ines CD and PF to AI~D gate 102 remain at
a logic 1 state and the register 32 again shifts the
respective positions of the input data.
1137340
The lo~d pulse on line I. fror,l the control loc,ic 3~ is
also applied to the reset input of counter 36 in FIG. 3.
Therefore, upon the depression of every new key by the instru-
ment player, the counter 36 is reset. The counter 36 receives
from control logic 34 the sanle control inputs as the shift
register 32 and therefore, sequences in sync ~7ith the shiftins
of register 32. For example, if D. C. level signals are
originally received at inputs 15, I9 and I12 of shifter resister
32 and the resister shifts four times the input data is no~.. a~
shift register bit positions 1, 5 and 8 ~hich provide a ~. C.
level signal at output lines Sl, S5 and S8. The losic array
38 identifies the Sl, S5 and S8 pattern as a major chord patte-n
and provides an output on line Al. The logic circuit 40
provides an output signal on line ~ indicating a major
chord pattern and on line PF indicating that a chord pattern
is identified. The signal on line PF is received by the
control circuit 34. Referring to FIG. 4, the input to ~ID
gate 102 on line PF changes logic state indicating that a
pattern is found. The output of AND gate 102 on line 103
changes logic state to a logic 0. The change to a logic 0
state on line 103 causes the outputs of OR gate 114 and CR
gate 128 to change logic states to a logic 0. The shift
register 32 and the counter 36 are disabled. The output of
counter 36 on line DMC is a binary value indicating the number
of shifts or data moves necessary before a chord pattern is
recognized by logic array 38. Thus, for the above e~ample,
a signal output on line r~ indicates that a major chord
pattern is being played and the DMC or data move count output
.
1~37340
signal from counter 36 is the binary valuc 0100 which indicates
that four shifts were necessary to recosnize the major chord
pattern. ~rom this information, it is clear that the instru-
ment player is playing the E major chord.
If a major chord pattern is detected by prosrar~ed
logic array 38 without any shifts of data in register 32, the
counter 36 would have a binary output 0000 indicating that no
shifts were required and the chord identification would be a C
major chord. ~hus, the chord recognition function of the data
register 30 is normalized to the key of C. The musical chord
pattern is identified as a n;ajor chord pattern, a minor chGrc
pattern, or a seventh chord pattern. The number of shifts
required by the register 32 before a chord pattern is
identified represents the root or alphabetic note of the
identified chord pattern. Since the programmed logic array
38 is normalized to identify chord patterns and not specific
alphabetic chords, the size is greatly reduced without a
decrease in the identification capacity.
The counter 36 is an up-down counter which counts
to twenty-four in modulus twelve with a one bit carry. ~he
DMC output or data move count of counter 36 represents the
alpha~etic note of the recognized chord pattern and modulus 12 is
an appropriate mathematical number system for recognition since
there are only twelve notes in an octave. ~hen the counter 36
reaches the twelfth count and recycles to begin over, it pro-
vides a carry bit output which is connected to latch circuit 56.
The counter 36 continues to count to eleven 10000 through 1011)
for the second time. If the counter 36 recycles for the
second time, indicating that register 32 has shifted tt.enty-four
times, through all possible data input combinations, without the
- 3~ -
1137340
progra~ed lo~ic array 38 identifying a chGrd p3tterr, a second
earry bit is provided to latch circuit 56. ~he second carry
bit ehanges the output logic state of latch circuit 56 on line
SD to a logic 1. The bass note generation system now defaults
to a scanning mode of operation, fully explained hereinafter.
If the chord recognition portion of the input
data register 30 identifies a chord pattern, the signal on
lines b~ ' or S from logie eircuit 40 and the data move
count on line D~IC from modulus 12 counter 36 are used as
a partial address to read only memory 70 in FIG. 2. The
read only me~.ory 70 is a standard ~ors ~ell-known in the
art. The ROM 70 is programr.led to provide a digital value
representing a predeterr.lined sequenee of notes cr bassline
at its output, depending upon the input address. The
selection of the predetermined sequence of notes or bass-
line ean be ~ade by one of ordinary skill in the art,
depending upon musical taste and preference. The pattern
memory 70 also reeeives the output of ~eat counter 72 via
line BC. The ~eat counter 72 is a standard binary eounter
~hieh reeeives the output of an external tempo cloek on line
TC. In addition, the beat eounter 72 receives a reset sisnal
on line R. The line R is at a logie 1 which resets the beat
eounter 72 when the rhythm unit, standard in eleetronic organs,
eompletes a two measure interval or when there is a key down
signal from an external key do~n detector standard in electronic
organs indicating a complete hands-on/hands-off eondition as
distinguished from a legato key down signal. Thus, the beat
counter 72 is synchronized to the rhythm unit over a t~;o
- 39 -
li373~)
measure interval but is reset by the key do~m signal to
assure that each time a new chord is struck by an instrument
player that chord is accompanied by a root bass note thereby
providing the player or listener with information as to what
harmonic change has occurred.
As an alternative, the beat counter 72 is reset
upon every new alphabetic chord recognized by the chord
recognition portion of input data register 30. The ne~
alphabetic chord circuit 200 is shown in FIG. 7 and is
connected in parallel relationship to the reset line input
to beat counter 72. The digital value of the counter 36 on
line D~.C is applied as the input to new chord register 202.
If the chord recognition portion of the input data register
recognizes a chord pattern, the line PF from chord logic
circuit 40 in FIG. 3 is at a logic 1 state. The P~D gate 204
receives the line PF as a first input and the line ~7~
indicating that the system is not in the root/fifth mode as
the second input. Thus, when the system is not in the root/
fifth mode and a chord pattern is recognized, both inputs
to AND gate 204 are true or at a logic 1 state. The output
of AND gate 204 is applied on line 206 to new chord register
202, on line 208 to old chord register 210 and on line 212
to comparator 214. The line 206 is connected to the load
input of new chord register 202, line 208 is connected to
the load input of old chord register 210 and line 212 is
connected to the enable input of comparator 214.
Upon receipt o~ the load signal on line 206 from ~D
gate 204, new chord register 202 loads the binary value of the
data move count at its input lines and the load signal on line 208
from AND gate 204 simultaneously causes old chord register 210
- 40 -
1~37340
to load the binary value at the output lincs of new chord
register 202. ~ssuming thc new chord register was previously
empty, the binary value 0000 is loaded into old chord register
210. The output lines of both new chord register 202 and cld
chord register 210 are applied as inputs to comparator 214.
The enable signal on line 212 causes comparator 214 to compare
the binary value at its input. If the binary value fror old
chord register 210 matches the binary value fro~, new chord
register 202, the output of the comparator is a logic 0 state.
If the binary value from old chord register 210 does not
match the binary value from new chord resister 202, the
output of comparator 214 is at a logic 1 state. The output
of comparator 214 is received by one shot 216. ~pon receipt
of a logic 1 at its input one shot 216 provides a pulse output.
The output of one shot 216 is connected to the reset line P~
of beat counter 72.
~ach time a new chord is detected by the chord
recognition portion of input register 30, the line PF goes
to a logic 1 state and the new alphabetic chord circuit 200
functions as described above. If the same alphabetic chord
is played, the output of one shot 216 remains at a logic 0
state, however, if a new alphabetic chord is recognized, the
output of one shot 216 goes to a logic 1 state and beat
counter 72 is reset. It should be apparent to one of
2~ ordinary skill in the art that other variztions of the
source of a reset signal to beat counter 72 are possible
and within the scope of this invention.
- 41 -
li37340
The i~ or S address to pattern memory 70 deterrines
a particular group of possi~le bassline routines and the data
move count address selects one of three variations within each
group. If the data move count is between thc binary value 0
to 3, variation ~o. 1 is selected, between the binary value 4
to 7, variation ~o. 2 is selected and between binary value 8 to
11, variation ~io. 3 is selected. In the preferred embodiment,
sixteen bass notes form each precor:.posed bassline pattern con-
tained in memory 70. The beat counter 72 addresses the pattern
memory 70 to select the next musical timc slot of the me2sure
in which the pattern memory 70 provides a digital value bass-
line note output. The digital value of the bassline notes
forming each bassline pattern are stored in the pattern memory
70 in normalized form. Thus, the memory size is greatly reduced
and the alphabetic note or key information necessary to place
the bassline in the proper musical key is independently supplied
and fully explained hereinafter.
The output sender 140, illustrated in FIG. 5,
receives a signal on line PF f~om the chord recognition
portion of the data register 30 to indicate that a chord
pattern is recognized. The sender 140 also receives the
digital note value from the pattern memory 70 as inputs to
port 142 and the digital value of the data move count as
inputs to port 143. The bassline port 142 normally passes the
digital value signals from the pattern memory 70 unless
disabled as fully explained hereinafter. A port is a
standard device used in MOS circuits and is well-known
to those of ordinary skill in the art.
- 42 -
~37340
~ n enable memory 74 in FIG. 2, receives the output
of beat countcr 72 and proviàes an enable signal to the output
sender 140. T~e ena~le signal is received as the first input to
AND gate 164 in FIG. 5. The second input to AND gate 164 is the
line S~ from ~R gate 128 in FIG. 4. The line SR indicates
that the shift register 32 is not shifting. Thus, the output
sender 140 in FIG. 5 does not operate ~Jhen the shift register 32
is shifting. The output of the ~ND gate 1~ is received ky
counter 160 for triggering the serially gating of the binary
inputs to ports 142 and 148 to the input of adder 150 and is
also received by the decoder keyer circuit 18 to synchronize
the receipt of data. The AND gate 164 and the counter 160
comprise a timing control circuit. P serial adder 150
receives the digital note value from port 142 via OR gate 158
and the digital value of the data move count from root port 148.
Beginning with the least significant bit, the adder 150 combines
the digital note value from the pattern memory 70 and the disit21
value of the move count from the modulus 12 counter 36. The
digital value from the counter 36 on line DMC transposes the
digital note value from pattern memory 70 into the proper }:ey
for the bassline since the value of the data ~ove counter
corresponds to the root or alphabetic note of the recosnized
chord pattern.
The AND gate 162 receives at its input the line PF
indicating a chord pattern found and a line ~7~ indicating
$hat the system is not in the root/fifth mode of operation
as fully explained hereinafter. ~hen the inputs to AND
- 43 -
1137340
gate 16~ arc both at a lo~ic 1 StatQ, the serial adcler 150
receives the logic 1 state sisnal fron. ~ sate 162 and
truncates in a well-~nown r,~anner the most ci~nificant bit
of the binary addition. In the preferred embodiment, siY.teen
digital valu~s of bac,s notes are stored in the pattern memory
70 for each selectable bassline and if the counter 36 is, fcr
example, at a count of a binary value 8, the addition of the
binary 8 to the binary note value information frorm the patterr.
memory 70 must e~ceed a binary value 8. Thus, the playinc cf
a bass note b~ the decoder-keyer 18 represented by a value
less than binary 8 would be precluded. However, if a larse
binary value from pattern memory 70 is added to the data r.ove
count digital value and the fifth bit is truncated by adder
150, lower note values can be played by the decoder-keyer
circuit 18.
The enable memory 74 in the preferred embodirert is
a read only memory which is programr.ed to provide an enakle
output signal in accordance with the following code:
- 44 -
~13734~)
C ~ T 2
m
~0 ~ ~ t,
a ~ o o ~ r~ o a
~; ~ o o ~ ~ ~ ~ ~
BE ~T ~ P~ P~ ~ ~ H H
a ~ ~-- L Q; c ~ U~ H H H
COUNTER V~LI,'~ ~ m r.
v~ 3 ~ u~ m
0 1 1 1 1 1 1 1 1 1 1 1 1 1
0 0 0 0 0 0 0 0 0 0 0 0 0
2 1 0 0 0 0 0 0 0 0 0 1 1 0
3 0 0 1 0 0 0 0 0 0 0 0 0 0
4 1 0 0 0 0 0 0 0 0 1 0 0 1
0 0 0 0 0 0 1 0
6 1 0 0 1 0 1 1 0 1 0 1 0 1
7 0 0 0 0 0 0 0 0 0 0 1 1 0
8 1 1 1 1 1 1 1 1 1 1 1 1 1
9 O O O O O O O O O O O O O
15 10 1 0 0 o o o o o o o o o o
11 0 0 1 0 0 0 0 0 0 0 1 1 1
12 1 0 0 0 0 0 0 0 0 1 0 0 1
13 0 0 0 0 0 0 0 0 0 0 1 1 1
14 1 0 0 1 0 1 1 0 1 0 1 1 1
20 15 0 0 o 0 0 o 0 0 o 0 0 o 0
-- 45 --
~1373~0
The enable remory 74 in FIG. 2 receivcs tho output
from the beat counteL- 72 and if the syster, is operatin~ in
standard bassline, as describe(l ahcve, provide~s an er.able out~t
to sender 140 at beat counter value 0, 2, 4, 6, B, 10, 12 and
14. ~he remainder of the program code for the enable remory 7
is explained hereinafter. Thus, the disital b2ss note value
generator 1~ provides at the musical time slots determined
by the beat cour.ter 72 and en2ble memory 74 a digital bass
note value to decoder-keyer circuit 18 which co~prises the
serially added digital note value from pattern ~emory 70
and the digital value of the binary move count.
The standard bassline routine provided to the
decoder-keyer 18 can be r.lodified by the instrument player's
selection of one of a plurality of bass rhyt.~m patterns. In
the preferred embodiment, six bass rhythm patterns are
selectable by the instrument player from the rhythm unit
22 and, of course, if no bass pattern is selected, the~. the
standard bassline is used. In the preferred e~bodiment, the
selected bass patterns arc waltz, march 6/8, liverpool, samba,
blues rock and beguine, afro-latin or tango. ~he digital
note value for the bassline is still selected from the
pattern memory 70 by the chord type signal on lines ~ . or
S, the data move count on line D~1C and the input from beat
counter 72. However, the s~andard bassline routine is r~odified
by blanking or deleting selected time intervals during ~.hich a
serially added digital note value would normally be sent to decoder-
keyer circuit 18. For example, if the instrument player selec_s
the samba bass rhythm pattern, the bass rhythr, pattern on line
1~3734~)
P~5 addresses the enable memory 74. ~he enable remorY 74 no~
provides an enable signal to output sender 1~0 at be2t ccur.tcr
values 0, 6, 8 and 14 according to the samba basslirle code in
Chart 2. Thus, the standard bassline is modified by deletir.s
5 the enabling signal and consequently discarding the digital
note value obtained from the pattern mermory 70 at beat counter
values 2, 4, 10 and 12.
The bass rhythm pattern input in the beguir.e, a ro-
latin and tango rhythm on line B~6 is applied to both the
er.a~le memory 74 and the pattern memory 70 on line EAT. The
BAT line is an address to the pattern r,emory 70 which overrides
the r~ , or c address from the chord recognition portion of the
data register 30. In the preferred embodiment, the line B~,T
selects the fourth grcup of bassline patterns stored in pattern
mer.lory 70. The data move count input address to pattern r.er..ory
70 on line D~C operates ~ith the address line BAT and selects
one of three variations in the fourth group of precomposec
bassline patterns, as explained above. In addition, the data
move count on line D~lC addresses the enable memory 74 and selects
the timing sequence of BAT 1, BAT II or BAT III as set forth in
Chart 2 above. Thus, if the instrur..ent player selects one of
the BAT bass rhythm patterns, the signal input on line BAI to
the pattern memory 70 selects a group of programmed basslines,
the data move count on line DMC selects one of three variatior.s
in each group in pattern memory 70 anc the line BAT and line
D~IC address the enable memory 74 to select the musical time
slot at which a digital bass note value signal is provided,
as e~plained above, to the decoder-keyer circuit 1~.
- 47 -
11373~0
If the bass rhythm pattern of waltz on line BI'3 or
r,larch 6/8 is on line IP2 is selected by the instrurent player,
a signal is applied on line ~i.rl to the beat counter 72. In the
preferred er..bodi~ent, a signal on line I~M modifies the beat
counter 72 b5~ deletins or blanking in a manner well-kno~in to
those of ordinary skill in the art an output on line EC at
count values 6, 7, 14 and 15. The shortened beat counter
sequence is necessary for compatibility to the waltz and march
6/8 rhythm patterns.
In the second mode of operation, the bass note
generation system provides the r..usical root/fifth routir.e
output if an input data is a recognized chord pattern. The
root/fifth routine mode of operation is obtained in either
of two ways. First, the instrument player can close a switch
24 on the orsan console, illustrated in FIG. 1, which provides
a signal input to root/fifth memory 76 on line 25 in FIG. 2.
The root/fifth signal input on line 25 is also applied as an
address to the enable memory 74. The bass note generation
system now operates in the root/fifth mode as described
hereinafter. Second, the root/fifth mode is automatically
obtained by the instru~.ent player's selection of certain bass
rhythm patterns which, according to the following chart, do
not have an associated bassline:
C~ART 3
PATT~RN BASSLIN~ ~ ROOT/~I~T~
Blues/Rock ****** JSodifie~
March 6/8 ****** ~;odified
~altz ****** ~Sodifiec
Liverpool ~10dified Modified
Samba Modified ~10difiec
BAT BAT ~Sodifie~
No Input Standard Standarc
- 4~ -
113734~)
If thc systelll is not manually put in thc root/fift~
mode as described above and thc instrument player selects the
Blues/Roc~, r~arch 6/8 or t,altz bass rhythm pattcrn, the system
is automatically set into the root/fifth mode. The root/
fifth routine played by the decoder-keyer circuit 18 is
modified from the standard root/fifth routine as explained
hereinafter. If the instrumcnt player does not select a bass
rhythm pattern, then the standard root/fifth bassline routine
is played.
If the instrument player selects the root/fifth routine
by closing switch 24, the data register 30 still attempts to
identify a chord pattern from the input data signals. The nurber
of shifts of register 32 necessary to recosnize a chorâ pattern
is still provided on line DMC. ~he type of chord pattern
recognized is still indicated on lines M, t~' or S. However, the
root/fifth memory 76 provides an output sisnal on line R/F to
the output sender 140 indicating that the system is in the
root/fifth mode. The signal of line R/F is received as the
first input to ?70R gate 154 in FIG. 5. The output of ;7CR
gate 154 is connected to the disable input of port 142. ~he
port 142 is disabled when the disable input is at a losic
0 state. Thus, in the root/fifth mode, the preprogra~ed
bassline from the pattern memory 70 is not used.
- 49 -
1~37340
The root/fifth me~ory 76 reccives an input fron~ tl~e
beat counter 72. The root/fifth mcmory 76 providcs a rcot
enable output sic3nal on linc ~E for the stanclard root/fifth
routinc at thc beat counter value 0 and 8. The output of the
root/fifth memory 76 is set forth in the followin~ table:
CI~.RT 4
ROOT FIFTI~ (LO~-IIIGI~) TI~!ING
P~ ~
a o o
w
- ~a ~ ~ ~
z ~ ~ m
~E,~T
COUNTEP~ V.~.LUE 3
0
0 0 0 0 0 0 0
2 0 0 0 0 0 0 0
3 0 0 0 0 0 0 0
4 0 0 0 0 0 0 0
0 0 0 0 0 0 0
6 0 0 0 0 0 0 0
7 0 0 0 0 0 0 0
8 0 1 1 0 0
9 0 0 0 0 0
0 0 0 0 0 0 0
11 0 0 0 0 0 0 0
12 0 0 0 0 0 0 0
13 0 0 0 0 0 0 0
14 0 0 0 0 0 0 0
0 0 0 0 0 0 0
-- 50 --
37340
The root cnable sig~al is inverted and applied at
the disable input to port 144 in the output sender ldO in FIG. 5.
The port 144 is disabl~d upon receipt of a losic 0 state sicnal
at the disable input. The port 144 receives as the input
the binary value seven (0111).
The data move count on line DMC is received by port
148. The data move count from modulus 12 counter 36 is FIG. 3
represents the alphabetic note of the recognized chord or the
root note. Therefore, ~hen port 144 receives a losic 0 state on
the line RE indicating a root enable signal from the root~fift~
memory 76 at beat counter value 0, the port 144 is disabled.
The signal on line 25 from the root/fifth switch 24 also
addresses the enable memory 74. An enable signal from enable
memory 74 in FIG. 2 is applied as the input to ~ND gate 164
at beat counter value 0 as set forth in Chart 2 for standarc
root/fifth. The second input of the AND gate 164 on line SR
is at a logic 1 state. The logic 1 state output of ~D gate
164 is applied to counter 160 to enakle port 148 and to the
decoder-keyer circuit 18 to sync receipt of data information.
The data move count from port 148 is now applied to adder 150.
Since port 142 and 144 (as well as port 146 as fully e~plainec
hereinafter) are disabled, nothing is added to the digital value
of the data ~ove count. The decoder-keyer circuit lg receives
the digital bass note value representing the root note of the
recognized chord and plays a corresponding musical output.
11373~)
No~ at beat countor value 4, the root/fifth r~c~ori
76 docs not provide a loyic 1 signal on line ?~,, see C"art 4.
The fifth note port 144 reccives a logic 1 state sisnal on lifie
R~ and is not disabled. The enable mcmory 74 provides an enaLle
S signal at beat counter value 4, see Chart 2. The output of .~..,3
gate 16~ is at a logic 1 state and counter 160 enables ?ort 144
and port 148. The input to port 1~4 is the binary value seven
from any generator mear,s ~ell-known in the art. The bir.ary vlue
7 is applied through OR gate 156 and OR gate 158 to adder 15C.
The adder 150 enabled by counter 160 serially adds the binar-,~
value seven from port 144 to the data move count fror~ port 1~.
The addition of a binary value seven to the binary value of .he
root note or data move count results in the binary value
of the fifth note. Of course, the enable sisnal from
memory 74 is applied to the decoder-keyer circuit 18
to synchronize the receipt of the digital note value
representing the fifth of the recognized chord.
Also, since the system is operating in root/fifth, the
R/F input to AND gate 162 is at a logic 0 state which
removes the logic 1 from the output of gate 162. The
adder 150 does not truncate the most significant bit
in the serial addition.
The same operation as just described occurs at
beat counter values 8 and 12 respectively. Therefore,
a disital note value representing the root of the
recognized chord played by the organist is sent to the
decoder-keyer circuit 18 at beat counter values 0 and 8
- 52 -
~137340
and a digital note value reprcsenting the fifth of the
sare recognizcd chor~ is sent to the decoder-keyer circ~it
1~ at beat counter values 4 and 12.
~ o~., if the instrur,lent player selects one of the
bass rhythm patterns in C~art 3 which does not have an associated
bassline, the root/fifth routine is automatically selected. The
bass patterns of blues/roc}:, march 6/8 and t~altz dc no.
have bassline patterns and, therefore, a modified root/
fifth routine is played. The code for enable rerory 7~
provides the timing sisnals regarding enabling the out?ut
senner 140 and the code for root/fifth memory 76 provides the
root enable signal to output sender 140. Thus, if the
systeM is not manually placed in the root/fifth mode by
switch 24 and the instrument player selects the bass
rhythm pattern blues/rock, the system is automatically
placed in root/fifth mode. ~Jow at beat counter value 0,
the digital note value representing the root of the
recognized chord played by the organist is applied to the
decoder-keyer circuit 18 and at the beat counter value 8,
the digital note value representing the fifth of the same
chord is sent to the decoder-keyer circuit 18.
The instrument player may also modify the standarc
root/fifth routine by selecting one of the bass rhythm patterns.
Thus, if the syster is in the rcot/fifth mode of operatior. ard
the instrument player selects the liverpool bass rhythm
1137340
pattern at bcat counter value 0, the disital note value
representins the root of the recognized chord playeu hy
the organist is applied to the decoder-keyer circuit 1
and at beat counter value 8, the digital note value
representing the fifth of the same chord is applied to
the decoder-keyer circuit 18.
The third mode of operation for bass note generator
system is referred to as the bassline scan default mode.
In the scan default mode the system does not provide
a preprogrammed bassline musical output but provides
a bassline by scanning the keys actually depressed by the
instrument player and playing selected ones of these nGtes ir a
fiYed routine. The system is automatically placed in the
scan default mode when the shift register 32 has completed
a twenty-four step shift sequence and the progra~able logic
array 38 and chord logic 40 have not indicated a pattern match
on line PF. The modulus 12 counter 36 counts to a binary eleven
and recycles and provides a carry bit output on line CB. The
carry bit output of counter 36 is also received by latch circuit 56.
The counter 36 counts another complete sequence indicating
that all possible data input combinations from the keying
lines have been compared in programmed logic array 38 and
that no chord pattern is identified. The counter now
provides a second carry bit output to latch 56 which
provides an output signal on line SD indicating that the
system is now in the scan default mode of operation.
- 54 -
1137340
T~le output of the latch 56 on linc 'iD is applic~
as the enable signal to note counter 58 in ~IG. 3. The input
to note counter 58 is the lowest or first bit position in the
shift register 32. Therefore, as the shift register 32 ~.oves
to a new position containins a data kit ir the first bit
position the counter 58 counts in a binary two sequence.
The note counter 58 cooperatcs with the beat counter 72
ar.d comparator 60 to provide a comparison control sisnal to
control circuit 34. The operation of these circuits assures
that when the systei,l defaults into the bassline scanning rGce
of operation a fixed bassline pattern is followed. Furtherrore,
the operation of these circuits assures that if the syste~,
defaults into the scanning bassline mode of operation after
the beginning of the musical two bar phrase of the beat
counter, the first bass note selected from the input data
received by register 32 is the appropriate bass note for
that specific time slot in the fixed scanning bassline pattern.
In the scan default r.ode of operation, the bass
note generation system provides a bassline of eight
notes in a sixteen beat measure. Therefore, a note is played
at the beat counter value of 0, 2, 4, 6, 8, 10, 12 anc 14
The shift register 32 shifts downward for data filled bit
positions, at beat counter values 2, 4, 6 and 8 and shifts
up for beat counter values 10, 12, 14 and 16(0) so that t~.e
bassline pattern is recycled always returnin~ at beat
counter value 0 to the original kit position of register
32 at which input data is located. It should also be
- 55 -
1137340
apparent to onc of ordinary skill in the art that o~her
fi~ed bassline patterns can be selected for the scan dcfault
~odc. Thc notes played in the bassline pattern of the scan
default mod2 correspond to the keys held down by the
instrument player. If the register 32 receives data
at input lincs Il through I5, the scanning bassline
pattern is:
CHART 5
Data Bit 1 2 3 4 5 4 3 2 1 2 3 4
Beat Counter ~7alue 0 2 4 6 8 10 12 14 0 2 4 6
If the register 32 receives data at input lines Il anG I2, t~e
scanning bassline pattern is:
C~IART 6
Data bit 1 2 1 2 1 2 1 2 1 2 1 2
Beat Counter Value 0 2 4 6 8 10 12 14 0 2 4 6
If the system is in the scan default mode of operation,
and the beat counter value is 0 and the register 32 has receive2
input data on line T3, I9 and I15, the circuit 34 of FIG. 3
controls the operation of the system. Since the system is in
the scan default mode, the note counter 58 is enable2 by a
logic 1 state on line SD. The input to the note counter 58
is from the lowest bit position of the register 32 which
in the present example is empty. The note counter 58 is a
four bit counter which sequences upon receipt of a sisnal
from the register 32 indicating that the lowest bit position
has data. The counter 58 has an output of binary 0
upon receipt of the first signal from register 32
and sequences by binary two upon receipt of each
- 56 -
1137340
su~sequcnt signal fror.~ register 32. If the count valuc- ~
of counter 5~ is less than the binary value ~, a signal is
provided on line XL8 and if the count value ~ of counter
58 is greater than or equal to the binary val~e 8, a sisnal
is provided on line ~ 8. Both outputs from the counter 58
are received by a cor~parator 60 and by the control losic
circuit 34. The comparator 60 is a standard well-known
device which also receives the binary value of ~eat
counter 72 from FIG. 2. The comparator 60 provides
a signal output if the binary value of the beat counter
72 is ecual to the value of counter 58 or equal to the
value of counter 58 plus a binary value one. The output
of coMparator 60 is received ~y the control logic circuit 34.
The control logic circuit 34 in FIG. 4 receives
the scan default sisnal on line SD as the first input to AMD
gate 104. The second input to ~ND gate 104 is from counter 58
indicating that the value of counter 5~ is less than binary
eight. The third input to ~ND sate 104 is the line R/F
from root/fifth memory 76 of FIG. 2 inverted or r~/F. Since
in accord with the present example, the system is r.ot in the
root/fifth mode of operation the logic state of line R/F is
logic 0 and the input ~7~ to ~ND gate 104 is lecic 1 state.
The logic 1 state output of ~ND gate 104 on line 105 is applied
to CR gate 114 which provides a logic 1 state on its output line
D. The output line D of OR c;ate 114 is connected to shift
register 32 to control the downward direction of tlle shift.
1~3734~
~ h~ output fror~ D gatc 10~ is also applied as the
first in~ut to ,~ND gate 122. The second input to ;;iD cate 122 is
the line PF fro~ chord logic circuit 40 in ~IG. 3 inverted or ~ ar~
since the system is in the scan-default mo~e, no chord pattern
is found so line F~ is at a logic 1 state. mhe output fror~
gate 122 is applied as the first input to CR gate 124. m~ he out-
put of OR gate 124 changes state to a logic 1 and is applied ~s
the first input to ~ND gate 1 6. The second input to ~...D gate
126 is the output fro~ cor,parator 60 in FIG. 3. The output
of co~.parator GO is at a lcgic 1 state since the binary value
of the beat counter 72 does not equal the bir.ary value of the r.ote
counter 58 or the binary value of the note counter 58 ~lus cr.e.
Both inputs to AND sate 126 are true or at a losic 1 state ar.c
the logic 1 state output is applied to the input of CR gate 128.
The logic 1 state output on line SR from OR gate 128 is applied
to register 32.
The register 32 receives the logic 1 state sisnal
on line D from OR gate 114 and the logic 1 state signal on line
SR from OR gate 128 causing register 32 to shift in the dc~n~.~2rd
direction. The lines SR and D are also connected as ir.puts to
the modulus 12 counter 36 in FIG. 3 causing the counter 36 to
sequence in an ascending binary count.
The register 32 shifts once and the data input that
was originally received on lines I3, I9 and I15 is shifted to
2S data bit positions 2, 8 and 14. l'he inputs to the control
- 58 -
1137340
logic circuit 34 of ~IG. 4 ùo not change ar.d the register 32
receives the signals on lines SR and D and shifts aaair, in the
downwarc direction. This second shift of register 32 places
the dat~ received on input line I3 in the first or lowest ~it
position of the register 32. ~ signal frorl register 32 is
received ~y note counter 58 in ~IG. 3 indicating that the
first bit position is filled with data. The r.ote counter
sequences to binary 0000 value and since the register 32
shifts at a rate much greater than the tempo cloc~. controllir.s
the beat counter 72, the ~eat counter value input to corparator
60 is still at binary value 0000. The value of the note counter
58 is ncw equal to the value of the beat counter 72 and the
output of comparator 60 changes to a logic 0 state. ?he locic
0 state signal from comparator 60 is applied as the secor.d
input to ~MD sate 126 in FIG 4. The first input to A~D sate
126 from A~D gate 104 via Ai~7D sate 122 and OR gate 124 is
still at a logic 1 state. The output of .~.~D gate 126 chanaes
to a logic 0 state. ~11 inputs to OR gate 128 are in a logic
0 state and the output line SR of OR gate 128 is at a losic 0
state. The register 32 now receives a losic 1 state sisnal
on line D indicating the downward direction and a locic 0
state signal on line S indicating do not shift.
The modulus 12 counter 36 is stop~ed at data move
count value 0010. The ~inary value of the data rove count is
applied on line DMC as the input to port 148 in FIG. S. The
- 59 -
11373~0
system is in scan default operation so the logic 1 state sic-r.~l
on line SD is inverted by i~lOR gate 154 and disa~les port 142.
The enable memory 74 in FIG. 2 provides a binar~ output
signal at cach even beat counter value. The logic 1 output
of ~ND gate 164 is applied to enable counter 160 and to
synchronize the decoder-keyer circuit 18. The port 148 is
triggered ky t~.e output from counter 160 causing port la8
to begin sending data, the least significant bit first,
to serial adder 150 for transmission to the decoàer-
keyer circuit 18. The counter 160 is operated to count to
binary value 0100 upon receipt of an enable signal from the
enable merLory 74 in FIG. 2. The enable memory 74 operates
in the same manner as described above and a digital value
of the bass note corresponding to input line I3 is
received by decoder keyer circuit 18.
Now, after the beat counter 72 changes value to 0001,
the output of comparator 60 remains at a logic 0 state sir.ce
the binary value of the beat counter 72 equals the value of
the note counter (0000) plus binary one. Upon receipt of the ne~t
tempo clock pulse, the value of the beat counter 72 is 0010
which is not equal to the value of note counter 58 (OOC0) or
the value of note counter 58 plus one (0001). The output o,
comparator 60 now changes to a logic 1 state.
The output of ~ND gate 104 on line 105 is at a losic
1 state since all of its inputs, namely, the system is in t~.e
scan default mode, the value of note counter 5a is less than
- 60 -
1137340
binary ~ and the system is not in thc root/fifth mode are trLr
or at a losic 1. l`he output of I:~D gate 122 is at a loc,ic 1
state and the output or OR gate 12~ is at a logic 1 state
as explained above. The inputs to ~ND gate 126 are koth at
a logic 1 state. The logic 1 state output of I~ D gate 126
is applied as an input to OR gate 128. The output of C~
gate 128 changes state to losic 1. The register 32 no~;
receives a logic 1 state signal on lines D and SR and begirs
shifting in the do~nward direction.
The register 32 originally received data on lr.ru.
lines I3, I9 and I15 so register 32 shifts until the data
received on line I9 is moved to the first bit position.
The register 32 must shift the received data eight times
to move the data received on line I~ to the first dat2 bit
position. The register shifted twice to move the data
received on line I3 to the first bit position and now shi'tc
six additional times to move the data received on line I9 to
the first bit position. The note counter ~8 receives the sicn21
from register 32 indicating that the lowest bit position is
filled and counter 58 changes value to 0010. The output
logic state of comparator 60 changes to a logic 0 state
since the value of the beat counter 72 e~uals the value of
the note counter 58. The removal of the losic 1 state sicnal
from comparator 60 as the input of ~ND gate 126 disables the
register 32 from shifting. The modulus 12 counter 36 which
tracks the operation of register 32 is also disabled. ~he cata
move count of binary eight on line D~1C is processed by the
output sender 140 of ~IG. 5 as described above.
- 61 -
11373~
Thc beat count~r value no~ chancj~ value to G011
~hich produces no change in the ~yste~ opcration. ":he beat
counter 72 ~gain changes value to 0100 which is not equal to
the value of the notc counter 58 (0010) or the value of the
note counter 58 plus onc (0011). The output of comparator
60 is at a logic 1 state and is applied as the second input
to ,~,ND ~ate 125. The output of ~7D gate 104 is at a lcgic 1
state sincc all its inputs are true. The output of r ~'D ga~e
122 is also at a logic 1 state and is applied via OR gate 124
to the first input of ~ND gate 126. The logic 1 output of
A~D sate 126 is applied to OR gate 128. The register 32
receives the logic 1 signal on line D from OR gate 114 ar.c
the logic 1 signal on line SR from OR sate 128 as describec
above ar.d be~ins shifting in the downward ~irection.
The ne~t data input was originally received ky
register 32 at input line I15 and the register 32 now shifts
until the data bit received on line I15 is at the lowest bi.
position. The note counter 58 receives the si~nal indicating
that the lowest data bit position is filled and sequences to
value 0100. The value of the beat counter 72 now equals the
value of the note counter 58 and the output of comparator 60
changes logic states and control logic circuit 3~ disables
shifting. ~he register 32 must shift the received data a total
of fourteen times to move the data received on line I15 tc the
first data bit position. The modulus 12 counter 36 co~pletes
an entire counting sequence, produces a signal on carry bit
line CB and begins a new counting cyclc. The value of r~oD 1
counter 36 is binary 0010 and a signal on line C~.
- 62 -
113734~)
The output sender 140 of FIG. 5 reccives thc
logic 1 signal on line CD via NOR gate 154 to disable port
142. The logic 1 signal on line SD is also applied as the fi-s~
input to ~ND gate 152. The logic 1 state signal on line CB is
S ~pplied as the second input to ~D gate 152. The logic 1 state
output of .~ND gate 152 removes the normally disabling input to
port 146. The octave port 146 receives as its input the bi ary
value 12 fro.7~ any generator well-known in the art. ~n enable
signal at beat counter value 0100 is provided fro.~ enable
memory 74 in FIG. 2 via .7~ND gate 164 which enakles the
counter 160 and synchronizes the receipt of data by the
decoder-keyer circuit 18. The port 146 receives the
enable input from counter 160 and serially applies
the binary value 12, the least significant bit first,
through OR gates 15~ and OR gate 158 to adder 150.
The adder 150 also receives the data move count from
modulus 12 counter 36 via port 148 which is added serially
with the binary value 12. The digital value of the serial
addition is applied to the decoder-keyer circuit 18 as
described above. Further, since the system is not in the
pattern found operation, the output of gate 162 is at a losic
0 state and the most significant bit of the serial addition
is not truncated.
- 63 -
1137340
Th~s, as descri~ed above for the beat counter
valucs of binary 0, 2 and 4, th~ digital valuc representing
data received at input lincs I3, I9 and I15, respectively,
is applied to the decoder-keyer circuit 18. In the example,
the instrument player has onl~ depressed keys correspondins
to the data or keying lines D3, D9 and D15. Now, for a beat
counter value of binary 6 and 8, the digital value representing
data received at input lines I3 and I9 is sent to the
decoder-keyer circuit 18 following the same circuit operation
described above since the register 32 is shifting in the
downward direction. The value of note counter 58 is now
1000 and the value of the beat counter is 1000 and the data
received on line I9 is the lowest bit position of register
32. The beat counter 72 now changes value to 1001 but the
comparator 60 does not change its o~tput logic state since
the beat counter value 1001 equals the value cf note counter
58 plus one (1001). The beat counter value changes to 1010
which does not satisfy the comparison requirements and the
output of comparator 60 changes logic state to a logic 1
state.
In Fig. 4, AND gate 108 of the control circuit 34
receives at its inputs the logic 1 output state of line SD,
line ~7~ and line XM8. The output on line 109 of AND gate
108 is at a logic 1 state since all the inputs are true.
The output on line 105 of AND gate 104 is at c logic 0 state
since the input on line XL8 from note counter 58 is at a
- 64 -
1137340
logic O state. The logic 1 statc on linc 109 is applicd to
the input of OR gatc 112. The output on line UP o OR gate
112 is a logic 1 state and is received by the register 32 to
control the upward direction of shifting.
The output on line 109 of AND gate 108 is applied
as the input to AND gate '18. The second input to AND gate
118 is the line PF which in the scan-default mode of operation
is always at a logic 1. The logic 1 output of AND sate 118
is applied to OR gate 124. The logic 1 output of OR gate
124 is applied as the first input to AND gate 126. The
second input to AND gate 126 from the comparator 60 is at a
logic 1 state since the value of the beat counter 72 does
not equal the value of note counter 58 or the value of note
counter 58 plus one. The logic 1 cutput of AND gate 126
through OR gate 128 applies a logic 1 state signal on line
SR. The register 32 receives a logic 1 state signal on line
SR and a logic 1 state signal on line UP to begin the
register shifting in the up direction.
The next data bit moved into the lowest bit
position of the register 32 due to the upward shifting
direction is the data originally received at line I3 by
register 32. The note counter 58 receives a signal from the
shift register 32 indicating th~ receipt of data in the
lowest bit position and changes its value 1010. The data
move count from Mod 12 counter 36 corresponding to the
number of shifts from the initial position of the register
- 65 -
113734~)
32 is applied to output sender 140. The digital value
representing the bass note corresponding to input data D3 is
sent to the decoder keyer circuit 18, as described above.
The upward shifting of the register 32 is continued for beat
counter valucs 12, 14 and 0 in the same manner as described
above forming a bassline pattern as follows.
CI~ART 7
Data Bit 3 9 15 3 9 3 15 9 3
Beat Counter Value 0 2 4 6 8 10 12 14 0
The enable signal output from enable memory 74 in
Fig. 3 is modified depending upon the selection of the bass
rhythm pattern by the instrument player in the same manner
as c'escribed for the preprogrammed bassline cperation when
the input from the manual is identified as a chord pattern.
Thus, if the instrument player selects one of the bass
rhythm pattern inputs and the bass note value system de-
faults to the scanning mode, the time slots at which a
digital bass note value from output sender 140 is applied to
decoder-keyer circuit 18 is modified by blocking selected
2G time slots in accord with the pattern code set forth in
Chart 2.
If the instrument player has selected the root/fifth
mode of operation by closing switch 24 on the console and
the data register 30 does not recognize the key combination
depressed by the instrument player as an identifiable chord
pattern the system defaults to the fourth mode of operation,
- 66 -
113734~
a low-hish selcct bass note routine. In FIG. 2, th~; output
of root/fifth memory 76 on root/fifth line R/E is apl~lied to
the input data rcgister 30. The output cignal from the
root/fifth memory 76 on root enable line RE in accord ~,ith
the code of the memory set forth in Chart 4 above is ap?lied
to the input data register 30. The root enable line RE and
the root/fifth line R/F are also applied to the output
sender 140.
The control logic circuit 34 in FIG. 4 receives
the line RE and the line R/F and in the low-high select
routine and controls the scanning of the inputs to shift
register 32 to select the lowest data bit position filled
and the highest data bit position filled. If the instrume-.
player in accord with the above example depresses keys on
the lower manual placing a signal on keying lines D3 and D9
and D15 the low-high select routine will provide a digital
note value representative of the musical note corresponding
to the data or keying line D3 and the digital value representing
the musical note corresponding to the data or keying line
D15 at the time intervals controlled by the root/fifth
memory 76 and the ena~le memory 74 as explained above
regarding the root/fifth operation of the system when a
chord pattern is identified.
In a standard root/fifth pattern set forth in
chart 2 and at the beat counter value 0, the root/fifth
memory 76 provides a logic 1 output signal on the root
enable line ~E. The control logic circuit in Fig. 4 receives
- 67 -
1137340
as inputs to ~ND gate 106 thc lcgic 1 signal on line S~,
root enable line R~ and root/fifth line P~/F. Thc logic 1
output state of ~ND gate 106 on line 107 is supplied as ar.
input to OR gate 114. The output of GR gate 114 on line ~
is received by t~le shift recJister 32 to control the cownward
direction of shifting. The logic 1 output signal of AND
gate 106 on line 107 is also applied to the first input of
AND gate 120. The second input to ~.ND gate 120 is the line
SF. The control circuit 34 receives the input line SF frcr~
the shift register 32 indicating that the lowest data bit
position is filled as shown in FIG. 3. The line SF appliec
as the second input to AND gate 120 is at a logic 1 state
and in accord with the example indicates that the lowest bit
position or slot of shift register 32 is not filled. The
logic 1 output of the AND gate 120 is supplied as the input
to OR gate 128. The logic 1 output on line SR of OR gate
128 is received by the shift register 32 to control shiftins.
The shift register 32 receives the logic 1 output on line D
from OR gate 114 and the logic 1 output on line SR from OR
gate 128 to control the downward shift of register 32.
In the above exa~ple, when the data received on
line I3 is shifted into the lowest bit position of shift
register 32, a logic 1 signal is applied on line SF. The
second input line SF to AND gate 120 in FIG. 4 changes state
to a logic 0. The output of AND sate 120 changes to a losic
0 state and the output of ~R ~ate 128 changes to a logic 0
state disabling the shift register 32.
- 68 -
1~373~)
The output sender 140 in ~IG. S receivcs a lcgic 1
on line R/r as the second input to ~R gate 154 disablins
port 142. The data move count fror.l~IOD 12 counter 36 is
received as the input to port 148. The inverted root enable
S signal on line RL is at a logic 0 state and is applied to
disable port 144. Er.able memory 74 on PIG. 2 provides an
output signal on an enable line via ~ND gate 164 to cour.ter
160 to gate, least significant bit first, the binary value
of the data r.love count fro~ port 148 to serial adder 150 and
to synchronize the receipt of data at decoder-~eyer circuit
18. The digital value of the bass note corresponding to the
keying line D3 the lowest note actually depressed by the
instrument player is sent to the decoder-keyer circuit 18.
In addition to the above, the output of ~.ND gate
106 on line 107 is applied as the input to one shot multivibr~tor
130. The output of one shot multivibrator 130 on line 131
is a short duration pulse which is applied to the reset
input of bistable device 134. The bistable device 134
receives a clocking input from ÆND gate 132. The line '`D is
applied to the input of one shot 140 which provides a losic
1 pulse output which is connecte2 as the first input to AM~
~ate 132. The output of ~ND gate 110 on line 111 is inverted
by inverter 138 and applied as the second input to AND gate
132. The output of inverter 138 is a logic 1 state if the
system is in scan default, root/fifth and has a logic 1 on
the root enable line. The logic 1 ctate output of ~ND gate
- 69 -
~13734`~)
132 and the coincic~ental logic 1 out~ut of onc shot 130
applied respectively to the clock and rcset inputs of
bistable 134 change the logic state of thc Q output to loc3ic
1. However, the duration of the pulse output from the one
shot 130 on linc 131 is shortor than the operation of the
bistable 134 so that logic 1 signal on line Q is not coinci-
dental with the logic 1 pulse on line 131 at the input to
AND gate 136. Thus, the output of AND qate 136 is at a
logic 0 state.
Subsequent pulses on line 131 cooperate with the
Q logic 1 state of bistable device 134 and set the output cf
AND gate 136 to a ]ogic 1 state for the duration of the
pulse on line 131. The logic 1 output of AND gate 136 is
applied to the input of OR gate 128 and causes the shift
register 32 to sequence once. This one step sequencing c,f
register 32 is necessary if the lowest data bit position is
filled which renders the SF inputs to AND gates 116 and 120
at the logic 0 state thereby preventing shifting of the
register under their control. However, it is necessary to
skip the first pulse on line 131 if the system is in scan
default, root/fifth, and root enable line is at a logic 1
state and the lowest data bit position of register 32 is
filled. In this situation, the input data is already in the
lowest data bit position and no shifting is necessary to
reach the lowest frequency keying line input data. Therefore,
the first pulse on line 131 sets the Q output line of the
root skip logic circuit but does rot enable shifting of
register 32.
- 70 -
1137340
At the bcat countcr value 1, the root enable line
from root/fifth memory 76 in FIG. 2 returns to thc logic 0
statc. The control logic circuit 34 in FIG. 4 has as the
inputs to AND gate 110 a logic 1 state at line SD, line R/F
and line r~. The output of AND gate 110 on line 111 is
connected to the input of OR gate 112 providing a logic 1
state at the output line UP. The output line ~P of OR gate
112 is connected to the shift register 32 to control the
upward direction of shifting. The output of A~iD gate 110 on
line 111 is also connected to the first input AND gate 116.
The second input of AND gate 116 is line SF. Since the
lowest bit position of the shift register 32 is filled with
the input data originally received on line I3, the second
input to ~D gate 116 on line SF is at a logic 0 state. The
logic 0 output of AND gate 116 is applied as an input to the
OR gate 128. The OR gate 128 does not provide a logic 1
signal on line SR to enable register 32. However, the
output of AND gate 110 on line 111 is also applied as one of
the inputs to a one shot multivibrator 130 which upon
receipt of the signal on line 111 provides an output pulse
of narrow duration on line 131. The ouput line 131 of one
shot multivibrator 130 is connected to the reset input of
flip-1Op 134. In addition, the output of the one shot
multivibrator 130 is connected as the first input to AND
gate 136. The Q output of the flip-flop 134 is connected as
the second input to AND gate 136. The cloc~ input to flip-
11373~)
flop 136 is the output line of ~D gate 132. The A.~D sate
132 receives as inputs thc line SD and thc invcrted output
of AND gatc 110 on line 111 via inverter 138.
Thc Q output of flip-flop ~34 is normally in the
logic 0 state, and the ~ND gate 136 is off or has a logic 0
state output. However, as discussed above, at beat counter
value 0, the output cf AND gate 106 on line 107 was at a
logic 1 state which is applied as the input to one shot
multivibrator 130 which set the Q line of bistable de~icé
134 to a logic 1. Now, the logic 1 state on line Q is
applied as the input to AND gate 136 and the short duration
logic 1 pulse on line 131 due to the logic 1 state of line
111 fxom AND gate 110 is applied as the second input to ~D
gate 136. The logic 1 state output of AND gate 136 is
applied as an input to OR gate 128. The logic 1 output line
SR of OR gate 128 is received by register 32 to control the
shifting. The register 32 receives the logic 1 state output
of OR gate 112 on line UP and the logic 1 state output of OR
gate 128 on line SR causing the register 32 to sequence
once. The short duration pulse from one shot 130 falls and
the control circuit 34 disables register 32. However, the
register 32 has shifted once in the upward direction removing
the data from the lowest bit position of register 32. The
inputs to AND gate 116 are now both true or at a logic 1
state. The logic 1 output of AND gate 116 is applied as en
input to OR gate 128. The logic 1 output of OR gate 128 and
the logic 1 output of OR gate 112 enable the register 32 to
begin shifting in the upward direction.
- 11373~
In accord with the above example, the shift
register 32 will continue shifting in an UP directio~ until
the data originally received on line I15 is shifted to the
lowest data bit position. When the data originally received
on line I15 is shifted to the lowest or first data bit
position, the line SF applied as the second input to A~7D
gate 116 changes logic state and removes the output sisnal
from AND gate 116 which via OR gate 128 disables the shiftins
of register 3~.
While it is necessary that the register 32 does
not shift when the system is first placed in the scan-
default mode of operation and the lowest data bit position
of the resister is filled since the data in the lowest bit
position of register 32 corresponds to the low note select.
However, it is subsequently necessary to step the register
32 once to remove the data from the lowest bit position to
enable the system to alternate between the lowest and
highest data bit positions.
The data move count from modulus 12 counter 36 is
applied as the input to port 148 in FIG. 5. Furthermore,
since the r:odulus 12 counter 36 is counting in the UP or
reverse direction, the counter 36 begins counting upward
from its previous position corresponding to the shifting of
register 32 to provide the originally received data bit on
line I3 in the lowest bit position. Thus, with the data
originally received on line I3 in the lowest bit position of
- 73 -
113734~
register 32, the valuc of t~OD 12 counter 36 is bir.ary 0010.
The register 32 shifts in the up direction and .~GD 12
counter 36 parallels this operation. ~fter the co~ntcr 3~
sequences from the 0000 count and the directior. control is
in the UP position, a carry bit signal is received on line
CB and the counter begins counting do~nward from its top
count binary 11. Thus the data move count of ~;OD 12 counter
36 when the lowest data bit position is filled with the data
originally received on output line I15 is a binary 0010 plus
a carry bit. In FIG. 5, the AND gate 152 receives an input
signal on line SD anu an input signal on line CB changir.c
the output of ÆND gate 152 to a logic 1 state and removina
the disable signal from port 146. In the standard root/fift~.
pattern at beat counter value 4, the enable memory 7a in
FIG. 2 provides an enable output signal which is connected
via A~D gate 154 to counter 160 to enable ports 1~6 and 148
to begin passing the serial data bits to serial adder 150
and to synchronize receipt of serial data by decoder-keyer
circuit 18. The adder 150 provides a digital bass note
value representing the note corresponding to keyina lir.e
D15, the highest note actually played by the organist to the
decoder-keyer circuit 18.
In the standard root/fifth routine which has
defaulted to a low-high routine, the enable memory 76 in
FIG. 2 provides an enable output signal at the counter value
~, 4, 8 and 12. This enable line output se~uence coupled
with the output sequence for the standard root/fifth of
- 74 -
1137340
root/fifth memory 76 of ~IG. 2 provides a lct~ note select at
the beat counter value 0, l~igh note select at the beat
counter value 4, the low note at the beat counter val~e P
and the high note at the beat counter value 12. Further-
more, as discussed above for the other modes of operation,the low-high routine in the standard root/fifth patterr. may
be modified by the instrument player's selection of one of
the bass rhythm pattern inputs to the root/fifth memory 76
and the enable memory 74.
If the system is in the scan default mode of
operation and the value of the beat counter 72 is a kinary 4
indicating that the system was set into the scan default
mode of operation during the course of a musical measure as
opposed to the beginning of the musical measure, it is
desirable to have the system play the bass note that is
normally played in the scanning bassline system at that
particular point in the musical measure. Assuming that the
instrument player depresses keys corresponding to keyir.g
lines D3, D9 and D15 as in the previous examples. The
system is placed in the scan default mode ~y having the
modulus 12 counter 36 complete one cycle, provide a carry
bit output on line CB and a set signal to latch 52 ar.d then
cycle a second time, provide a second signal to latch
circuit 56 which responds by providing a logic 1 signal on
line SD. The note counter 58 is enabled by the logic 1
state on line SD.
113734~
The control circuit 34 of ~IG. ~ receives as
inputs to ~ND gate 10~ a losic 1 on the line SD, a logic 1
signal on the line ~/~ and a loc;ic 1 on the line ~L8. mhe
logic 1 state output on line 105 of l!~D gate 104 is applied
S as an input to the ~R gate 114 providing a logic 1 signal on
the output line D to control the downward direction of the
shift register 3 The output line 105 of ~D gate 104 is
also applied as the first input to ~ND gate 122. ~he second
input to A`~D gate 122 is the line PF indicating that the
system has not found a chord pattern on the input data. The
logic 1 output of A~D gate 122 is applied as a first input
to OR gate 124 and the output of OR gate 124 is applied as a
first input to AND gate 126. The second input to A~ID g2te
126 is the output of comparator 60 in FIG. 3. If the output
of comparator 60 is in a logic 1 state the output of A~D
gate 126 ~ill be in logic 1 state providing a logic 1 output
from OR gate 128 on line SR. The comparator 60 in FIG. 3
receives the beat counter value and compares that value to
the value of the note counter 58. Therefore, in the above
example, if the shift register 32 receives the data input on
lines I3, I9 and I15 at beat counter value binary 4 the
output of cor.lparator 60 is at logic 1 state. The shift
register 32 receives a logic 1 signal from the output of ~R
gate 11~ on line D and a logic 1 signal on the output of OR
gate 128 on line SR to control the shifting of the register
in the downward direction.
- 76 -
11,37340
Thc data bit oriqinally reccivcd on input linc I3
is shifted to the lowest bit position in thc register 32
which provi~ s a count output signal to notc countcr 58
making thc output of note counter 58 a binary value zero.
The output of comparator 60 remains at a logic 1 state since
the value of the note counter 58 or the value off the note
counter plus binary one does not equal the beat counter
value binary 4. The shift register 32 continues to shift in
the downward position and the data bit originally received
on line I9 is shifted to the lowest bit position in register
32 which provides a signal to note counter 58. The note
counter 58 changes its output ~alue to a binary value 2.
The comparison criterion is still not satisfied and the
logic 1 state output of comparator 60 remains. The shift
register 32 continues to the sequence in the downward
direction and the data bit originally received on line I15
reaches the lowest bit position providing an output signal
to note counter 58. Note counter 58 changes its output
value to a binary value 4. The value of the note counter 58
is now a binary 4, and the value of the beat counter 72 is c
binary 4. The output of comparator 60 changes state to a
logic 0 state since the comparison requirement is satisfied.
The output of AND gate 126 in ~IG. 4 changes state to a
logic 0 and the output of OR gate 128 on line SR changes to
a logic 0 state disabling the register 32 from shifting.
The above sequence of shifting on register 32 is completed
before the ~eat counter 72 increases its value since the
speed of register 32 is much greater than the tempo input
signal to beat counter 72.
1137340
The output sender in FIG. 5 receives the data move
count cs the input to port 148 and since thc Modulus 12
counter 36 has recycled moving the original input data
received on line S15 to the lowest data bit position a logic
1 carry bit output is on line CB and is received by the
output sender 140. The ~ND gate 152 receives the logic 1
signal on the line CB and the logic 1 signal on line SD in-
dicating that the system is in the scan default mode of
operation. A logic 1 signal at the output of AND gate 152
removes the disable signal from port 146. Since the system
is still at beat counter value binary 4 an enable signal
from enable memory 74 in FIG. 2, is applied as an input to
AND gate 164. The output of OR gate 128 on line SR is now
at a logic 0 state since shifting of register 32 has ceased.
Thus the line SR input to AND gate 164 is at a logic 1
state. Both inputs to the AND gate 164 are true or at a
logic 1 state. The logic 1 state output of AND gate 164 is
applied to the counter 160 to gate the bits of the data move
count from port 148 and the bits of the binary 12 value
input from port 146 and to synchronize receipt of data by
decoder-keyer circuit 18. The bits from the binary 12 value
and the binary value of the data move count are serially
added at adder 150. The digital note value representing the
note corresponding to an input signal on line 115 is sent to
the decoder-keyer 18 at beat counter value 4. Therefore,
the same note will be generated at beat counter value 4 as
if the system was put into a scan default at the beginning
- 78 -
1137340
of b~at counter 72 two measure sequence. The systcm now
continues to opcrate in thc scanning basslinc modc for beat
countcr values binary ~, 8, 10, 12, 14 and 0 as described
above.
The instrument player ~ay manually place the
system in the scan default mode of operation by closins a
switch or tab 62 illustrated in FIG. 3. The logic 1 state
signal obtained by closing switch 62 is inverted by inverter
64. The loyic output of inverter 64 on manual scan default
line ~ISD is connected to the Eattern found line PF from
chord logic circuit 40. The logic 0 state of line ~SD holds
the line PF at a logic 0 state even if a chord pattern is
recognized by programmed logic array 38. The input line
PF to ~D gate 102 in FIG. 4 remains at a logic 0 state and
the register 32 completes an entire shifting cycle. The
modulus 12 counter 36 completes two cycles of counting and
via latch circuit 56 provides a logic 1 state signal on scan
default line SD. The system continues to operate as described
above for the scan default modes of operation.
FIG. 6 is a partial block diagram c,f the decoder-
keyer circuit 18. The decoder-keyer 18 receives the signals
from the digital bass note value generator 14 and provides a
corresponding musical output. In an optional mode, the
decoder-keyer 18 receives inputs directly from the pedal
clavier and provides a high select pedal musical bass note
output.
- 7g -
~37340
In the prcfcrrcd cmbodiment, the cn~blc signal and
thc serial data from tl~c digital note valuc gencrator 14 are
received by serial to parallel converter 170. The opcration
of the bass note generator 18 docs not depend upon the mode
of operation of the digital note value generator 14. Thus,
whether the serial data is a precomposed bassline, a root/fifth
routine, a scanning bassline or a low-high routinc, the
series to parallel converter 170 when enabled by the synch-
ronize enable signal from the digital note value generator
14 converts the serial data into paIallel digital data.
Series to parallel converters are well-known in the art and
any standard converter is suitable. The parallel binary
value output of converter 170 is applied as an address to
selection multiplexer 172.
The selection multiplexer 172 also receives as
inputs the twelve frequency signals from the top octave
generators or MDD devices which are well-known in the
electronic organ industry. The address received by selection
multiplexer 172 from the output of converter 170 determines
which multiple derivative divider (MDD) input is selected.
The output of selection multiplexer 172 is received by a
chain of dividers 180 which divide the MDD signal frequency
down to the bass note range. The output of the divider
chain 180 is received by the standard stairstep keyer
circuit 182 to provide a musical output signal. As is well-
known in the art the musical output signal is either 8'
pitch or 16' pitch.
- 80 -
1~37340
The read only memory 178 receives a signal on linc
P/~ from the instrument console indicating that the d~codcr-
keyer 18 is operating in the serial data mode. The enable
signal from the digital bass note value generator 14 is
received ~y ROM 178 to indicate that serial data is being
received. The ~O~1 178 receives an input line SB from a
switch or tab on the organ console which is usually O~.
Upon receipt of an enable signal, the ~O~. 178 provides a
signal on line PC to a time constant trigger circuit 190
which is well-known to those of ordinary s]cill in the art.
The time constant trigger circuit 190 also receives a signal
on line P/W indicating that the decoder-keyer 18 is operating
in the serial data mode and the time constant trigger
circuit 190 also receives the sigr.al on line SB. The time
constant trigger circuit 190 provides a pulse output signal
on line E of approximately 20 ms. which is received by the
re~aining standard organ circuitry for generating a D. C.
waveform envelope. The keyer circuit 182 receives from the
standard organ circuitry such as a capacitive discharge
device a D. C. waveform envelope which is used to amplitude
modulate the stairstep keyer circuit as is well-known in the
art. The envelope keyer signal is now percussive in nature
to provide percussive output notes.
If the optional one finger chording system is
unused, the line SB is connected to the standard organ key
down detector. Upon receipt of an enable pulse, the RO.'~ 178
provides a signal to time constant circuit 190 which also
_ 81 -
1137340
receives a logic 0 on line SB due to the ~ey down detection.
The time constant circuit 190 provides a constant level
output signal on line E until the depressed key is released
and the line ~B returns to a logic 1 state. The keyer
circuit 182 receives from the standard organ circuitry a
D. C. level waveform and the musical output remains at a
steady state for as long as the key remains depressed.
The musical bass note output is in one of two
octaves as decided by the digital bass note value generator
14. The output lines of converter 170 corresponding to the
binary value of 4, 8 and 16 are sent to a second octave
circuit comprising PND gate 174, OR gate 176 and read only
memory 178. The output lines of converter 170 corresponding
to binary value 4 and 8 are applied as input signals to the
AND gate 174 and the output line corresponding to binary
value 16 is applied to the input of OR gate 176. The output
of AND gate 174 is applied as the second input to OR gate
176. If the output binary value of converter 170 is greater
than the binary value 12, a logic 1 is at the output of OR
gate 176 indicating that a note in the second octave is
selected. The output of OR gate 176 is applied to read only
memory 178 which provides an output signal on cut line C
which is received by the divider chain 180. The output from
read only memory 178 on line C disables one of the dividers
thereby doubling the frequency of the note selected and
raising the note by one octave.
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1137340
The read only memory 178 also receives an input
from the second octave switch on the instrurent console. I r
the second octave switch is O~F, the system operates as
above. ~owever, if the second octave switch is ~, the RO~
178 prohibits an output signal on line C to divider 180 from
double the frequency regardless of the logic level output
from OR gate 176.
The decoder-keyer circuit 18 also provides the
alternative operation of playing the highest manually
selected pedal note by the depression of one of thirteen
pedals by the instrument player. If the instrument player
closes a switch or tab (not shown) on the console, the RO~I
178 receives a sisnal on line P/~ indicating that the system
is operating in the optional pedal mode. The RO~ 178
provides a clear signal on line l91 to converter 17C to
assure that no serial data is provided to the selection
multiplexer 172. During the high select manual pedal
operation, the serial data or walking bass mode of operation
is not operative.
The depression of a pedal by the instrument player
places a D. C. level voltage on a corresponding one of the
pedal lines Pl through P13. The pedal lines are connected
as input signals to the input actuator 184. The input
actuator 184 provides a key down output signal to the read
only memory 178. The input actuator 184 provides a ~ey
down signal when any pedal is depressed by the instrument
player regardless of whether other pedals have been depressed
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1137340
an~ retained down. The data output of the input actuator
184 is received by the multiplexer circuit 186. ~hc scanner
188 continuously sequences in the manual pedal mo~e of
operation and provides an address signal to multiplexer 186.
The digit~l ad~ress signal to multiplexer 186 interrogates
the highest frequency value pedal line P13 to determine if a
D. C. level voltage is present on line P13. T~.e scanner 188
sequences through each binary address signal until a pedal
line P13 through Pl is detected with a D. C. level voltage
signal. ~7hen the binary value of scanner 188 corresponds to
a pedal line with a D. C. level voltage, the output of
multiplexer 186 indicating that a match has been located is
applied to the read only memory 178. The read only memory
178 provides an output signal on Line L to multiplexer 172
an~ divider 180 to load the address data and cut information
respectively. The read only memory 178 upon receipt of the
signal on the match line ~1 after loading as described above
resets the scanner to the highest digital value and scanning
im~.ediately resumes.
Upon receipt of the load signal on line ~ from RO';
178, the binary value output of scanner 188 is loaded into
multiplexer 172 which has a binary storage or latch capability.
The digital value of the scanner 188 selects which top
octave generator or multiple derivative divider is necessar~
to ultimately provide the bass note output signal. The
~ output of multiplexer 172 is applied as an input to divider
chain 180 which divides down the multiple derivative divider
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113734~
frequency to the bass note range. The output of divi~er
chain 180 is applicd as an input to the standard keyer
circuit 18'.
If the string bass s~itch is in the OFF posit~on
up receipt of the key down signal from actuator 184, RG~ 17~
provides a signal to time constant trigger circuit 190. ~e
time constant trigger circuit 190 provides a D. C. level
sisnal to the standard organ circuit which provides an
envelope input to keyer 182 as described above. If the
string bass switch is ON and the ROM 178 receives the key
down signal, the time constant trigger circuit 190 which
also receives the line SB provides a pulse output. The
pulse output is received by standard organ circuit such as a
capacitive timer which provides a percussive input to ~.eyer
circuit 182. The output of the keyer circuit 182 is the
bass note pedal frequency selected by the instrument player.
.he output from scanner 188 is fed back on line
189 to the read only memory 178. If the digital value of
line 189 corresponds to a binary 13 value and the read only
memory 178 receives a match signal on line ~ from the
multiplexer 186, the highest frequency pedal P13 has been
depressed by the instrument player. The read only ~.,emory
178 provides an output signal on line C to the divider chain
180 to eliminate one divider element and thereby double the
frequency or increase the octave by one. The second octave
input to the RO~ 178 in the manual pedal mode can be used
to double the frequency of the pedal inputs and thereby prc-
vide for receipt of a twenty-five pedal clavier.
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113734~)
Thc instrumcnt playcr opcratcs thc bass notc
generator 18 in thc manual high pcdal sclect mode of opcration
so that a bass notc corrcsponding to thc highest pcdal
selected by the instrumcnt player is played. If the instru-
ment player inadvertently depresses two pedals since the
system scans from the highest to the lowest value, only the
highest value pedal is selected.
It is to be understood that the present disclosure
is to be interpreted in its broadest sense and the invention
is not limited to the specific embodiments disclosed.
Furthermore, the embodiments set forth can be modified or
varied by applying current knowledge without departing from
the spirit and scope of the novel concepts of the invention.
Having described the invention, what is claimed
is:
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