Note: Descriptions are shown in the official language in which they were submitted.
~137535
INK DROP COMPENSATION sAsED ON
DYNAMIC, PRINT-DATA BLOCKS
Description
Field of the Invention
This invention relates to an apparatus for correcting
the flight path of an ink drop in an ink jet printer
to obtain precise printing. More particularly, the
invention relates to correcting the flight path of
ink drops to compensate for the effects of charge
repulsion between ink drops, induced charges on the
ink drops and aerodynamic drag on the ink drops.
Background Art
The three effects that can change the flight path of
an ink drop in an ink jet printer are charge repulsion
between drops, charge induction between drops and
aerodynamic drag. The ink drop is charged as it
breaks off from the ink stream. This is typically
accomplished by grounding the ink, which is conductive,
and surrounding the ink stream at the drop breakoff
point with a charge ring connected to some predetermined
voltage. The voltage between the ink stream and the
charge ring creates electrical charges in the ink
stream which are trapped in the drop as the drop breaks
off from the stream. The magnitude of this charge
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trapped on the drop i5 used to control the flight path
of the drop by placing an electric field in the flight
path to deflect the charged drop. Thus, a change in
the voltage potential applied to the charge ring can-
change the charge in the drop and the ~light path ofthe drop.
Charge induction errors in the flight path are caused
by previously charged drops in the vicinity of the
drop breakoff point inducing a charge on the drcp
currently breaking off. The charge placed on a drop
is predominantly controlled by the charge ring but an
error charge can be placed on the drop due to a
previously charged drop near the drop breakoff point.
The error in charging the drop then causes an error in
the flight path of the drop to the print media.
The charge repulsion error effect is created by drops
of the same charge repelling each other as they fly
towards the print media. The repelling forces between
the drops change their flight paths and thus change
the point at which the drops strike the media creating
an error in printing.
The aerodynamic drag on a drop can change the flight
time of a drop to the print media. The faster the
print media is moving relative to the drop stream,
then the greater will be the errors in print position
due to changes in flight time of a given drop. The
amount of drag experienced by a drop depends upon the
pattern of drops flying in front of the print drop or
reference drop.
Each of the above three effects can create errors in
precision ink jet printing. Which effect is dominant
largely depends on the distance from the drop breakoff
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point to the print media and the relative velocity
between the lnk drops and the print media. If the
velocity of the print media is slow relative to the
ink drop velocity the predominant errors in printing
are due to charge induction and charge repulsi~n. As
the flight time of ink droplets increase and as the
velocity of the print media relative to the droplets
increase, aerodynamic drag becomes the more pre-
dominant source of error in printing. This is espe-
cially true in a binary ink jet system using unchargeddrops as the print drops and charged drops as the
gutter drops. Since the uncharged drops are the print
drops the error effects due to induced charges and
charge repulsion are small compared to the errors due
to the aerodynamic drag on the drops.
In addition, the error effect of induced charges or
charge repulsion is limited to substantially the three
or four drops immediately in the vicinity of the ref-
erence drop. It is known for example that the charge
induction effect falls off nonlinearly with distance
from the reference drop (drop breaking off). The fourth
drop away from the reference drop is the last drop that
usually needs to be considered (for example, see U.S.
Patent 4,032,924, issued to Takano et al on June 28,
1977). Similarly, the charge repulsion effect between
drops decreases as an inverse function of the squared
distance between the drops. Thus, the charge repulsion
effect on print error need be considered only for drops
immediately in the vicinity of the reference drop.
On the other hand, the aerodynamic error effect, when
it is predominant has been found to be a long term
effect. In some situations drops in excess of 30 drop
positions in front of the reference drop can have an
effect Oll the aerodynamic drag OIl the reference drop.
.
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Examples of apparatus compensating for induced charges
are taught in U.S. Patents 3,631,511 and 3,789,422.
The Keur et al Patent 3,631,511 issued on December 28,
1971, teaches correcting the reference drop for induced
S charge from the immediately preceeding drop. The
Haskell et al Patent 3,789,422 issued January 2~,
1974, teaches compens~ting for charge effects based
upon any number of previously charged drops.
U.S. Patents 3,828,354 and 3,946,399 teach compensating
for the error effects due to charges and aerodynamic
drag. The Zareski Patent 3,946,399 issued on March 23,
1976, teaches monitoring the data pattern for an ink
jet stream to detect particular print data patterns.
These print data patterns are then logically analyzed
to select a compensation charge signal to be applied
to the charge ring. The Hilton Patent 3,828,354
issued on August 6, 1974, teaches monitoring a seven .
bit print data pattern to generate the compensation
signal for aerodynamic and charge induced effects.
Hilton monitors four drops ahead of the referenae drop
two drops behind the reference drop and the reference
drop itself, Based upon the binary pattern for these
seven drops, Hilton addresses a read-only-store memory
which contains predetermined compensation values for
each possible address.
None of the above patents teach compensating for the
relatively long term aerodynamic drag effects. One
problem in trying to correct for such effects is the
number of patterns to be corrected for. If drops as
far as 30 drop positions away from the reference drop
have an effect, then the number of possibilities
requirillg correction are 23. Clearly storing a
charge compensation value for each and every pos-
sibility is not practical.
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The basic solution to the above problem is to compensate the
reference drop for each and every drop in the immediate
proximity to the reference drop and to summarize the effect
of groups of drops more remote from the reference drop. Em-
bodiments of this basic solution to the problem are shown inFIGURES 1, 2, and 3 herein. However, further improvement of
print quality can be achieved with the same limited memory
space if tradeoffs are made between print data patterns
taking into account the print error distribution produced by
the pattern combinations.
Summary of the Invention
It is the object of this invention to correct the flight
path of an ink drop to achieve the highest quality of print-
ing appearance with a predetermined system limit on the
quantity of compensation values available to correct the
flight path of the drop.
In accordance with this invention, the above object is ac-
complished by monitoring the print data pattern and dynami-
cally selecting the one of a plurality of print data blocking
or grouping techniques to determine the compensation effect
to be used to correct the flight path of the ink drop. In
one mode, the correction is based only on individual drops
in close proximity to the reference drop. In one mode, the
correction is based only on individual drops in close
proximity to the reference drop. This mode is used when a
high percentage of the drops close to the reference drop
will be flying in the same path as the reference drop to the
print paper. In another selectable mode, the effect of
drops in close proximity to the reference drop are individ-
ually corrected for and the more remote drops are correctedfor as a single large block. In yet another selectable
mode, the more remote drops instead of being corrected for
as a large group are
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divided into sub-blocks and the effects of the drops in the
sub-blocks are corrected for. Where the more remote drops
are grouped as sub-blocks, the correction is based upan the '
pattern of print data that acts as a link or a bridge~be~
5 tween the remote drops and the drops in close proximity to -~
the reference drop.
The great advantage in dynamically selecting print data
blocks for correction effects is that storage space cOnsumed
to store correction values for~patterns producing little or
10 no error can now be reallocated~to store correction values ~ -
for patterns producing a large~error. In other words, in a
situation where many of the drops in close proximity to the
reference drop are flying in the same flight path they will ~-
tend to isolate the reference-drop from the effects of more
remote drops. Accordingly, there are fewer combinations of
print patterns producing a sizable error that need to~be
taken into consideration and stored as correction values.
The storage locations, which~arè saved, can be used to store
compensation values for patterns where the more remote drops
have~a stronger effect on~the flight path of the reference
drop.~ As a result for the same stored quantity of correc-
: tion values, a higher print quality appearance~can beachieved by dynamically selecting the correction modes based
on print data.
::~
Brief Description of Drawings
::'
FIGURE 1 shows one embodiment of the invention, wherein the '~
print data for the drops more remote from the reference
print drop are grouped into three blocks of increasing size
to reduce the number of print data patterns compensated for.
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FIGURE 2 shows one example of logic that can be used to
implement the block B logic in FIGURE 1.
FIGURE 3 shows a simpler alternative embodiment of the FIG-
URE 1 in~entio}l wherein only one block of remote print
s data is combined to reduce the print data patterns used
to retrieve the compensation signal to be applied to
the charge electrode.
FIGURE 4 is a graph of print error distributions for
different size data pattern samples.
FIGURE 5 shows one embodiment of the present invention
wherein the grouping of print data is dynamically
changed depending upon the print data patterns.
FIGURE 6 shows the embodiment of FIGURE 5 in more
détail.
FIGURE 7 shows another embodiment of the present
invention using a computer to implement the grouping
or blocking of print data patterns for compensation
effect,
FIGURE 8 is a timing diagram with examples of waveorms
appearing in the embodiment of FIGURE 7.
FIGURES 9 and 10 show program flow diagrams indicating
program control for the computer in FIGURE 7 to
implement the dynamic grouping or blocking of print
data patterns of FIGURE 5.
Detailed Description
In FIGURE 1, ink jet head 10 is printing on a media
mounted on drum 12. As drum 12 rotates ink jet head 10
is indexed parallel to the axis of the drum so as to
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print the entire page mounted on the surface of the
drum 12. Ink in the head 10 is ~under pressure and
thus issues from the nozzle 14 as an ink stream~ In
addition, a transducer in the head 10 provides a
vibration in the ink cavity inside head 10. This
vibration or pressure variation in the ink causes
the stream 16 to break-up into droplets.
The transducer in head 10 is driven by drop generator
driver 17. The clock signal applied to driver 17
controls the frequency of the drops and the drop
period--distance between drops. To synchronize the
system, the clock signal is also applied to the shift
register 30 and to the drum motor driver 19. Shift
register 30 is shifted by the leading edge of the clock
signal. The speed of dr~m 12 and motor 21 is held
steady to the clock by feedback from tachometer 23
through phase locked loop circuit 25 to motor driver
19 . . .
:
Charge ring 18 surrounds the ink stream 16 at the
point where the ink stream breaks into droplets.
Nozzle 14 and ink 16 are electrically conductive. With
nozzle 14 grounded and a voltage on charge ring 18,
electrical charges will be trapped on the ink droplet
as it breaks off from stream 16.
A~ the droplets fly forward they pass through an
electrical field provided by deflection electrodes 20.
If the drops carry a charge they are deflected by the
electrical field between electrodes 20. Highly ~ ~,
charged drops are deflected into a gutter 22, while
drops with little or no charge fly past the gutter
to print a dot on the media carried by drum 12. Ink
caught by gutter 22 may be recirculated to the ink
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system supplying islk to head 10.
In E'IGURE 1 the print drops have no charge placed on
them due to data. If there were no error effects, the
print drops would be uncharged. However, because of
the error effects, Gompensation charge is applied to
the print drops. This compensation charge varies from
print drop to print drop depending upon the correction
required to obtain the proper flight path to the media
on the drum 12.
The charge voltage applied to charge ring 18 is either
a gutter (no-print) voltage or a compensation voltage.
Switching circuit 24 receives the gutter print voltage
from gutter voltage generator 26 and the compensation
voltage from digital to analog converter 28. A zero
bit in the reference drop R position of shift register
30 indicates the reference drop DR should be guttered.
Accordingly, a binary zero from the reference drop stage
of shift register 30, causes switch 24 to connect the
gutter voltage generator 26 to the charge electrode
amplifier 34. On the other hand, if the reference drop
is to be printed, the R stage in shift register 30 will
have a binary one stored therein, A binary one applied
to switch 24 causes the switch to connect the
compensation signal from the digital-to-analog converter
28 to the charge electrode amplifier 34.
Digital-to-analog converter 28 receives a digital
compensation signal from the read only memory 32, The
size o the digital word from memory 32 depends upon
the capacity of the memory, Typically a 9 bit word
representative of a compensation signal with 512
possible levels might be used.
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The 9 bit word is converted into ~n anal~g signal by
the converter ~8 and applied to the switch 24. The
signal from switch 24 is amplified by the charge
electrode amplifier 34 and applied to the charge ring
18.
?
To generate the compensation signal, read only memory
32 contains 2 memory addresses with each address con-
taining a compensation voltage for a particular print
data pattern of drops. In the embodiment of FIG~RE 1,
one drop is monitored behind the reference drop and 30
drops are monitored in front of the reference drop.
The shift register 30 thus has 32 stages to temporarily
store the print data for the reference drop and the
additional 31 drops being monitored. Drop Do is the
trailing drop. Drops Dl to D30 are the drops
immediately preceeding the reference drop DR. Since
FIGURE 1 is a schematic representation and not to
scale, the distance shown from the reference drop DR
to the print drum 12 is not 30 drops. In actual
operation the distance would be in excess of 30 drop
periods (a drop period in distance equals the velocity
of the drops multiplied by the period of the drop
generation frequency).
:
L~ading drops Dl to D7 and trailing drop Do are
applied individually to the address register 33 for
read only memory 32 at clock ~ ~t time. The time,
clock ~ ~t, occurs a short time after the shift
register 30 has shifted but before the reference drop
DR breaks off during the clock cycle. Each of these
drops is close enough to the reference drop DR so that
each variation in their print data pattern has a
significant individual error effect on the flight time
of the reference drop. The quantity of leading drops
for which an individual correction is made is a design
trade-off between the size of the memory 32 and the
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eff~ct th~t the ne~t most remote drop has on the
r~ference drop.
One guideline that may be used to determine when to
start grouping the leading ~rops is as follows~ If the
last drop which is individually corrected for has an
error effect Oll the reference drop that requires a
compensation signal of z volts, then the next n number
of drops, which together are responsible for a
correction of z volts can be grouped together into a
single compensation bit decision. This is only one
of many ways in which to select the grouping of drops
for making a block compensation signal. Other
alternatives will be discussed hereinafter.
In FIGU~E 1, the remaining leading drops are grouped as
IS follows. slock or group A includes leading drops D16
through D30. Block B includes drops Dll through D15.
Block C includes drops D8, Dg and Dlo. Each of these
blocks is responsible for generating one bit of the
address used by address register 33 in read only
memory 32. In FIGURE 1 the criteria for designating
a block as a one or zero address bit based on the
print data in the block is indicated at the output of
ea~h block logic. For block C logic 36, if any of the
drops D8 to Dlo are a print drop then the Block C
logic will have a one output. In other words, n is
greater than 0 where n is the number of binary ones in
block C. The block C logic 36 could simply be an OR
circuit to generate an output binary one in the event
any of the stages D8, Dg, or Dlo of register 30 contains
a binary one.
The block B logic 38 monitors stages Dll through
D15 of shift register 30 for a total number of binary
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one~ excess of one. If two or more of the draps
Dll thro~gh D15 are print ~rops, block B logic 38
will have a binary o~e output. Similarly, block A
logic 40 monitors stages Dl6 through D30 of the shift
register 30 for a total of binary one's greater than
4. Thus, if 5 or more of the drops Dl6 through D30 are
print drops, block A logic 40 will have a binary one
output.
An example of the logic to implement block B logic 38
is shown in FIGURE 2. AND gate 42 in combination with
OR circuit 44 look~ for a print condition for drap Dl5 ~-~
in combinatiGn with a print condition for any of the
drops Dll through D14. AND gate 46 in combination with
OR circuit 48 looks for a print condition for drop Dl4
in combination with a print condition for any of the
drops Dll through Dl3. Similarly, AND gate 50 in
combination with OR 52 looks for a print condition on
drop D13 in combination with a print condition on drop
D11 or D12. Finally, AND gate 54 looks for the
combination of drops Dll and D12 being printed. All of
these possibilities are logically collected by OR 56
to generate the n greater than l indication as the
output from block B logic 38. Of course, any number
of logic designs might be used to determine 2 or more
of the droplets Dll through Dl5 are print drops.
A variety of techniques may be used to determine the
number of ones in a block or group which are necessary
before assigning a single bit code to the output of a
group. The criteria, n greater than 0 for block C, n
greater than 1 for block B, and n greater than 4 for
block A, were-all determined empirically. The test
procedure involved monitoring the compensation voltage
necessary to bring a print drop to the correct
pOsitioll for particular patterns. The patterns chosen
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for each block were consecutive print drops from 0 up
to the maximum size of the block'with the consecutive
drops being c~ntered in the block. All drops, other
than the reference drop, outside the block of drops
5 being observed were gutter drops. A correction
voltage for each pattern in each block was taken. The
maximum and minimum correction voltages were averaged.
Patterns requiring a correction voltage less than the
average value were then desi~nated as a one bit for the
group. Patterns requiring a correction greater than thè
average value were then designated as a zero bit for the
group. For example, in the Block A Logic if the number
of drops was 4 or less, the correction voltage was
greater than half of the average correction voltage for
the block. If the number of drops was 5 or greater than
the correction-voltage was less than half of the average -~
for the block.
The operation of the apparatus in FIGURE 3 is substan-
tially the same as the operation in FIGURE 1. The print
data for drops in the ink stream are buffered in shift
register 60. Trailing drop Do and preceding drops Dl -
through Dlo are applied directly to the address regis-ter
62 of read only memory 64. Drops Dl1 through D17 are
analyzed by logic 67. Logic 67 generates a binary one
if three or more of the droplets Dll through D17 are
print drops, i.e., binary one stored in at least three
of the shift register positions Dll through D17.
AY in FIGURE 1, the shift register is shifted at the
beginning of each drop clock cycle. Shortly there-
after (clock plus ~t) the values from the shiftregister 60 and the logic 67 output are loaded into
the address register 62. Thus the address register 62
is loaded with a new pattern address prior to the
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breakof~ time. The compensation value retrieved by the
acldr~ss irl the addless regfster i9 a 9-bit value which
is passed to the digital-to-analog converter 66. The
nine bits can then be converted by converter 66 to one
of 512 analog values. These analog compensation values
are amplified by the charge electrode amplifier and
applied to the charge electrode (FIGURE 1). If the
reference drop bit is a binary zero (a gutter drop),
the gutter uoltage is generated by converter 66. The
10 binary zero from the reference drop bit signals ~-
converter 66 to generate its maximum output voltage - ~' -
irrespective of the value from ROM 64. The drop is
charged with the maximum voltage and deflected to the
gutter as shown in FIGURE 1. If the reference drop bit
is a binary one (a print drop), converter 66 will
generate the charge electrode voltage based on
the compensation value received from memory 64. ; ~
An analysis of print error distribution, as a function - - -
of the total number, sample size NT, of droplets
20 preceding the reference drops that are individually -
monitored and as a function of print density, leads
to the present invention which further improves the
print quality. FIGURE 4 is a graph of print error
values versus the number of print combinations pro-
ducing the error value for various sample sizes NT.
Each curve or function represents a different NT. As
will be described hereinafter, this analysis shows that
further improvement in print quality can be achieved by
dynamically adjusting the blocking depending upon the
pattern of print data for droplets preceding the
reference drop.
The curves in FIGURE 4 are representative and not
precise. The NT=ll curve indicates the distribution of
the print error when 11 drops preceding the reference
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drop are individually monitored. The NT-8 curve
~indicates the distribution of th~,print error when
8 drops preceding the reference drop are monitored.
Generally, as fewer drops are monitored, the
distribution curve becomes flatter and wider and the
center point or highest number of combinations is at
a point further out on the print error axis in the
graph.
From the standpoint of print quality, it is the right-
hand portion of the distribution curves that represents
the most objectionable errors on the printed page.
Print errors in the left-hand portion of the error
distribution curve tend to not be visible to the eye
while those in the right-hand portion stand out on the
printed page. The curves show that if a very large
memory were available so that more drops coula be
monitored individually, the print error distribution
could be squeezed down to a spike and moved left on
the graph to or near zero print error. Of course, such
a gy5tem is not practical because of the large size
memory required. Within the limitation of a 4K memory, '
only 12 drops can be monitored. As previously
discussed, fewer drops immediately preceding the
reference drop could be monitored individually and
more remote drops monitored as groups.
In FIGUR~ 4, choosing to monitor 8 drops individually
instead of 11 drops moves the print error distribution
to the right. However, the print error distribution
for NT=8 can be divided into regions based upon print
density, the number of print drops in the eight bit
sample. The cross-hatched region in the right-hand
portion of the curve represents all combinations where
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the number of print drops is equal to or less than 3
~(r~<8) a low print density. The left-hand cross-
hatched portion in NT=8 represents all print drop
combinations where ~ive or more of the eight drops are
print drops (n~5) a high print density. The n>5
portion of the distribution confirms the expectation
that if a large number o the drops adjacent the
reference drop are print drops, they provide an ~
aerodynamic shield for the reference drop as it travels ~ -
10 to the print media. Conversely, if three or less of ~ -
the drops out of the eight drops are print drops, there
is much less shielding for the reference drop as it
flies to the print media, and the print error increases. ~ -~
If storage locations in memory for the patterns where
n>5 could be borrowed and given to the patterns where
n<3, it would be possible to.lower the worst case print
error. Stated another way, the drops more remote than
8 drops from the reference drop have a stronger effect
when three or less of the drops in the eight drops
proceeding the reference drop are print drops. There-
fore, for all cases where five or more of the drops in
the first eight are print drops, only pattern changes in
the eight drops will be monitored to address the `
read only memory for charge correction values. The
memory saved by not using bits 9, 10 and 11 may then
be used to store more correction values when three or
fewer of the first eight drops are print drops.
Referring again to FIGURE 4, the dashed curve for
NT= 8~3:5) shows a print error distribution for the
above memory swap method. In effect, the NT=8 waveformis squeezed to form the NT= 8~3:5) waveform. As a
result, there is an improvement in worst case error as
compared against NT=ll waveform, but there is also a
degradation in the smaller print errors. Since the
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113~53S
larger print errors are the most visible to the eye,
~this is an attractive tradeoff for improving overall
print quality.
In effect, the memory space swapping divides the NT=8
waveform into three portions requiring different
optimum print error pattern monitoring for optimum use
of the memory for storing compensation values. A first
mode for addressing the memory would be where five or
more of the droplets in the first eight drops preceding
the reference drop are print drops. A second mode
would be where four of the droplets of the first eight
preceding the reference drop are print drops. Finally,
the third mode would be where three or less of the drops --
of the first eight drops are print drops. In other
words, depending upon the number of print drops in the
first eight drops, the pattern monitored in the print
data and the blocking or grouping of print data to
address the memory may be dynamically changed.
~pparatus to implement my invention, the dynamic
grouping of the print data, is shown in FIGURE 5. This
apparatus divides the N~=8 curve into the three
portions shown in FIGURE 4. To do this the eiyht drops
immediately preceding the reference drop have their
pri.nt data monitored by a mode selection logic 72.
Print data register 70 contains the print data for the
reference drop R, one trailing drop Do and 17 drops
Dl-D17 preceding the reference drop.
Mode controlled gating 73 responds to the mode signals
from logic 72 to form the addresses used by the
compensation storage device 75. In the embodiment of
my invention in FIGURE 5, storage device 75 is
addressed by 12 bits. The 12 bits are ~ormed by the
mode control gating 73 from the print data bits in
the print data register 70.
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The mode control gating circuits receive data bits Do
~and Dl through ul7 from the print data register. In
mode 1, where the number of binary one's in Dl through '~
D8 is equal to or greater than five as signalled by the
mode selection logic 72, the gating circuits use Do and ~ -~
Dl through D8 as the address for the storage device 75.
The last three bits in the address are set to zero.
Setting these three bits to zero saves memory space
which can be subsequently used during mode 3.
In mode 2, where the number of binary one's in D
through D8 is equal to 4, the mode controlled gating ~
circuits group the print data bits from Dll through -
D17. These data bits are formed into a single data
bit B for the entire grcup or block. Accordingly, in
mode 2 the gating circuit 73 form the address for
storage 75 as Do~ Dl through Dlo and bit B.
In mode 3, where the number of binary one's in D
through D8 is less than~or equal to three, the gating
circuits 73 make use of the memory locations saved
during mode 1. Further, mode 3 operates in two phases
or two levels of addressing of the storage device 75.
In the first phase of addressing, the gating circuit 73
simply uses data bits Do and Dl through Dll to address
thè storage device 75. The compensation value
addressed is loaded into VcE storage device 77. The
gating circuits then proceed to the second phase of
addrèssing if two conditions exist in the print data--
D9, Dlo, and Dll are not all binary one's and D12
through D17 are not all binary zeros. If either of
these conditions occur, then mode 3 addressing stops
at phase 1. This in effect says that under these
conditions looking fox fluctuations in data patterns
at more remote drop positions is not necessary.
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Phase 2 or second level addressing during mode 3
proceeds i Dg, Dlo and Dll are not all binary one's
and if there are any binary one's in D12 through D17.
The address in phase 2 is generated by inverting data
bits Dl through D8 and pairing data bits D12 through
D17 into three block bits; Bl, B2 and B3. The trailing
bit data bit Do is also used at the first bit position
in the address. The fact that BI, B2 and B3 bits will
have one or more binary ones and the fact that Dl
through D8 data bits have been inverted means the
second level or second phase address will be identical
to the addresses saved during mode 1 on a one-to-cne
basis.
.
To use the compensation values accessed by the addresses
generated by gating circuit 73, storage devices 77 and
79, bridging logic 81 and adder 83 are used. In all
situations except mode 3, phase 2, the final compen-
sation value is stored in the VcE storage device 77.
From there VcE is passed through adder 83 to be
applied eventually to the charge electrode. In mode 3,
phase 2, adder 83 adds a Q VcE increment to the VcE
voltage. This is accomplished by loading compensation
values from storage device 75 into the Q VcE storage
device 79 during phase 2 of mode 3.
Each mode-3 phase-2 address accesses in storage device
75 three incremental compensation values ~ VcE one of
which may be added to the compensation value in storage
device 77. Which one of the three ~ VcE voltages is to
be added to the VcE voltage is controlled by bridging
logi~ 81. Bridge logic 81 is so named to reflect the
fact that the binary pattern in data bits Dg, DlOt and
Dll has a bridging effect between the data bits D~
through D8 and data bits D12 through D17. In other
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words, the strength of the effect of the pattern of
drops D12 through ~17 on the reference drop will depend
UpOIl the bridging effect of drops Dg, Dlo, and Dll.
Logic 81 selects one of the ~ VCE increments from
storage device 79 to be adde~d to the charge electrode
voltage VcE based upon whether the number of binary
one's in Dg, Dlo, and D11 is zero, one or two-
Thus, the apparatus in FIGURE 5 has dynamically selectedvarious print data bit groupings depending upon the
10 print data pattern. Further, those print data -~
combinations producing small errors have had their
memory storage space reallocated to those print data
patterns which contribute large errors. In this way,
the swap of storage space between mode 1 and mode 3
produces an overall reduction in the worst case print
error.
In FIGURE 6, a more detailed drawing of the FIGURE 5
embodiment of the invention is shown. Shift register 70
in mode selection logic 72 in FIGURE 6 correspond to the
print data register 70 and mode selection logic 72 in
FIGURE 5.
The mode selection logic 72 monitors drops Dl through D8
to detect the three conditions--n greater than or
equal to 5, n equals 4 and n less than or equal to 3
where n is the number of binary one's in the print
data for droplets Dl through D8. Mode 1 where n~5
utilizes only the variations in print patterns in the
first eight drops, Dl through D8, to change the address
in the read only memory 74. Mode 2 where n=4, treats
the trailing drop and the ten drops immediately
preceding the reference drop individually and treats
drops Dll through D17 as a group, i.e~, mode 2 operates
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exactly as the apparatus shown in FIGURE 3. Mode 3
wher~ n<3 makes use of the addresses saved during
mode 1 and changes the data blocking or data grouping
of droplets Dg through D17 based upon the pattern of ' ',
drops in Dg through D17.
In mode 1 and al'l other modes, the print data for the
trailing drop Do is passed directly to the zero order ,
position in address register 76. Also, the print data
from droplets Dl through D8 is passed to the address
10 ' register 76 via the invert switch 78. The invert
switch 78 is active to invert the print data for
droplets Dl through D8 only during mode 3 as will be
discussed hereinafter. Normally the invert switch 78
passe's the print data for droplets Dl through D8
15 directly from the shift register 70 to the address :
register 7 6.
In addition, in mode 1, the signal line representing
the condition n>5 is used to enable gate 80. Gate 80
passes binary zeroes to OR circuits'82, 84 and 86 which
20 in turn pass the binary zeros to the ninth, tenth and ~, :
eleventh order positions of the address register 76.
Thus, in mode 1, the three highest address register
positions are forced to zero and this space saved
during mode 1 will be subsequently used during mode 3
as hereinafter described.
In mode 2, the print data in the shift register 70 is '''
monitored in the same manner as the print data was ' ,~
monitored, in FIGURE 3. The mode 2 signal or n=4
condition signal is used to activate or enable gate 88.
Gate 88 passes the print data bit from D9 to OR circuit
82, from Dlo to OR circuit 84 and from logic 90 to OR
circuit 86. The last address bit is generated from the
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22
qroup analysis of data positions Dl1 through D17 by the
n>3 logic 90.
The address positions for the ninth, tenth and eleventh
order bits in the address register are then passed by
OR's 82, 84 and 86 to the address register 76 of the
read only memory 74. The first address position in the
address register 76 is from the trailing drop position
Do in the shift register 70. The next eight positions
in the address register are from drop data positions
Dl through D8 in shift register 70. In other words in
mode 2, the trailing drop and the ten drops immediately
preceding the reference drop are monitored individually
while drops Dll through D17 are grouped into a single
data bit for addressing the read only memory 74. This
operation is identical to that previously described for
FIGURE 3.
In mode 3, the read only memory 74 is addressed in two
phases or two levels. The blocking or grouping of the
data in this two-phase addressing for droplets Dg
through D17 depends upon the pattern of print data in
9 gh D17. If Dg, Dlo, and Dll all contain binary
one's, then only one phase of addressing is used during
mode 3. Also if droplets D12 through D17 are all binary
zeros, only one phase of addressing is used in mode 3.
If neither of these conditions are satisfied, then two
phases of addressing are used during mode 3.
In phase 1 of mode 3, gate 92 is enabled to pass the
print data from stages Dg through Dll to address
register 76. Simultaneously binary.bits for stages Do
and Dl through D8 are also passed to the address
register 76. Thus, the first phase or first level
addressing of memory 74 uses the individùal data bits
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for Do and Dl through Dll. At clock phase 1 time
plus ~tl (Clk Ph 1 -~ ~tl) AND ga~e 94 is enabled and
provides a set signal for register 96. Register 96
then stores the binary bits for Dg, Dlo and Dll passed
~y gate 92. The Clk Ph 1 ~ ~tl signal is used so that
transients in the logic die out before setting register
96 with the contents of Dg, Dlo and Dll from shift
-register 70. Shift register 70 is shifted by the
leading edge of the clock phase 1 (Clk Ph 1) signal.
10 The Qtl interval occurs early during the duration of ~-
the clock phase l signal.
At clock phase 1 plus at2 (Clk Ph 1 + ~t2), the
compensation value addressed in memory 74 during phase
1 is loaded into a register 98. The ~t2 interval occurs
during clock phase 1 duration shortly after the ~t
interval pulse occurs during clock phase 1.
Note that address register 76 is set by Clk Ph 1 + ~tl
via OR 100. As a result, the address register is set at
~tl during phase 1 and the compensation value read out
20 from memory 74 is loaded into register 98 at ~t2 during
phase 1.
In summaxy, in phase 1 mode 3, at time Qtl print data
or Do through Dll are loaded into the address register
76. At phase 1 ~t2 time, the compensation value for
this first level addressing of memory 74 is stored in
register 98. Also register 96 is set at ~t2 time to
store the contents of Dg, Dlo and Dll. These binary
values will be used as described hereinafter during
phase 2 of mode 3.
30 A mode 3 phase 2 condition is signaled by AND gate 102.
The inputs to AND gate 102 are the mode 3 signal from
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24
logic 72, the clock phase 2 (Clk Ph 2) signal and the
output of NOR 104. ~OR 104 has an output only i~ Dg,
Dlo, Dll are not all binary one's and only if D12
through D17 are not all binary zeros.
D12 through D17 are paired to form three blocks or
groupings of two by OR circuits 110, 112 and 114. OR
110 will have an output if either D12 or D13 contains a
binary one. OR 112 will have an output if either D14
or Dl5 contain a binary one. OR 114 will have an output
if either D16 or D17 contain a binary one.
NOR 108 monitors the output of the paired blocks and
has an output itself if OR circuits 110, 112 and 114
all have zero outputs. AND gate 106 monitors~Dg, Dlo
and Dll and has an output only if Dg through Dll are
all binary one's. NOR 104 then collects the output
from AND 106 and NOR 108 and has an output only if
there is zero output from both AND 106 and NOR 108.
Thus a one output from NOR 104 means that Dg through
Dll are not all l's and D12 through D17 are not all 0's.
This is the phase 2 mode 3 condition and if it is mode 3
at Clk Ph 2 time AND 102 will have an output. This mode
3 phase 2 signal is used to enable gate 116, to switch
invert switch 78 and to enable AND gates 118 and 120.
Enabling invert switch 78 means that the inverted data
bit pattern from Dl through D8 in shift register 70 is
applied to bit positions 1 through 8 in the address
register 76. Enabling AND gate 118 means that at Clk
Ph 2 time plus Atl (Clk Ph 2 ~ ~t2) address register 76
will be set to the value on the input lines to the
address register. ~tl is a timing pulse occurring some
time during duration of Clk Ph 2. Enabling AND gate
120 means that at Clk Ph 2 ~ ~t2 time ~shortly after
Clk Ph 2 ~ ~tl) ~VcE register 122 will be loaded with
BO978055
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the compensa-tion value addressed at Clk Ph 2 ~ Qtl time.
EllablincJ gate 116 means that the paired grouping output
rom D12 through D17 is passed by gate 116 thrGugh OR's
82, 84 and 86 to the address register 76. These bits -
are the address inputs for bits 9, 10 and 11 in the
address register 76 during the phase 2 or second level
addressing. . :
:
In summary, the second level address for the read only
memory 74 is the trailing bit Do~ the inverted data
10 pattern for Dl through D8 and the paired groupings from : :
D12 through D17. At Clk Ph 2 ~ Qt2 time, AND gate 120
will have an output since it has been enabled by AND
gate 102. This output from AND gate 120 sets QVCE ~ : .
register to load the nine bits of compensation stored
15 at the address accessed during the second level ~ ~
addressing. Thus, in mode 3 at the end of clock phase -.
2, the VcE register 98 contains a compensation value
and the QVCE register 122 also contains values for
compensating the charged drop. - :~
The values in the QVcE register are divided into three
portions. Memory 74 has a nine-bit output so these
nine bits may be divided into three groups of three
bits and stored in QVCE register 122. One of the three
bit values in register 122 will be added to the VcE
nine bit value in register 9~ by the digital adder 124.
Which one of the three bit values in register 122 is
added depends upon the contents of register 96.
Register 96 is analyzed by the ~VCE logic 126. Depending
UpOII whether the number of one's in print data bits Dg,
30 Dlo and Dll is 0, 1 or 2, gate 128 will gate one of the
three bit values in register 122 to the digital adder
124. The selected QVcE compensation value is added to
the VcE compensation value and passed to the digital-to-
analog converter 130. The output of the converter 130
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26
goes to the switch 24 which performs the same function
as described in FIGURE 1.
To summarize mode 3, if the number of binary one's in
bits Dl through D8 are less than or equal to 3 and bits
Dg, Dlo and Dll are all one's or bits D12 through D17
are all zeros, the pattern is sufficiently isolated that
the memo.ry 74 is addressed by the trailing bit and
bits Dl through Dll. However, if the bits Dg through
Dll are not all one's and the bits D12 through D17 are
10 not all zeros, various patterns of compensation will ~ :
occur. The streng~h of the bridging of compensation
1 D8 to D12 - D17 will depend upon the
number of one's in Dg, Dlo, and Dll. Accordingly, a
~VcE compensation is added to a VcE compensation by
two-level addressing of memory 74. The values for
the VcE in the first level depend upon the data pattern
from Dl through Dll while the values in the second -~
level for the ~VcE increments depend upon the data
pattern in D12 through D17 grouped in pairs and the
strength of the bridging as represented by the number
of binary one's in Dg, Dlo and Dll. ,
In the first level of addressing, a 9-bit word read
from the memory 74 define~ the value for VcE. In the
second level of addressing, the 9-bit word read from
memory is partitioned into three 3-bit words--one
th.ree bit word for each QVCE increment. Thus, the
second level 9-bit word is partitioned so that there
is a three-bit incremental compensation word for each
of the three possible bridging effects (Dg, Dlo and
Dll contain 0, 1 or 2 binary ones)..
Note that the ~VcE register 122 is reset at Clk Ph 1 ~
~t2 time. Accordingly, register 122 is reset to zeros
near the end of each Clk Ph 1 time. Therefore, register
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~7
12~ will have values in it only if there i~ a mode 3
phase 2 condition as indicated by AND 102. Under all
other conditions the compensation value applied to the
converter 130 is represented only by the digital value
in VcE register 98. ~
In the above described manner, FIGURE 6 implements ~ ~ -
the waveform NT= 8(3:5) shown in FIGURE 4. As described
earlier, this print error distribution produces an ~ -
improvement in the worst case condition andl thus, an
improvement to the eye of an observer of the printed
document.
,
My invention may also be implemented by use of a
computer. A computer controlled system to retrieve the ;
compensation values to be applied to the charged
electrode amplifier is shown in FIGURE 7. Waveforms
occurring in FIGURE 7 and illustrative of the timing
of the system are shown in FIGURE 8.
In FIGURE 7, timing for the system is provided by the
timing oscillator 132. Oscillator 132 generates a
cycle clock signal ~waveform A of FIGURE 7) which is
used to control the cycles of the computer 134. The
cycle clock signal is divided by a frequency divider
136 to generate a drop clock signal (waveform B FIGURE
8). The division factor M for the frequency divider
circuit 136 is selected to provide the desired drop
frequency and also to allow the computer sufficient
time during a drop cycle to find the compensation value
to be used during the next drop cycle.
Sync logic 138 is controlled by computer 13~ to generate
a sync pulse (waveform C of FIGURE 8) to synchronize
the system with the time of occurrence of drop breakoff
B0978055
1~37S35
28
of the ink droplet from the ink stream. Waveform D in
FIG~RE 8 is an example of the ch~rge electrode voltage
building up during each cycle between sync pulses.
Sync logic 138 under control of computer 134 generates
the sync pulse at a time sufficiently ahead of the
drop breakoff time to allow the charge electrode voltage
to build to a stable level. Typically, the sync pulse
will be generated such that it occurs during the first
one-fourth of the drop cycle while the drop breakoff
point occurs approximately three-fourths of the period
through the drop cycle.
The sync pulse is used as a clocking pulse for the
data source 140 and shift register 142. Serial data
from the data source is shifted into the shift
register 142 by the leading edge (LE) of the sync
pulse. The trailing edge (TE) of the sync pulse~enables
gate 144 to pass print data bits Do and Dl through D
to computer 134 for analysis. Thus, the leading edge
of the sync pulse is used to shift data into the shift
register 142 and the trailing edge is used to gate that
data in parallel to the computer.
The compuker 134 analyzes the print data pattern to
retrieve the compensation value from the read only
memory 146 before the leading edge of the next sync
pulse transfers the compensation value into the vcE
register 148.
Computer 134 contains a processor and a memory. The
computer is program controlled to implement the group
blocking of the print data into a pattern which can be
used to address the read only memory 146. Gating
logic 150 is controlled by the computer to pass the
addresses generated by the computer to address the
BO978055
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read only memory. Gating logic 150 is also controlled
by the computer to access the compensation value stored
in the read only memory as addressed and to operate on
that compensation value as dictated by the program. The
final compensation value is then gated under computer
control to the register 148.
The register 148 is set to the digital value for the
charge electrode voltage by the leading edge of the sync
pulse. Since computation time is predetermined to be
less than the time between sync pulses, the charge
electrode voltage is computed during one cycle between
sync pulses and used during the next cycle between the
sync pulses. -~
~.
The computer 134 can also be used to store a digital
value for the gutter voltage. Thus, in the event that
the reference bit R is a no print or zero bit, the
computer 134 gates the digital value of the gutter
voltage through the gating logic 150 to the register
148. At the leading edge of the next sync pulse, the
gutter voltage value is loaded into register 148. The
digital-to-analog converter 151 then applies the gutter
voltage value to the charge electrode amplifier. If
the reference drop R is a print drop, the compensation
value will be loaded into register 148, converted by
converter 151 to an analog signal and applied to the
charge electrode amplifier.
The advantage of the apparatus in FIGURE 7 is that
computer 134 can be programmed to implement a number
of print data grouping or print data blocking
techniques to address the memory 146 for compensation
values. One example of program control of the
computer 134 to implement the embodiment previously
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.,
described for FIGURES 5 and 6 is illustrated by the
program flowcharts in FIGUR~S 9 and 10. When programmed
in accordance with these flowcharts, the computer 134
will dynamically change the group blocking of the print
data in accordance with the three modes previously
discussed with reference to FIGUR~S 4 and 5. Any
number of computing systems could be used so long as
they are fast enough to complete the addressing within
the period of one drop cycle (about 10 ~sec.).
Referring now to FIGURE 9, the program starts by
checlcing the reference drop R to determine whether it
is a print drop or a gutter drop. If the reference
drop is a binary zero, decision block 152 passes control
to block 154. Operation block 154 controls the computer
to provide a digital value VcE equal to the count 511.
The count 511 corresponds to the nine bit digital value
of the gutter voltage. Accordingly, when the VcE
rêgister 148 (FIGURE 7) is next loaded by the sync
pulse, the 511 count would be passed into the register.
If the reference drop is a binary one, program control
passes to decision block 156. Decision block 156
is the mode 1 decision block. If the number of binary
one's for print data bits Dl through D8 is greater than
or equal to 5, program control branches to mode 1
implemented by operation block 158. If the number of
binary one's in Dl through D8 is less than 5, program
control passes to decision block 160 to make the
decision between mode 2 and mode 3.
In mode 1, operation 158 sets the 4K address for the
read only memory to the binary values for Do through
D8 and forces the three highest address bit positions
to zero. Program control passes then to operation
BO978055
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31
block 162 where the mode 1 address is used to access
.the charge electrode volta~e fro~ the read only ~emory.
At the next sync pulse this charge electrode value
would be loaded into register 148 in FIGURE 7.
Mode 2 operation occurs if the decision block l60
indicates the number of binary one's in Dl through D8
is equal to 4. The program control then passes to
decision block 164. Decision block 164 represents the
group analysis of print data bits Dll through D17. If
the number of binary one's in Dll through D17 is equal
to or greater than 3, the program passes to operation
block 166. If the number of one's in Dll through D17
is less than 3, the program passes to operation block
168. In operation 166, the add~ess bits are set to
the values for data bits Do through Dlo, and the elev-
enth bit position is set to binary 1 representing databits Dl] through D17 as a group. Operation 168 sets
the address to the data bits for Do through Dlo and
the eleventh bit is set to a binary 0 representing the
group of data bits Dll through D17. The mode 2
address from èither block 166 or 168 is used by
operation block 162 to access the read only memory
to obtain the charge electrode voltage. ThiS mode 2
charge electrode voltage is then loaded into the
regi5ter 148 (FIGURE 7) during the next sync pulse.
Mode 3 operation is indicated by a negative decision
by decision block 160 in FIGURE 9. If the decision
blocks 156 and 160 both produce negative results, then
the number of binary one's in Dl through D8 must be
less than or equal to 3 which is the mode 3 condition.
The mode 3 operation 170 in FIGURE 9 is diagrammed in ,
detail in FIGURE 10.
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:. . . , , :
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32
In FIGUI~E 10, the m~d~ 3 operation starts by hlocking or -
grouping the data bits pairs D12'with D13, D14 with Dl5,
16 17~ D12 or D13 or both contain a
binary one r then decision block 170 sets a block bit B
to 1. If both D12 and D13 contain binary zeros, then
decision block 170 sets the block bit Bl to zero.
Decision blocks 172 and 174 perform the same function
for data bits D14 with D15 and D16 with D17, respec-
tively. Block bit B2 is set to one if D14 or D15
contains a binary one; otherwise, block B2 equals zero.
Similarly, block bit B3 is set to one if D16 or D17
contain a binary one; otherwisej block bit B3 is set to
zero.
Next program flow moves to decision block 176 to
determine if the number of binary one's in Bl through
B3 is equal to zero If it is, program flow branches to
operation block 178. If it is not, program flow
branches to decision block 180 to determine if the
number of binary one's in data bits Dg through Dll is
equal to 3. If it is, the program flow branches to
operation block 178. If it is not, program flow
branches to mode 3 double phase.
In mode 3 single phase, operation block 178 sets the
address bits to the data bit pattern for data bits Do
through Dll. Computer 134 then controls the gating
logic via operation block 182. Operation 182 causes
the computer to address the read only memory with the
address bits set by operation 178. The charge electrode
voltage obtained from the read only memory is then
gated to the register 148 during the next sync pulse.
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n mode 3 double phase, progrdin flow branches from
decision block 180 to operation block 184. In the
first phase of the double phase operation, block 184
sets the address bits to the value of the data bits
5 Do through Dll. This address is then used by operation
186 to access the read only memory and get charge
electrode voltage VlcE for phase 1.
Program control passe`s on to operation 188 to commence
the second phase of the double-phase operation. In
operation 188, the computer inverts the data bits for
Dl through D8 and proceeds to operation 190. In
operation 190, the computer sets the address bits to
the bit Do~ the inverted data bits for Dl through D8, -
and the block bits Bl, B2 and B3 for positions 9, 10
15 and 11 of the address. This second phase address is
then used during operation 192 to access the read only
memory.
In operation 192, the 9 bits of compensation value read
from the read only memory are partitioned into three
sections, ~ 2 and Q3, of three bits each. Each of
these three-bit values may then be added to the VlcE
charge electrode voltage determined during phase 1.
The addition operation depends upon the number of binary
one's in the data bit positions D9, Dlo and Dll. The
program control flows from operation 190 to decision
block 194.
I~ the number of binary one's in Dg, Dlo and Dll is
equal to zero, then decision block 194 branches the
program to operation block 196. Operation 196 adds ~1
to the charge electrode voltage VlcE determined during
the first phase. If the number of binary one's in Dg
through Dll is not equal to 0, program control branches
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to decision block i98 to determine whether the number
of binary one's is equal to 1 or greater than 1. If
the nu~er of binary one's in Dg through Dll is equal
to 1, then the charge electrode voltage is formed by
operation 200. Computer 134 in operation 200 adds the
first phase charge electrode voltage VlcE to ~2 to
obtain the final charge electrode voltage V1cE. If
the number of binary one's in Dg, Dlo and Dll is not
equal to zero and not equal to one, the program will
branch to operation block 202. In operation 202, the
computer 134 adds the first phase charge electrode
voltage vlcE to Q3 to form the final charge electrode
voltage VcE. As discussed earlier, these ~ charge
electrode increments are different due to the different
bridging effect, caused by the number of binary one's
in positions Dg, D10 and Dll, on the block pairs
represented by binary bits Bi, B2 and B3. Once the
final charge electrode voltage is determined in the
double-phase operation by one of the operations 196,
200 or.202, that charge electrode voltage is loaded
into the register 148 (FIGURE 7) during the next sync
pulse.
While FIGURE 7 has been described as programmed to
implement the embodiment in FIGURE 6, it will be apparent
to one skilled in the art that the computer could be
programmed to implement other embodiments. For example,
by changing the size of the shift register and the read
only memory and be changing the group data bit analysis
performed by the programmed computer, any number of
blocking or grouping patterns might be used to address
the read only memory.
Further, more or less than three modes of selection to
different dynamic blocking or grouping routines could
B0978055
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be used. For ex~mple, if the data bit pattern being ?
~monitored to make the mode selection contained an odd
number of data bits, the invention might be implemented
by using two modes rather than three modes. In other
words, if the first seven data bits preceding the
referenced drop were being monitored to make the mode
selection, the memory swap could be made based on a
greater-than-or-equal-to four and a less-than-or-equal-
to three mode selection. There would be no middle
10 condition between the swap and, thus, there would only
be two modes selected.
Furthermore, if more data bits were being monitored,
the computer might be programmed to dynamically group
more data bits as a function of the bridging effect of
15 the data bit pattern in one group on the data pattern
in the next group.
While I have illustrated and described the preferred
embodiments of my invention, it is understood that -:
I do not limit myself to the precise constructions ~-
herein disclosed and the right is reserved to all
changes and modifications coming within the scope of the
inventioll as defined in the appended claims.
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