Note: Descriptions are shown in the official language in which they were submitted.
1~385~1 .
Back round of the Invention
This invention relates generally to semiconductor struc-
tures and manufacturing methods and more particularly to short
channel metal-oxide-semiconductor (MOS) field-effect transistor
structures and manufacturing methods.
As is known in the art, high performance MOS field-effect
transistors generally require channel lengths below 3~m and
even as short as 0.5 to 1.0~m. It is very difficult to
obtain these small dimensions with present photolithographic
techniques. This difficulty has led to the development of
several types o~ transistors having channel lengths defined
by means other than photolithography. One such device is
generally referred to as a D-MOS transistor where two
~iffusions of dopants of opposite type conductivity are
driven to different depths in a silicon substrate through
~/7~
one, noncritical mask opening, resulting in a channel length
equal to the difference in the depth of the electrical junctions
formed. Here, however, since the doping concentration varies
along the channel, the "turn-on" voltage, which is a function
of doping, is critically dependent on the location in the
channel and the concentration at which the two diffusion
profiles intersect. In practice, therefore, the "turn-on", or
threshold voltage, will exhibit relatively large fluctuations
because of the difficulty to control ~he two diffusions.
Other types of transistors wherein channel width is
controlled by means other than photolithography are so-called
"V-MOS" transistors and "D-V-MOS" transistors. With a V-MOS
transistor the channel length is generally defined by the
up-diffusion of boron from an n-type substrate into a p-type
epitaxial layer formed on such substrate, in combination with a
~38571
V-shaped groove etched through the epitaxial layer, down into
the substrate. In the D-V-MOS transistor the channel is
generally defined by an implant of boron from the top surface,
through the n+ layer forming the source and drain, and again the
intersection of the implanted zone with the walls of a V-shaped
groove.
113~571
Summary of the Invention
In accordance with the present invention a masking layer is formed
to cover a portion of a surface of a semiconductor; a first doped region is
formed in a portion of the semiconductor exposed by the ~asking layer; a
chemical etchant is brought into contact with the masking layer, reducing
the area of the masking layer covering the semiconductor, exposing a second,
different portion of the semiconductor contiguous to the first exposed por-
tion of the semiconductor; and particles capable of establishing a doped
region in the semiconductor are introduced into the second exposed portion
of the semiconductor to form a second doped region in the semiconductor
contiguous to the first doped region, such chemically etchet masking layer
inhibiting such particles from becoming introduced into the portion of the
semiconductor disposed beneath the chemically etched masking layer.
Thus, this invention provides a method of forming a semiconductor
structure comprising the steps of:
(a) forming an insulating layer over a portion of a surface of a
semiconductor having a first type conductivity masking such portion of the
semiconductor;
(b) forming a region of opposite type conductivity in a portion
of the semiconductor layer unmasked by the insulating layer;
(c) bringing a chemical etchant into contact with the insulating
layer, reducing the area of the semiconductor masked by the insulating layer;
(d) ion implanting particles capable of establishing a first type
conductivity in the semiconductor into a portion of the semiconductor exposed
by the chemically etched insulating layer forming a region of first type
conductivity contiguous to both the first formed region of opposite type
conductivity and a region of the semiconductor masked by remaining portions
of the chemically etched insulating layer; and,
(e) forming an electrode over remaining portions of the chemically
~0 etched insulating làyer and over the portion of the semiconductor exposed
1131~1571
by the chemically etched insulating layer and having formed therein the ion
implanted region.
In a second aspect, this invention provides a method for forming a
semiconductor structure comprising the steps of:
(a) forming an insulator over a portion of a surface of a semi-
conductor structure;
(b) forming a first doped region in a portion of the semiconductor
structure exposed by the insulator;
(c) bringing a chemical etchant into contact with the insulator
removing edge portions thereof ~xposing a second, different portion of the
semiconductor structure contiguous to the first doped region;
(d) introducing particles into the second, different portion of
the semiconductor structure, the remaining unetched portions of the chemically
etched insulator inhibiting such particles from becoming introduced into the
portion of the semiconductor structure disposed beneath remaining portions
of the insulator; and
(e) forming an electrode over remaining portions of the insulator
and over the second, different portion of the semiconductor structure exposed
by the insulator.
In a preferred embodiment of this invention a second masking layer
is formed over the first-mentioned masking layer, such second masking layer
~emaining over the first-mentioned masking layer while a portion of the
first-mentioned layer is chemically removed. The second masking layer re-
stricts the chemical attack of the etchant to the side of the first-mentioned
masking layer.
Further, the structure is formed in a mesa-shape with side walls of
such structure being oxidized for device isolation. The first-mentioned
masking layer is silicon dioxide and the second masking layer is silicon
nitride. During the oxidation process the second masking layer remains over
the first-mentioned masking layer, enabling the selective oxidation of the
walls of the silicon semiconductor, but preventing oxidation of the first-
mentioned masking layer.
- 3a -
1~38571
Still further, in a preferred embodiment of this invention
the masking layer is used to form source and drain regions of a
field effect device. The particles are ion implanted to form a
gate region contiguous to one of the source and drain regions.
The channel length of this gate region is accurately controlled
by the chemical etching process. The masking layer used to
form the source and drain regions is, after being chemically
etched, used as an ion implantation mask for forming the qate
region. In this way the process is self-aligning since the mask
used to form the source and drain regions is, after being
etched, used to form the gate region. The masking layer includes
a layer of silicon dioxide. A drift channel is formed in the
silicon layer disposed beneath the silicon dioxide masking layer
to electrically connect the ion implanted gate region to the
source and drain regions.
With such techniques the field effect device has a
uniformly doped short channel formed by ion implantation.
Furthermore, ~he channel length depends on an accurately
controlled chemical etching process. Still further, a relatively
thick oxide or insulator layer is formed over the drift region
so that when a gate electrode is formed over this oxide layer,
any parasitic capacitance between such electrode and the
drift region is reduced by this thick oxide layer.
1138571
Brief Description of the Drawings
The foregoing features of this invention, as well as the
invention itself, may be more fully understood from the fol-
lowing description read together with the accompanying drawings,
in which:
FIGS. 1-9 are cross-section elevation, diagrammatical
views of a portion of a field effect device according to
the invention at various steps in the manufacture thereof; and
FIG. 10 is a cross-sectional eleva~ion, diagrammatical
view of a portion of the field effect device according to an
alternative embodiment of the invention at an intermediate
stage in the manufacture thereof.
1138571
Description of the Preferred Embodiments
Referring now to FIGS. 1-9, the fabrication of a field
effect device will be described. As shown in FIG. 1, a p-type
silicon substrate 10, preferably having a surface parallel
to the ~100> crystallographic plane and having a doping concen-
tration in the range of 5X1014 to 1015 atoms per cm3 is coated
with a 1500 to 3000 A thick silicon dioxide layer 12 by conven-
tional thermal oxidation or chemical vapor deposition, or a
combination of both. Next the silicon dioxide layer 12 is
coated with a silicon nitride layer 14, here in the order of
1500 A thick, using conventional chemical vapor deposition. A
photoresist layer 16 is formed over the silicon nitride
layer 14 and selectively removed using conventional photo-
lithography to form a mask 18, as shown. The photoresis~ mask
18 is used to remove exposed portions of the silicon nitride
layer 14 and the then exposed silicon dioxide layer 12 adjacent
such mask 18 using any conventional technique. For example,
the exposed portions of the silicon nitride layer 14 may be
removed using conventional plasma etching and the then
exposed portions of the silicon dioxide layer 12 are removed
with a suitable chemical etchant, here a hydrofluoric acid
solution or also by plasma etching. That is, as will become
apparent hereinafter, the composite silicon dioxide layer 12
and silicon nitride layer 14 are etched away from the field or
isolation region while they are retained over the mesa shaped
Z/~ ~ ~ own in FIG. 2. The remaining portions of the composite
silicon dioxide layer 12-silicon nitride layer 14 form an etch
resistant mask 20, as shown. The portions of the silicon sub-
strate 1~ exposed by such mask 20 are brought into contact by a
suitable etchant, either an isotropic or anisotropic etchant,
113857~
to etch such exposed portions of the silicon substrate 10
to a depth in the order of 3000 to 4000 A, as shown. The sur-
face of the structure thus formed is exposed to ion implanted
particles 22, here boron atoms, with a dosage of 5X1013 atoms
per cm2 to 5~1014 atoms/cm2 at an implant energy here in the
order of 40 Kev. The structure is then heated in a conventional
manner to anneal any implant damage and to activate the im-
planted boron atoms forming p-type conductivity regions 24, as
shown.
Referring now also to FIG. 3, the structure is then
oxidized to form a 6000-8000A thick silicon dioxide layer 26
on the side walls of the mesa-shaped silicon substrate 10 and
thereby form a surface in the isolation regions which is substan-
tially co-planar with the device surface. (It should be
noted that during the oxidation the boron dopant is driven
further into the silicon substrate 10.) The boron implant,
i.e. p-type conductivity regions 24 (FIG. 2), prevents the
formation of an inversion layer on the surface of the high
resistivity silicon substrate 10 which would destroy device
isolation.
A photoresist layer 28 is deposited over the surface
of the structure and then suitably masked and etched,
using conventional photolithographic~chemical etching
techniques to form a mask 30, as shown in FIG. 3. The
portions of the silicon nitride layer 14 and silicon dioxide
layer 12 exposed by the photoreslst mask 30 are removed in
any conventional manner, similar to that described in
connection with FIGS. 1 and 2, to expose portions of the
underlying surface of the silicon substrate 10, wherein the
source and drain regions 36, 38 of the device will be formed,
1~3~S71
as shown in FIG. 4. The remaining portions of the composite
silicon nitride layer 14 and silicon dioxide layer 12 form an
ion implantation mask 32 as shown in FIG. 4. Particles, here
arsenic atoms, are ion implanted into the portions of the
silicon substrate 10 exposed by the ion implantation mask 32.
Here a dosage of 5X1014 atoms/cm2 and an implant energy level
of 140 Kev is used. The structure is heated to anneal any
implant damage and to activate the implanted arsenic atoms
to form n-type conductivity source and drain regions 36, 38
respectively, as shown, in the regions of the silicon sub-
strate 10 which are adjacent the region of such substrate 10
covered by the ion implantation mask 32. The depth of the
source and drain regions 36, 38 is here in the order of 1000 A.
Referring now also to FIG. 5, a photoresist layer 40 is
formed over the surface of the structure, using conventional
photolithographic techniques to form an etch resistant mask 42
as shown. It is noted that a window 44 is formed in the photo-
resist layer 40 to expose: A portion of the silicon substrate
10 having the source region 36 formed therein; the side portions
of the silicon nitride layer 12; the side portions of the
silicon dioxide layer 14 adjacent the source region 36; and a
portion of the upper surface of the silicon nitride layer 14.
The purpose of the mask 42 is to expose only the edge of the
source region 36 while covering the drain region 38. This
masking step is then relatively noncritical. A chemical etchant,
here a hydrofluoric acid solution, which selectively etches
silicon dioxide without attacking either silicon, silicon nitride
or photoresist, is brought into contact with the surface of the
structure. The chemical etchant passes through the window 44
tG attack the exposed side portions of the silicon dioxide layer
113857~
12 and thereby selectively etch away and remove such exposed
portion of the silicon dioxide layer 12. The chemical etchant
therefore reduces the area of the silicon substrate 10 dis-
posed beneath the chemically etched silicon dioxide layer 12,
exposing a gate region 47 (FIG. 6) which is contiguous to the
source region 36. As will be described, the remaining portion
of the silicon dioxide layer 12 will provide an ion implantation
mask for forming gate region 47 of the field effect device. The
silicon dioxide layer 14 is therefore etched bac~ a length L,
here in the order of 0.5 to 2.5~ m, such length, L, being the
channel length of the field effect device. It is noted that
the length L of the gate region is determined by the amount
of chemical etching provided to the silicon dioxide layer
12. This chemical etching process is readily controllable by
the etching time duration and chemical etchant stren~th which
is itse~f controllable by proper dilution. Further, the
etching processes may be monitored using a high powered
measuring microscope. The resulting structure, after
photoresist layer 40 is removed, is shown in FIG. 6.
Referring now also to FIG. 7, the silicon nitride layer 14
is removed in any conventional manner and a thin silicon dioxide
layer 46 is thermally grown over the surface of the structure.
The thin silicon dioxide layer 46 is here in the order of
300 to 1000 A thick and, as will be shown, provides the gate
oxide for the device. (It is noted that the silicon dioxide
layer 46 is thicker over the surface of the silicon substrate 10
than over the silicon dioxide layer 14.) Following this thermal
oxidation, particles, here boron atoms, are ion implanted into
the surface of the structure. It is noted that the thicker
silicon dioxide layer 12 serves as an ion implantation mask
113857~
so that the boron atoms become implanted only into the portion
of the silicon substrate 10 which is disposed beneath the
thinner oxide layer 46, the silicon dioxide layer 12 inhibiting
boron atoms from becoming implanted in the portions of the
silicon substrate 10 disposed beneath the silicon dioxide
layer 12. The concentration of boron atoms in the silicon
substrate 10 is here in the order of 3 x 1012 atoms/cm2 and hence,
after annealing, a p-type conductivity region is formed in
the gate region 47 as shown in Figure 7. It is noted that the
concentration of n-type dopant in the source and drain regions
36, 38 is in the order of 3 x 1019 atoms/cm3 or higher and hence
is not substantially affected by the boron implant which results
in a concentration several orders of magnitude less than
3 x 1019 atoms/cm3.
Referring now also to Figure 8, a photoresist layer 50
is deposited over the surface of the structure and patterned
into a source/drain contact mask 52, as shown, using con-
ventional photolithographic-chemical etching techniques. A
suitable chemical etchant is then brought into contact with
the mask 52 and the portions of the silicon dioxide layer 46
exposed by the windows 51, 53 formed in the mask 52 to selec-
tively remove such exposed portions of the silicon dioxide layer
46 which are disposed over portions of the source and drain
regions 36J 38, respectively, as shown in Figure 9. After the
photoresist layer 50 has been removed in any conventional manner
a suitable metalization layer 54 is deposited over the surface
of the structure, i.e. over the remaining portions of the silicon
dioxide layer 46 and, through the windows 51, 53 formed therein,
onto the exposed surfaces of the silicon substrate 10 which are
disposed over portions of the source and drain regions 36, 38
- 10 -
~F`
~`~
l~3ssn
to form ohmic contact with such regions 36, 38. The metaliza-
tion layer 54 is then patterned, in any conventional manner, as
by photolithographic-chemical etching processing, into source,
drain and gate electrodes S, D and G, respectively, as shown in
FIG. 9. It should be noted that although the gate electrode G
overlaps the source region 36 and the drain region 38 as well as
the gate region 47 and a drift region 56, the gate electrode G
- is separated from the drift region 56 by a thick insulating
layer of silicon dioxide, i.e. layer 12, which is in the order
of 1500 A to 3000 A thick.
In the MOS field effect device thus formed, and shown in
FIG. 9, the drift region 56 which is disposed beneath the thick
silicon dioxide layer 12 connects the gate region 47 to the
drain region 38. The drift region 56 is an n-type conductive
region formed at the surface of the silicon substrate 10 adjacent
the silicon dioxide layer 12 because of fixed positive charge,
generally referred to as QSS~ present in the silicon dioxide
layer 12, and also as a result of the positive gate voltage
which turns the drift region 56 "on" to a greater degree when
the short channel is biased "onn. Also, as is Xnown, when
the silicon dioxide layer 12 is initially thermally grown over
the surface of the silicon substrate 10, as discussed in
connection with FIG. 1, and then cooled in an oxygen environ-
ment, positive charges are created in the silicon dioxide layer
- 1~ to create a strong inversion in the contiguous high resis-
tivity p-type conductivity silicon substrate 10 surface to form
an n-type conductivity drift region 56.
Alternatively, the drift region 56 may be formed by ion
implanting a suitable n-type dopant, as phosphorous atoms,
//~/7~ 30 into the surface of the structure either prior to or subsequent to
1138571
the ion implantation of the boron atoms discussed in connection
with FIG. 7. That is, referring to FIG. 10, after the thin
silicon dioxide layer 46 is deposited over the surface of the
structure phosphorous atoms are ion implanted into the silicon
substrate 10 disposed beneath the silicon dioxide layer 12, as
shown, to form, after annealing, the drift region 56'. The
boron atoms are then ion implanted to form the gate region 47;
however, the depth of such implanted boron atoms is less than
the depth of the implanted phosphorous atoms and such implanted
boron atoms do not enter the drift region 56'. Further, it
should be noted that the implanted phosphorous atoms are dis-
posed beneath the source, drain and gate regions 36, 38, 47
because the silicon dioxide layer 46 is thinner over such
regions than the thick silicon dloxide layer 12 disposed over
the drift region 56'. The phosphorous implant serves to
reduce the impedance of the drift region 56' and may also serve
to form a buried channel in the drift region 56' to reduce gate
electrode capacitance. The structure is then processed as
described in connection with FIGS. 8 and 9 to complete the
MOS field effect device.
The length of the drift region 56 (or 56') may be adjusted
to the desired circuit conditions and may range from about one
micrometer to five micrometers. The drift region ~6 (or 56')
eliminates the short channel effects (i.e. punch through from
drain to source and dependance of the gate threshold voltage on
the ~rain voltage) which affect many short channel devices
without much additional expenditure in wafer area. ~urther,
_ the techniques described above enable the fabrication of
~ hc
devices suited for~relatively high voltage levels prevailing in
many analog circuits and charge-coupled devices.
- 12 -
~13E}571
Having described preferred embodiments of this invention,
it is evident that other embodiments incorporating these
/~ concepts may be used. For example, a relatively thin silicon ~;tr;~
layer, 300-500 A thick, may be formed between the metalization
layer 54 and the silicon dioxide layer 46. Also, the drift
region 56 may be formed by ion implanting phosphorous or
arsenic atoms into the silicon substrate 10 prior to the
formation of silicon dioxide layer 12 and silicon nitride
layer 14. Still further, the source and drain electrodes
S, D may be formed in a separate masking step than that used
to form the gate electrode G. Also, the gate electrode G may
be doped polycrystalline silicon, aluminum or a composite layer
of titanium and aluminum. Further, the gate electrode G need
not extend to the overlap of the drain region 38, but can
terminate at one end over the silicon dioxide layer 12. Still
further, while~ n-channel device has been described, a
p-channel device may be formed in analogous fashion by using
dopants of opposite polarity. Also, the termS source and
drain regions may be used interchangeably. It is felt, there-
fore, that this invention should not be restricted to thedisclosed embodiments, but rather should be limited only by
the spirit and scope of the appended claims.
