Note: Descriptions are shown in the official language in which they were submitted.
113~ ;5
The invention relates to a circuit system for the
generation of a direct control voltage dependent upon an alter-
nating voltage with a charging capacitor which can be charged
through at least one charging circuit and can be discharged
through at least one discharge circuit, specifically for the
generation of a direct control voltage in a system for dynamic
compression or expansion.
U.S. Patent No. 3,969,680 of Wermuth, issued July 13,
1976 has disclosed the use of a circuit system of this kind as
a control voltage generator in a compander system.
To the input of the control voltage generator is
supplied on "compression" the alternating voltage output signal
and on "expansion" the alternating voltage input signal derived
from an amplifier located in the useful signal path, the ampli-
fication of which is electronically controllable (adjustable)
via another electronically controllable amp]ifier. The direct
voltage output signal of the control voltage generator is fed
both into the control input of the amplifier located in the
useful signal path and also to the control input of the further
amplifier. The control voltage generator acts in this context
so that on exceeding of a threshold value by the alternating
voltage fed into the input of the control voltage generator it
generates a quickly rising direct voltage which varies the ampli-
fication of the amplifier located in the useful signal path
until the alternating voltage at the input of the control
voltage generator has dropped back below the said threshold
value.
One example of an embodiment of the prior art control
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voltage generator comprises a charging capacitor one terminal
of which is connected to ground and the other terminal of
which is wired on one hand through a charging resistance to an
operating voltage (supply) and on the other hand through a
discharge transistor to ground. The alternating potential fed
into the transistor base is rectified in the transistor. On
transgression of a threshold value by the alternating voltage
at the transistor base the capacitor charged through the re-
sistance is simultaneously relatively swiftly discharged through
the instantaneously current conducting switched transistor. In
contrast to this very fast discharge of the charge capacitor its
charging is mainly determined by the magnitude of the charging
resistance.
It had been found, e.g. in the case of an expander
circuit, that two inherently contradictory requirements have to
be fulfilled in the described charging of the charging capacitor.
The charging should, on the one hand, proceed as rapidly as
possible so that in the event of a suddenly occurring prolonged
decrease in the amplitude of the useful signal requiring to be
processed, it is possible to effect a quick correction in the
amplification of the amplifier located in the useful signal
path. Undesirable noise signals would otherwise become audible
in such a case during the long transition time caused by the
slow charging. Charging should, on the other hand, not proceed
too rapidly to avoid that, in the case of the lowest frequencies
to be processed, control is so fast as to produce distortions of
the pure sinusoidal oscillations with the lowest frequencies.
~ t' ~ r
This problem is particularly manifested in wide band ~ompandor
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~.
systems because in these all frequency ranges including even the
lowest frequencies are processed in the one single available
channel.
The above considerations apply correspondingly also,
when in another exemplary embodiment of the prior art control
voltage generator, it is not discharging but charging which is
effected through a transistor. The above considerations apply
in this case to the discharge of the charging capacitor.
A compromise has to be made in the choice of the
charge and discharge time constants to meet the aforementioned
contradictory requirements.
The invention has the object of providing a circuit
system in which the aforesaid compromise can be solved better
so that there is an improvement either in the behaviour of the
cirsuit in respect of the undesirable audible noise signals
(noise behaviour) at relatively slight distortion or in the
behaviour in respect of the distortions at relatively good
noise behaviour.
According to the invention there is provided a circuit
system for the generation of a direct control voltage dependent
upon an alternating voltage with a charging capacitor which can
be charged through at least one charging circuit and can be
discharged through at least one discharge circuit, specifically
for the generation of a direct control voltage in a system for
dynamic compression or expansion, having arranged at least in
one charging circuit and in at least one discharge circuit an
electronically controllable current path, the control inputs
of which are connected through one control lead each with one
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output of a comparator for the alternating voltage or of a logi-
cal element for two comparators, in that a time-lag circuit is
arranged in one of the control leads and in that the signal out-
puts of the two control leads are inverting in respect of one
another.
The invention will be explained in greater detail with
the aid of two examples of embodiments which are shown in the
accompanying drawing, in which:
Figure 1 shows the basic diagram of the circuit in
accordance with the invention;
Figure 2 shows the voltage and current patterns at
various parts of a circuit per Figure l;
Figure 3 shows a beneficial form of an embodiment of
the circuit in accordance with the invention;
Figure 4 shows the voltage and current patterns at
various parts of the circuit of Figure 3.
Figure 1 shows the basic diagram of the circuit system
in accordance with the invention. Such a circuit is typically
inser*able as a control voltage generator into the function
blocks designated by 5 of the circuit shown in Figures 1 and 2
of the above-mentioned U.S. Patent No. 3,969,680.
The circuit in accordance with the invention has an
input 1 for the alternating voltage and an output 2 for the
direct control voltage. The input 1 is wired through a resist-
ance 3 to a non-inverting input 6 of a differential amplifier 7.
A reference voltage Uref is fed through input terminal 4 into
the inverting input 5. The differential amplifier 7 acts as
comparator and may occupy a first output state characterized by
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~t,
113~ i5
low potential (L-potential) and a second output state character-
ized by high potential (H-potential). The first output state
occurs when the alternating input voltage Ul is smaller than the
reference voltage U4; the second output state occurs when the
alternating input voltage Ul is larger than the reference voltage
U4. From the output 8 of the differential amplifier 7 branch a
first control lead 9 to the control input 11 Oc an electronically
controllable charging current path 14 and a second control lead
10 to the control input 22 of an electronically controllable
discharge current path 25. The charging current path 14 and the
discharge current path 25 are wired to a contact of a charging
capacitor 15. The other contact of the charging capacitor 15 is
applied to a reference voltage (ground). The common junction of
the charging current path 14, of the discharge current path 25
and the charge capacitor 15 is connected with the output 2.
The electronically controllable current path 14 contains a
current source 12 and an electronically controllable switch 13,
which is controllable through a control input 11. The elect-
ronically controllable discharge current path 25 contains a
current source 24 and an electroncially controllable switch 23
which is controllable through a control input 22. The control
input 11 of the charging current path is directly wired through
the control lead 9 to the output 8 of the differential amplifier
7 whereas an inverter 20 is inserted between the control input
22 of the discharge current path 25 and the output 8 of the
differential amplifier 7. The output 8 of the differential
amplifier 7 is wired to the input 16 of the time-lag element
17; one output 18 of the time-lag element 17 is wired to an
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input 19 of the inverter 20 and one output 21 of the inverter
20 is wired to the control input 22 of the electronically
controllable discharge current path 25.
The circuit system is suitable as a control voltage
c ~ ,~, fri .~ r-
C generator for compan~ systems of the kind which feed a con-
stant dynamic alternating voltage signal to the control voltage
generator in the steady state and in the event of input ampli-
tude jumps only give rise to short time span amplitude varia-
tions which are however then restored by the control circuit to
the steady state value. In the steady state the alternating
input voltage at the input terminal 1 settles down to a peak
value which just exceeds the value of the reference voltage
applied to the terminal 4.
This relationship is shown in Figure 2 by the poten-
tial patterns designated Ul and U4. For the case when the
alternating voltage peak Ul exceeds the reference voltate U4
the output 8 of the differential amplifier 7 takes on the second
output state for the duration of this transgression. The
pattern of the output voltage at the output 8 of the differ-
ential amplifier 7 is shown by the curve designated U8. Thevoltage Ug in the control lead 9 and the current I14 through
the charging current path 14 have the same shapes as U8 and are
shown as one curve. A high potential at the output 8 is passed
through the control lead 9 to the control input 11 of the elec-
tronically controllable current path 14 and renders the current
path 14 conducting. A current I14 is fed to the charge capaci-
tor 15. The voltage U8 at the output 8 of the differential
amplifier 7 is simultaneously applied to the input 16 of the
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time-lag element 17. The time-lag element 17 is a post-trigger-
able monostable trigger step and flips into the unstable state.
The output signal U17 of the monostable trigger step 17 is
passed as signal U20 through the inverter 20 to the control
input 22 of the discharge current path 25. The current path 25
whose switching state is shown by the curve I25 is controlled
to be nonconducting.
The differential amplifier 7 readopts the first out-
put state, i.e. low potential at the output 8, for the case
where the alternating input voltage Ul no longer exceeds the
value of the reference voltage U4. This makes the current path
14 non-conducting. The monostable trigger step 17 maintains
the unstable state for a delay time tl7 in the other control
lead. After lapsing of the delay time it flips back into the
stable state. This renders the discharge circuit 25 conducting.
This just described performance sequence has, on a direct con-
trol voltage U2 tappable at the output terminal 2, the effect
that it maintains its value during the delay time tl7 when the
peak of the alternating input voltage Ul no longer reaches the
threshold value preset by the reference voltage U4. The direct
control voltage is changed only after lapsing of the delay
time tl7. This prevents distortion by control actions of the
shape of the curve of the alternating voltage signal passing
r~, ~ G r . d~,~
~_ through the co~a~o~.
In the case of the example shown an alternating input
voltage exceeding the value of the reference voltage leads to
an increase in the direct control voltage. When however a
contrary (opposed polarity) variation of the direct control
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S
voltage in relation to the alternating input voltage is required
for the control of the correcting elements in an amplifier with
variable transfer constant it becomes necessary to change over
the charging current path and the described circuit.
A beneficial improvement of the invention is shown in
Figure 3. The circuit has an input 26 for the alternating
voltage and an output 27 for the direct control voltage. The
input 26 is connected through a first resistance 28 with an
non-inverting input 33 of a first differential amplifier 34 and
through a second resistance 29 with an inverting input 36 of a
second differential amplifier 38. A positive reference voltage
is supplied through an input terminal 30 to an inverting input
32 of the first differential amplifier 34 and a negative refer-
ence voltage is supplied through an input terminal 31 to a non-
inverting input 37 of the second differential amplifier 38.
Outputs 35, 39 of the two differential amplifiers are wired to
the inputs 40, 41 of a first OR-logical element 42. The
previously described circuit operates as a comparator, whereby
one output 43 of the OR-logical element 42 can take on a first
and a second output state. The first output state occurs when
the positive half wave of the alternating voltage is smaller
than the positive reference voltage and the negative half wave
of the alternating voltage is larger, i.e. more positive, than
the negative reference voltage. The second output state occurs
when the positive half wave is larger than the positive refer-
ence voltage or the negative half wave is smaller, i.e. more
negative, than the negative reference voltage. From the output
43 of the OR-logical element 42 branch a first control lead 44
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1~39;~6S
to a control input 47 of an electronically controllable charging
current path 61 and a second control lead 45 to a control input
58 of an electronically controllable discharge current path 62.
The charging current path 61 and the discharge current path 62
are wired to a contact of a charging capacitor 49. The other
contact of the charging capacitor is wired to a reference vol-
tage (ground). The common junction of the charging capacitor
49, the charging current path 61 and the discharge current path
62 is wired to the output 27 and the one contact of a resistance
50. The other contact of the resistance 50 is wired to a
reference voltage (ground). The resistance 50 is a non-control-
lable discharge current path. The electronically controllable
charging current path 61 comprises a current source 46 and an
electronically controllable switch 48 controllable through a
control input 47. The electronically controllable discharge
current path 62 comprises a current source 60 and an electroni-
cally controllable switch 59, which is controllable through a
control input 58. The control input 47 of the charging
current path 61 is directly connected with the output 43 of the
first OR-logical element 42. The second control lead 45 between
the output 43 of the first OR-logical element 42 and the control
input 58 of the electronically controllable discharge current
path 62 contains the series circuit comprising a post-trigger-
able monostable trigger step 52 and an inverting OR-element
(NOR) 56. In this the output 43 of the first OR-logical element
42 is wired to a trigger input 51 of monostable trigger step 52
which responds to the negative flank the output 43. The output
53 of the monostable trigger step 52 is wired to one input 55
_g_
1~3~S
of the inverting OR-element 56. The output 57 of the inverting
OR-element 56 is wired to a control input 58 of the controllable
discharge current path 62. Another input 54 of the inverting
OR-element 56 is wired to the first control lead 44.
The voltage and current patterns of a circuit in
accordance with Figure 3 are shown in Figure 4. The curves are
designated with the letter U for voltage and I for current
corresponding to the reference symbols of the circuit parts in
Figure 3 at which voltages and currents occur.
Employment of the circuit in a closed control circuit
will result in a steady state value for the alternating input
voltage U26 such that its peaks just exceed the limits preset
by the two reference voltages U30, U31; i.e. they exceed the
positive reference voltage U30 and fall below the negative
reference voltage U31. For the duration of the transgression
the output 43 of the OR-logical element 42 takes on the second
output state (U43). In the present case a low potential
(L-potential) corresponds to the first output state, and a high
potential (H-potential) corresponds to the second state. The
20 control input 47 of the electronically controllable charging
current circuit 61 is directly connected through the first
control lead 44 with the output 43 of the OR-logical element 42.
The charging current path 61 is controlled to be current
conducting (I61) when H-potential is applied to the control
input 47 (U47).
In the steady state the charging capacitor 49 (U49)is
periodically charged through the charging current path 61 (I61).
This will occur specifically for as long as the alternating
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113~5
voltage input peaks (U26) exceed the limits preset by the refer-
ence voltages U30, U31. The charge slowly draining away through
the discharge resistance 50 is just compensated by the periodi-
cally occurring charging.
The discharge current path 62 (I62) is controlled to be
non-conducting during the time span in which the charging current
path 61 (I61) is controlled to be conducting at its control in-
put (47) by H-potential. This control is achieved by the inver-
ting OR-element 56 whose output takes on L-potential when one or
both inputs 54, 55 are triggered with H-potential. Since the
input 54 is connected with the control lead 44 an H-potential in
the control lead 44 will produce an L-potential at the control
input 58 of the discharge current path and thereby its blockage.
This avoids both electronically controllable current paths
becoming current conducting simultaneously as a result of which
an uncontrolled charging state would be produced in the
capacitor 49.
Whenever the instantaneous value of the alternating
input voltage U26 returns after exceeding the limits preset by
the reference voltages U30 U31 back to the zone lying between
these limits, the output 43 of the first OR-logical element 42
returns also from the second switching state (H-potential) to
the first switching state (L-potential). The thereby occurring
negative pulse flank at the input 51 (U51) of the post-trigger-
able monostable trigger step 52 then changes the trigger step
52 to the unstable state, which in the present case is character-
ized by H-potential at the output 53 (U53). Since in the
event of a constant alternating current input signal U26 at the
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il39;~t~S
C input 26 the output 43 of the OR-logical element -~ switches in
every oscillation period twice to and fro between H-potential
and L-potential (U43) the monostable trigger step 52 is periodi-
cally post-triggered and maintains its unstable switching state
(u53).
On variation of the alternating input voltage the new
value of the direct control voltage at the output 27 is obtained
by variation of the time in which the charging current path 61
is controlled to be current conducting. The charging capacitor
49 receives a raised final charging voltage when the "current
conducting" switching state is extended; on shortening of the
"current conducting" switching state the continuous discharge
through the resistance 50 is not correspondingly compensated
and the final charging voltage is reduced. In the latter case
the speed at which the control voltage can vary towards lower
values is initially limited by the time constant of the
capacitor 49 and resistance 50.
In none of the cases considered so far comprising
1. steady state of the alternating input voltage
0 2. increase of the alternating input voltage at an arbitrary
speed
3. slow falling off of the alternating input voltage has there
been an activation of the electronically controllable discharge
current path 62. This changes when the alternating input vol-
tage falls from a finite value very rapidly to a low value and
maintains this low value.
Directly the alternating input voltage U26 no longer
reaches the critical value given by the reference voltages U30,
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1139365
U31 the output 43 of the OR-logical element will cease to take
on H-potential but will retain L-potential (U43). The charging
capacitor 49 will consequently be no longer recharged through
the charging current path 61 and will slowly lose charge through
the resistance 50.
Since no more trigger pulses are supplied to the post-
triggerable trigger step 52 it will remain in the unstable state
only for the delay time t52 counted from the last trigger pulse.
If after lapsing of the delay time t52 the output 43 has still
L-potential (U43) both inputs 54, 55 of the inverting OR-logi-
cal element will receive L-potential whereupon the output 57
takes on H-potential (U57) and the electronically controllable
discharge current path 42 (I62) is controlled to be current
conducting. The discharge of the charging capacitor 49 (U49)
takes place then very much faster than previously through the
resistance 50.
If following this the alternating input voltage rises
again and exceeds the limits preset by the reference voltages,
the output 43 of the OR-logical element will then again take on
H-potential as a consequence of which the discharge circuit 62
will be controlled to be non-conducting and the charging circuit
61 will be controlled to be current conducting.
The behaviour of the circuit in accordance with the
invention after a rapid falling off in the alternating input
voltage has the result that on one hand there occurs no
falsification of the curve of the decaying useful signal and
that on the other hand the transfer constant of the controllable
amplifier is changed well in time so that no interfering noise
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1~39;~5
is noticeable.
The advantage of the circuit of Figure 3, with twocomparators, over the circuit of Figure 1 with one comparator,
is that for the achievement of a given low non-linear distortion
factor during variation in amplification the delay time t52 has
to be chosen only half as large as the delay time tl7 in a
circuit with only one comparator. In a circuit per Figure 1 it
is e.g. only possible to detect the positive half-wave of an
input signal. The circuit will not recognise whether or not
this is followed by a negative half-wave and this has to be
allowed for through the choice of an appropriately longer delay
time.
Another difference between the circuit shown in
Figure 3 and that shown in Figure 1 is that a trigger pulse is
supplied to the monostable trigger step not at the instant at
which the instantaneous value of the alternating input voltage
exceeds one of the limits preset by the reference voltages, but
only at the instant in which the instantaneous value of the
alternating input voltage returns again into the zone between
these limits. Compared with Figure 1 it is possible to reduce
the delay time of the monostable trigger step by the value by
which a very low frequency alternating voltage could exceed one
of the limits preset by the reference voltage. A long delay
time is however unnecessary at high frequencies in respect of
the non-linear distortion factor and prevents a fast correction
of the transfer constant.
In cases where the circuit per Figure 3 is used to
achieve a variation of the direct control voltage opposite
A~
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(of opposed polarity) to the change in the alternating input
voltage, it is necessary to design the current path 62 as a
charging current path and the current path 61 as a discharge
current path. The other pole of the resistance 50 must further-
more be connected with another reference voltage.
It is also possible to design the comparator so that
the outputs vary their output states from H-potential to
L-potential when the alternating input voltage exceeds the limits
preset by the reference voltages. The remaining circuit may
also be designed in negative logic. The OR-logical element
would e.g. have to be replaced by an AND-logical element and
the inverting OR-logical element by an inverting AND-element.
It would also be necessary to employ a monostable trigger step
with a trigger input which responds to the positive flank and
likewise an inverting output to the output 53. It is finally
possible to design a combined positive and negative logic
circuit.
It is furthermore possible to design the resistance
50 in the form of a constant current source and the current
¢ 20 source ~ in the form of a resistance.
In a beneficial form of embodiment of the system in
accordance with the invention the delay time of the monostable
trigger step should be about 25 ms. This will have the result
that a non-linear distortion factor due to the control system
is down to a lowest frequency of 20 Hz determined (governed)
only by the time constant of the resistance 50 and of the
capacitor 49. The time constant formed from the charging
113~6S
capacitor 49 and the combined discharge current circuit com-
prising the resistance 50 and the current path 60 can be rated
so small that a correspondingly short transition time for the
correction of the electronically controllable amplifier will be
achieved when the level of the useful signal drops suddenly.
This transition time which is made up by the constant delay of
25 ms and the rapid discharge time of e.g. 150 ms can in fact
be made shorter than the time required by the human ear to
readapt itself to low-level noises after abruptly ceasing loud
noises. Noise signals which occur during the transitional
correction time will therefore not be noticed.
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