Note: Descriptions are shown in the official language in which they were submitted.
1139~93
Specification
Title of the Invention
Field Effect Transistor Devices
and Methods of Manufacturing the Same
Background of the Invention
This invention relates to a field effect transistor,
more particularly a field effect transistor device in which
function regions which constitute the field effect transistor
are disposed in a compound semiconductor layer on a semiinsu-
lating substrate made of a similar compound semiconductor and a
method of manufacturing such transistor.
An ordinary field effect transistor now being used
widely is constructed such that an N type semiconductor layer
made of such compound semiconductor as GaAs is epitaxially grown
on a semiinsulating substrate made of the similar compound semi-
conductor, that a source electrode and a drain electrode having
a predetermined spacing are attached to the surface of the semi-
conductor layer with ohmic contacts and that a gate electrode in
a Schottky barrier junction with the semiconductor layer is dis-
posed between the source and drain electrodes. Such a construc-
tion is disclosed in a Charles A. Liechti's paper entitled
"Microwave Field-Effect Transistor 1976", I.E.E.E. Transaction
on Microwave Theory and Techniques, Vol. MTT-24, No.6 pages 279
- 300, June, 1976.
In a transistor of this construction, a depletion layer
extends into the semiconductor layer from the Schottky junction
-
~39893
according to the magnitude of a control voltage impressed across
the gate and source electrodes so that the cross-sectional area
of a ~rain current patb in the semiconductor layer is narrowed
in accordance with the gate control voltage.
Moreover, the transistor constructed as above described
involves the following problems.
First~ly, as the semiconductor layer is epitaxially
grown on the semiinsulating substrate, in most cases, portions
of the semiconductor layer near the substrate have crystal de-
fects. In addition, since these portions are formed at the ini-
tial stage of epitaxial growth, the impurity concentration is
difficult to make uniform due to manufacturing technique. For
this reason it is extremely difficult to make uniform the char-
acteristics of the transistor at or near cutting off the drain
current (gate pinch off) regardless of an accurate control of
the thickness of the semiconductor layer as the subsequent
process for manufacturing steps of the transistor. Thus, this
problem is one oE the factors that decreases the yield of
satisfactory transistors. This is more particularly true in
transistors assembled into an integrated circuit. For example,
it is desired to ON/OFF control the drain current with rela-
tively small gate control voltage of about ~ 1 volt, the thick-
ness of the semiconductor layer becomes about 0.1 to 0.15 micron
- for 1 x 1017 through 5 x 1016 cm 3 of N type impurity concentra-
tion in ~aAs so that the problem caused by the construction
described above results in a large dispersion in the gate pinch
-- 2 --
~139893
off voltage.
For this reason, it is difficult to assemble transis-
tors into an integrated circuit for commerical use.
Furthermorer the transistor of this type is manufac-
tured by the steps of forming a semiconductive layer of oneconductivity type by implanting ions of an impurity into one
surface of a semiinsulating substrate made of such compound as
GaAs, forming source and drain elec~rodes in an ohmic contact
with the surface of the substrate, and then forming a gate
electrode to form a Schottky junction. Transistors prepared by
this method are disclosed in a B.W.Welch et al paper entitled
"Gallium Arsenide Field Effect Transistor by Ion Implantation",
Journal of Applied Physics, vol. 45, No. 8, pages 3685-3687,
Aug. 1974 and a R.G. Hunsper~er et al paper entitled
"Ion-Implanted Microwave Field Effect Transistors in GaAs",
Solid State Electronics, Vol. 18, pages 349-352.
With the transistor of the construction described
above, for the purpose of recovering distorted crystal structure
caused by the implanted ions which are implanted into the semi-
conductor substrate for forming the semiconductor layer and ofelectrically activating the implanted ions of an impurity it is
necessary to subject the implanted substrate to an annealing
treatment in which the substrate is heated to a high temperature
of 800 to 900C. However, such annealing treatment accompa-
nies the following problem. More particularly, such residualimpurities as chromium, silicon, etc. contained in the substrate
~i~
at the time of preparing the semiinsulating semiconductor sub-
strate tend to diffuse or unwanted external impurities might be
incorporated, or impurities implanted into a predetermined
portion at a predetermined concentration tend to diffuse. In
addition, when the surface of the semiinsulating semiconductor
substrate is subjected to thè high temperature described above,
such surface of compound semiconductor as GaAs often decom-
poses. Due to various phenomena appearing at the time of an-
nealing it is difficult to obtain at a high reproducability a
semiconductor having a uniform thickness and containing an
impurity at a uniform concentration. This also causes disper-
sion in the pinch off voltage of the resulting transistor thus
decreasing the yield.
Summary of the Invention
1~ Accordingly, it is a principal object of this inven-
tion to provide a field effect transistor and a method of
manufacturing the same at a high yield which is suitable to
assemble an integrated circuit.
Another object of this invention is to provide a field
effect transistor device and a method of manufaaturing the same
capable of reducing dispersion in the gate pinch off volta~e.
Still another object oE this invention is to provide
an improved field effect transistor device suitable for use in
a logic circuit consuming only a little electric power.
A further object of this invention is to provide an
improved field effect transistor device and a method of manu-
1139893
facturing the same capable of determining the size of a channel
to be formed according to the accuracy of a mask utilized at
the time of manufacturing the transistor device and having a
unifor~ characteristic and can be manuactured at a higher
yield than the prior art field effect transistors.
A still further object of this invention is to provide
a field effect transistor device and a method of manufacturing
the same capable of having excellent characteristics not
affected by the crystal quality of an compound semiconductor
layer formed by growing on a semiinsulating compound semicon-
ductor substrate.
Yet another object of this invention is to provide a
field e~fect transistor device and a method of manufacturing
the same having characteristic not affected by various factors
caused by a high temperature annealing treatment utilized at a
time when an N type semiconductor layer is formed in a semi-
insulating substrate by N type ion implantation technique.
According to this invention, these and other objects
can be accomplished by providing a field effect transistor co~-
prising a semiinsulating layer made o a compound semiconduc-
tor, a compound semiconductor layer of a first conductivity
type which is disposed on sald semiinsulating layer, at least
two semiconductor gate regions of a second conductivity type
different from the first conductivity type which extend from a
main surface of the semiconductor layer substantially to said
semiinsulating layer and which are spaced apart from each
~139893
other, source and drain electrodes arranged at both sides of
said semiconductor regions to have an ohmic contact therewith,
and a gate electrode means which has an ohmic contact with said
semiconductor gate regions and which further has a Schottky
contact with the semiconductor layer interposed between the
semiconductor gate regions, a periphery of a resulting transis-
tor being in contact with at least two of said semiconductor
gate regions.
According to this invention, these and other objects
can be accomplished by providing a method of manufacturing a
field effect transistor comprising the steps of forming a semi-
insulating layer made of compound semiconductor and a first
conductivity type compound semiconductor layer disposed on said
semiinsulating layer, forming at least two semiconductor gate
regions of a second conductivity type different ~rom the first
conductivity type which extend from the main surface of said
compound semiconductor layer substantially to said semiinsulat-
ing layer and which are spaced from each other by implanting an
impurity of the type different from the first conductivity type
from above the main sur~ace, and forming gate, source and drain
electrodes at both sides of said semiconductor gate regions as
well as on said semiconductor gate regions by applying metal
layers which are in an ohmic contact therewith, said second
step including a process to locate said at least two semicon-
ductor gate regions so as to be in contact with a periphery ofa resulting transistor and said third step including a process
. .
,, ,
-- 6 --
1139893
to apply the metal layer to be used as the gate electrode so as
to be in an ohmic contact with the semiconductor gate regions
and further in a Schottky contact with the semiconductor layer
interposed between the semiconductor gate regions.
Brief Description of the Drawing_
In the accompanying drawings:
Fig. 1 is a perspective view showing one embodiment of
a field effect transistor device embodying the invention;
Fig. 2 is a cross-sectional view taken along a line
II-II shown in Fig. l;
Fig. 3 is a graph showing tbe voltage-current charac-
teristic obtained when electrodes are formed on a GaAs sub-
- strate of P type;
Fig. 4 is a graph showing the voltage-current charac-
teristic detailed sectional view showing a manner obtained whenelectrodes are formed on a GaAs substrate of N type;
Figs. 5A through 5F show successive steps of one
method of manufacturing the transistor shown in Fig. l; and
Fig. 6 is a cross sectional view showing the main
2~ parts of a modified embodiment of the field effect transistor
of Figs. 1 and 2.
Description of the Preferred Embodiments
Figs. 1 and 2 show a preferred embodiment of the field
effect transistor device according to the present invention.
In the drawings, the semiconductor substrate 211 is made of
such compound as GaAs or InP. The substrate 211 has a thick-
1139893
ness of about 300 microns and a high specific resistivity of
106 ohm cm or more. On the substrate 211 is formed an N type
compound semiconductor layer 212 made, for instance, of GaAs or
InP, by expitaxial growth. The semiconductor layer 212 has an
impurity concentration of 5 x 1016 atoms/cm3, for instance,
and a thickness of 0.1 to 1 micron. On the main sur~ace of the
semiconductor layer 212 there are arranqed metal layers 213 and
214 comprising gold-tin and gold-germanium or the like in par-
allel with a suitable spacing of, for instance, 5 - 10 microns
to form source and drain electrodes. These metal layers 213
and 214 here are arranged so as to be in an ohmic contact with
the semiconductor layer 212.
A plurality of P type semiconductor gate regions 215a,
- 215b, 215c and 215d are formed in the semiconductor layer 212
along a straight line at about the center between the metal
layers 213 and 214 and extending in parallel thereto and with a
spacinq of, for instance, 4 microns, the impurity concentration
thereof being 1 to 20 x 1018 atoms/cm3. These semiconductor
gate regions 215a through 215d are formed by implanting ions of
Be, Cd or Zn into the semiconductor layer 212 and have a
substantially circular cross sectional con~iguration, extending
from the main surface of the semiconductor layer 212 either to
the interface between the semiconductor layer 212 and the
semiinsulating substrate 211 or more deeply into the substrate
211. A metal layer 217 made of molybdenum or chromium is
arranged as a gate electrode on the gate regions 215a through
1139~393
215d and on the channel regions 212a through 212c of the
semiconductor layer 212 which locate in the spaces between said
gate regions 215a to 215d. The metal layer 217 directly
contacts with the N type semiconductor region 212a, 212b and
212c interposed between each gate regions 215a through 215d to
form a Schottky barrier junction therebetween.
Fig. 3 is a graph of the characteristics in order to
prove that when metal layers are applied on a P type semicon-
ductor gate region, an ohmic contact is formed therebetween
while Fig. 4 is a graph of the characteristics in order to
prove that when metal layers are applied on an N type semicon-
ductor layer a Schottky junction is formed therebetween.
Fig. 3 shows the voltage-current characteristics ob-
- tained by forming the first electrode made of Mo, o 42 microns
in diameter and of 0.2 to 1.0 micron in thickness on the P type
GaAs substrate, forming the second electrode made of Mo, of 52
microns in inner diameter and of 0.2 to 0.3 microns in thick-
ness which is arranged concentric with the first circular
electrode and applying a voltage between the said electrode
wherein the impurity concentration on the surface of the GaAs
substrate being more than about 5 x 1013cm and each Mo
electrodes being formed by the vacuum deposition techni~ue upon
being heated at the temperature of 300 to 500C. As shown in
the linear voltage-current characteristics, when electrodes are
formed on a P type GaAs substrate, an ohmic contact is formed
therebetween.
93
Fig. 4 shows the voltage-current characteristics ob-
tained by forming the first and second electrodes of the size
similar to the one shown in Fig. 3 on an N type GaAs substrate
having the impurity concentration of less than 3 x 1017cm 3
under a condition similar to that in Fig. 3, and applying volt-
age therebetween. Tbe voltage-current characteristics which
are similar to a diode-characteristic indicate that a Schottky
junction is formea between electrodes and an N type GaAs
substrate when the electrodes are formed on the N type GaAs
substrate.
The structure described above permits the semiconduc-
tor layer have the following effect in addition to the effect
caused by providing a P type columnar semiconductor gate region
in an N type semiconductor
The field effect transistor constructed as above
described has the following advantages.
(L) Since a plurality of semiconductor gate regions are
formed through a semiconductor layer consisting of a compound
semiconductor formed on a semiinsulating semiconductor layer
made of similar compound from the main surface of the semicon-
ductor layer to the semiinsulating qemiconductor it is possible
to obtain field effect transistors of uniform ~uality at a high
yield, which are suitable to fabricate integrated circuits.
More particularly~ the depletion layers extending from the
semiconductor qate regions formed substantially at right angles
to the semiconductor layer 212 are formed substantially in
-- 10 --
~139a~93
parallel with tl~e direction of thickness of the semiconductor
layer and extend toward the opposed semiconductor gate regions.
For example, the state of the depletion layer will be described
in more detail with reference to Fig. 2. The depletion layer is
more or less deformed at a portion of th~ semiconductor layer
212a close to the substrate due to crystal defects or nonuni-
form COnCentratiQn of the impurity, and under a normal state
the depletion layer extends longer than other portions because
of the less concentration of N type impurities. For this
reason, these portions are connected together a little earlier
than other portions. Since these portions are located near the
substrate by a few hundreds Angstroms which is extremely smal-
ler than the thic~ness (1 micron, for example) oP the semicon-
ductor layer 212. For this reason, regardless of a variation
in the characteristics of these portions close to the substrate
the control of the drain current, that is the gate characteris-
tic, is determined by the state of elongation of relatively
uniform depletion layers at portions other than the portions
close to the substrate. Thus, it is possible to obtain transis-
tors having uni~orm characteristics. Furthermore, according tothis invention since the depletion layers extend in the opposite
directions, even when the thickness of the semiconductor layer
is extremely reduced to several hundreds Angstroms, for example,
for the purpose of obtaining logic transistors of a low power
consumption the gate pinch off characteristics of the transis-
tors are not affected by the crystal defects or nonuniform
-- 11 --
1139893
concentration oE the impurity in the direction o~ thickness.
Thus, it is possible to obtain field effect transistors consum-
ing less power than the prior art transistors.
(2) Furthermore, as it is possible to determine the width
of the channel according to the space between the semiconductor
gate regions the gate control characteristic of the transistor
can be determined by the accuracy of a mask utilized to form
the gate regions. Moreover, as the thickness of the semicon-
ductor layer is not predetermined for the purpose of determin-
ing the width of the channel as has been the prior art practice,it is possible to select any desired thickness for the semicon-
ductor layer thus readily producing a field effect transistor
of a desired current value.
(3) In addition, according to this invention, the semicon-
ductor gate regions at both ends of an array of the gate regionsare positioned at peripheries or boundary regions of the tran-
sistor region, so that it is possible to obtain a transistor
that would not be in~luenced by the construction at the
periphery of the transistor region.
(4) As above described since the semiconductor gate regions
at both ends of the array thereof are positioned at the peri-
pheries of the transistor region, it i9 possible to prevent the
gate control characteristic from being affected by the side
walls formed when the transistor is formed as a mesa type.
(5) In addition, ~y positioning the semiconductor gate
regions at the peripheries o~ the transistor region, even when
- 12 -
:1139893
the accuracy o~ positioning a mask utilized to form the
peripheries o~ the transistor may decrease more or less, it is
possible to obtain at a high yield transistors having desired
characteristics. This advantage can be enhanced by increasing
the dimension of the semiconductor gate regions in contact with
the periphery in the direction of alignment of the gate regions.
(6) The structure described above permits the semiconductor
layer have the following effect in addition to the effect caused
by providing P type columnar semiconductor gate regions in an N
type semiconductor layer formed on a semiinsulating substrate.
The metal layer 217 comprising the gate electrode is made to
form a Schottky junction 216a, 216b and 216c with an N type
semiconductor regions even if the metal layer 217 is applied not
necessarily on the semiconductor gate regions 215a through 215d
but on N type semiconductor regions 212a to 212c interposed
between the P type semiconductor gate regions as well as on the
N type semiconductor region surrounding each semi~onductor gate
regions. The junction thus formed can be utilized as a gate
junction together with the columnar P-N junctions 217a, 217b,
~17c and 217d formed by the columnar semiconductor gate regions
and the N type semiconductor region adjacent thereto. In more
detail, when a predetermined bias is applied on the gate elec-
trode, depletion layers 218a to 218d extend Erom the P-N junction
between the P type semiconductor gate region and the N type
semiconductor region adjacent thereto in the direction parallel
to the main sur~ace and, further, depletion layers 219a to 219c
- 13 -
~3;98g3
extend from the Schottky junctions 216a to 216c in the direc-
tion oE the thickness of the semiconductor layer 212 or the
direction of the semiinsuiating substrate 211. The portions of
the depletion layers 218a to 218d which are closer to the
substrate 211 extend before other portions thereof. Therefore,
when a bias voltage is applied to form depletion regions indi-
cated by the broken lines in Fig. 2 and, as the reverse bias
voltage increases, the regions encircled by the broken lines
further shrink to ~inally reach the cut-off condition. In
other words, in the structure as shown in the embodiment, even
i the semiconductor gate region is minimized, the metal layer
217 formed thereon does not require the manufacturing precision
corresponding to the size of the surface of the columnar
region. Accordingly, such structure can simplify the manufac-
turing method which is to be described below. Needless tomention, in the cases like this, the depletion layer from the
Schottky junction does not necessarily reach to the semiinsu-
lating substrate 211. The transistor structure as a whole can
also be simplified because the metal layer 217 comprising the
gate electrode can be incorporated into the transistor by
merely putting the same upon the semiconductor layer 212
including the semiconductor gate regions.
Fig. SA through 5F show an embodiment o the manuac-
turing method of the field effect transistor device shown in
Figs. 1 and 2. First, there is prepared a semiinsulating
substrate 230 comprising a compound semiconductor of GaAs or
- 14 -
ii39893
the like and with the specific resistivity of more than 106
ohm.cm and the thickness of 200 to 400 microns. Thent on the
main surface of the substrate 230 is formed an N type semicon-
ductor layer 231 comprising such compound semiconductor as GaAs
and of 1015 to 3 X 1017 cm 3 in surface impuri~y concentration
and of 0.1 to 1 micron in thickness. In this embodiment the
impurity concentration of the semiconductor layer is determined
in the range so as to form a Schottky junction between the
semiconductor layer and the metal layer to be placed thereupon.
The semiconductor layer 231 is formed by, for instance, the
epitaxial growth metbod, as shown in Fig. 5A.
Then, a photo-resist layer 233 is formed on the said N
type semiconductor layer 231 in the thickness of 0.5 to 3
micron. A plurality of windows or openings 233a to 233d are
made on the photo-resist layer 233 by the photo etching method,
forming a line. The openings or the windows in this embodiment
have circle configurations and are arranged to be spaced
- uniformly, as shown in Fig. SB.
Ions of P type impurities such as Be, Zn or Cd are
~o implanted from the direction of the arrow mark P by using the
photo-resist layer 233 with the openings as a mask. In this
case, the implanta~ion may be 150 KeV and the dose o~ the
impurities may be 5 X 1014cm 2. As a result, the impurity
ions are implanted into the semiconductor layer 231 and further
into the upper layer of the semiinsulating substrate 230 there-
under through the openings 233a to 233d o~ the pboto-resist
1139893
layer 233 so as to form implanted regions 234a, 234b, 234c and
234d on the portions corresponding to the openings 233a through
233d, as shown in Fig. 5C. The photo-resist layer 233, then,
is removed by etching using a resist remover. The substrate is
subjected to an annealing processing at a low temperature of
500 to 600C for 20 to 60 minutes in order to activate the
implanted regions 234a to 234d so as to recover the damages
caused by the implantation and to make the implantation regions
into P type semiconductor gate regions 235a to 235d having the
surface impurity concentration of more than 5 X 1018cm 3.
As a result, a P-N junction is formed between the P
type semiconductor gate regions 235a to 235d and the rest of
the layer or N type semiconductor region 231a in the semicon-
ductor layer 231 as shown in Fig. SD.
The surface of the semiconductor layer 231 is removed
in the thickness of 10 to 100 Angstroms by slightly etching the
same. The etching solution herein may be a well known mixture
of sulfuric acid, hydrogen peroxide and water.
At a next stage, a metal layer in a form of the strip
240 is formed on the semiconductor gate regions 235a to 235d
on the semiconductor layer 231 and on the N type semiconductor
region 231a interposed between the said gate regions. ~he
metal layer 240 is, for i~stance, of sucb metal as Mo or Cr to
act as a gate electrode. The metal layer 240 is formed in the
thickness of 0.1 to 1 micron by the vacuum deposition method at
the temperature of 300 to 500C as shown in Fig. 5E.
- 16 -
~3sa~3
The metal layer 240 may be deposited in the direction
perpendicular to the cross section thereof extending beyond the
P type semiconductor gate regions 235a to 235d.
Then, metal layers 242 and 243 are formed in a manner
that the metal layers are arranged at both sides o~ the strip
metal layer 240 and spaced from the semiconductor gate regions
in a suitable distance and parallel with the line direction of
the semiconductor gate regions 235a to 235d, as shawn in Fig.
5F. Fig. 5F shows the substrate o~ which cross section is
shown in Fig. SE when it is cut along the line F-F. The metal
layers 242 and 243 are formed, for instance, by an Au-Ge alloy
to function as source and drain electrodes for the field effect
transistor which is to be formed. The metal layers 242 and 243
are deposited in the thickness of 0.1 to 0.3 microns by, for
lS instance, a well known vacuum deposition method and then,
sintered for several seconds to several minutes at a tempera-
ture of 400 to 500C. The whole configuration of the thus
obtained transistor is identical with the one shown in Fig. 1.
In this embodiment, source and drain electrodes are
formed after the formation of the gate electrode. There~ore,
when metal layers 242 and 2~3 which are to form source and
drain electrodes later are being formed, the manu~acturing pre-
cision could be in the range which is comparatively low. It
would be easily understood from this embodiment that gate elec-
trodes might be formed after the formation of source and drain
electrodes.
- 17 -
9893
In the embodiment shown in Fi'gs. 1 and 2, such metals
as Mg, Li, Zn, Be, or Cd may be applied on the surface of each
P type semiconductor gate regions 215a, 215b ... in the manner
similar to the case shown in Fig. 6 by either diffusion or im-
plantat;on techniques in the formation of P+ or P + semi-
conductor regions in order to secure the ohmic contact between
the P type semiconductor gate regions 215a, 215b ... and the
metal layer for the gate electrode 217.
Moreover, Be or Cd ions may be implanted and then
annealed on the surfaces of the N type semiconductor regions
212a, 212b ...... to form compensated N surfaces 252a, 252b
..... shown in Fig. 6.
Further, O or Proton ions also may be implanted on the
surfaces of the N type semiconductor regions 212a, 212b ......
In this case, the resultant surface regions 252a, 252b ...... on
the N type semiconductor regions 212a, 212b .. ....shown in Fig.
6 substantially insulate the gate electrode metal 217 from the
N type semiconductor regions 212a, 212b ...... such that the
gate control voltage may be lar~er than the embodiment of the
Schottky barrier junction type under the forward bias condition.
The structure shown in Fig. 6 enables the metal layer
for the gate electrode to be formed with an arbitrary metal.
- 18 -
