Note: Descriptions are shown in the official language in which they were submitted.
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BACKGROUND OF THE INVENTION
This invention relates to analog-to-digital con-
verters and to a comparator circuit useful in a simplified
parallel analog-to-aigital converter.
A conventional parallel analog-to-aigital (A/D)
` converter compares an analog input signal to each input from
a set of discrete voltage levels which define voltage inter-
vals. The converter produces a digital output indicative of i'
the voltage interval into which the analog input signal falls.
A separate voltage comparator is associated with each refer-
ence level to compare the analog input to that level. Hence,
for an n bit digital code which can indicate any of 2n voltage
intervals defined by 2n-1 quantum levels, 2n-1 comparators
are required. The reference inputs to the com,parators are ,
generally taken from a string of 2n resistors of equal resist-
ance values arranged in series across a reference voltage.
The outputs of the 2n-1 comparators drive a logic tree to
decode the comparator outputs into n bits. Using the con-
ventional circuits, a three bit converter requires seven
comparators and a seven-input logic network; and a four bit
converter requires fifteen comparators and a fifteen-input 1,
logic network.
An object of this invention is to provide an im-
proved A/D converter.
A more specific object of this invention is to
provide an A/D converter of the parallel type, and ~hich
uses only a relatively small number of comparators to produce
an output code.
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According to the invention in one of its aspects,
in a parallel A/D converter for converting an analog input
signal to an n bit digital code, the analog input is compared
to 2n-1 discrete reference levels in n comparators. Each
comparator has a one bit binary output, the value of which
alternates as the analog input signal increases through the
discrete reference signal levels. Logic circuitry produces
the n bit code from the n comparator outputs. .
According to other aspects of the invention, the
logic circuitry includes n-l exclusive-OR gates.
According to yet other aspects o~ the invention,
the comparator comprises a pair of differential transistors
associated with each reference level. The collectors of the
transistor pairs are cross coupled to draw current through
two load resistors, the relative current through which indi-
cates a one bit binary output.
According to other aspects of the invention, the
comparator output resistors are connected to a differential
exclusive-OR gate and the comparator includes a latch circuit.
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BRIEF DESCRIPTION OF THE DRAWINGS
The foregoing and other objects, features, and
¦aavantages of the invention will be apparent from the follow-
ling more particular description of a preferred embodiment of
the inventio , as illustrated in the accompanyinq drawings in
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which like reference characters refer to the same parts
throughout the different views. The drawings are not neces-
: ( sarily to scale, emphasis instead being placed upon illus-
trating the principles of the invention.
Figure 1 is a schematic of an A/D converter includ-
ing three comparators for providing a three bit code;
; Figure 2 is a detailed schematic of ~e circuitry
in the comparator C3 of Figure 1 and its associated exclusive-
OR gate.
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BRIEF DESCRIPTION OF A PREE'ERRED EMBODIMENT
.
The A/D converter of Figure 1 converts the analog
input signal VIN into a three bit digital code including bits
B], B2, and B3. Seven reference levels Al, A2, A3, A4, A5,
A6, and A7 are provided by reference means 12 which incluaes
eight resistors Rl through R8 connected in series across a
positive reference voltage 14 and a ground connection 16.
Reference levels Al through A7 are taken from the nodal points
between respective resistors. m e analog input signal VIN is
compared to the seven reference levels in three comparators,
Cl, C2 and C3,
Reference A4 is applied to the comparator Cl throug
line 18. Comparator Cl is a conventional two input comparato
and provides a high output on line 19 when the analog input
signal is greater than the reference level A4 on line 18.
In the comparator C2 the analog input signal is
compared to reference levels A2 and A6 applied through respec
tive lines 20 and 22 The output of comparator C2 on line 23
is a one bit signal, the value of which alternates as the
~ana~o input 5 ignal increases p~st the refcrence leve 15 ~2
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and A6. When the analoy input is less than re~erence level
A2, the output on line 23 is low. When the input increases
( to a level greater than A2 but less than A6 the output on
line 23 is high. And when the input increases past level A6
the output on line 23 returns low.
The analog input signal is compared to reference
levels Al, A3, A5 and A7 in comparator C3. The respective
reference levels are applied to the comparator through lines
24, 26, 28 and 30. The one bit output on line 32 alternates
as the analog input signal increases through each of these
reference levels. Hence, with the analog input less than
level A1 the output on line 32 i5 low. This output switches
high as the analog input increases to a voltage level between
the reference levels Al and A3. With the analog input betwee~
levels A3 and A5 the comparator output returns to a low
condition. Similarly, with the analog input between reference
levels A5 and A7 the one bit output on line 32 is high. And
the output returns low as the analog input increases past
reference level A7.
The bit output Bl of the parallel A/D converter is
taken directly from the output 19 of comparator Cl. This
output 19 is also input to an exclusive-OR gate 34 alon~ with
the output 23 from comparator C2. The output 36 rom the
e~clusive-O~ gate 34 provides the second output bit B2 from
the converter and is also applied to a second exclusive-o~
~ate 38. The output 32 from comparator C3 is also applied
to the gate 38 to provide the third bit output B3 of the
converter on line 40.
Bit Bl on line 19 is the most significant blt of
the digital ode and should be low for the lower ~our inter-
vals of the analog input signal and high ~or the higher
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intervals. This result is obtained by connecting the mid-
; level reference A4 to the comparator Cl~ For all values of .
VI~ less -than the level A~ bit Bl is low and for all values
greater than that level Bl is high.
In the conventional binary code, the second bit B2
should indicate whether the analog input VIN is in the lower
or upper portion of the reference interval determined by bit
Bl. Hence, the reference levels applied as inputs to compar-
ator C2 are the mid-levels within either of the two reference
ranges indicated by bit Bl, that is, levels A2 and A6 -With
the analog input signal less than the voltage at A2; the Cl
col~parator output, bit Bl, is low; the output from comparator
C2 is also low and thus the output on line 36, bit B2, is low.
If the analog input increases to a level above level A2 the
output from comparator C2 on line 23 goes high while the out-
put from comparator Cl remains low, and the exclusive-OR
output on line 36 goes high to give a bit B2 value of "1".
As the analog input signal increases past level A4 the signai
on line 23 remains high but comparator Cl switches to also
give a high output on line 19. The result is a low output on :
line 36 giving a bit B2 value of "O". As the analog signal
. further increases past level A6 the signal on line 19 remains
high but comparator C2 switches to give a low output on line
23. The result is a high output on line 36 or a bit B2 value
of "1".
Bit B3 is the least significant bit and should
indicate whether the analog input is in the upper or lower .
portion of each in-terval covered by each combination of the
bits sl and s2. Hence, the inputs to comparator C3 are taken
from the mid-levels of each voltage interval defined by bits
Bland B2. In the same manner that the output oE exclusive-oR
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. gate 34 altexnates as the analog signal passes through levels
.. A2, A4 and A6, the out~ut on line 40 from the exclusive-OR
( gate 38 alternates as the analog signal passes through each
: reference level Al through A7.
A summary of the comparator outputs-and the bit
values for an analoy input signal within each reference inter-
val is set forth in the following table:
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Code
IN 1 1C2 B2C3 B3~Bl B2 B3)
VIN ~ Al 0 0 0 0 0 0 000
Al ~ V~ A2 O 0 1 1 001
A2 < V~ ~ A3 1 1 1 0 010
I A3 ~ VIN < A4 1 1 0 1 011
A4 < VIN ~ A5 1 1 1 0 0 0 100
A5 < VIN ~ A6 1 1 1 0 1 1 101
. . A6 < VIN ~ A7 1 1 0 1 1 0 110
: A7 ~ VIN 1 1 0 1 0 1 111
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The A/D converter of Figure 1 provides a three bit
digital output However, it should be readily understood
that that converter can be reduced or expanded to provide a
code having more or less bits. For example, to provide a
four bit code, each resistor Rl throuyh R~ could be center-
tapped and each of the eight reference levels so provided
would thcn dpplied to a fourth comparator, the output of
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which alternates as the analog input signal VIN passes through
those eight reference levels. The output from that fourth
( comparator would be applied along with the B3 output to a
third exclusive-OR gate to provide bit B4.
In more general terms, a parallel analog-to-digital
converter can be designed according to this invention to
convert an analog input signal .to an n bit digital code in-
cluding bits Bl, B2, ... Bj, ... Bn~ The reference means 12
establishes 2n-1 discrete reference signal levels Al, A2, ..
10 . Ak, A2n_l. Each comparator Cl, C2, Cj, ~- Cn com-
pares the analog input signal to all signal levels Ak in the
set ~A2n(m/2j)} where m is any of the first 2i 1 odd integers
Logic means set the value of each bit Bj in accordance with
the output of comparators Cl through C~. More particularly,
the logic means comprises n-l exclusive-O~ gates, each gate
having as one input thereto the output of a comparato~ C.j ,
other than Cl and the output B]_l
The simplified A/D converter of Figure 1 is made
. possible by the use of comparator circuits C2 and C3 each of
which has a plurality of reference inputs and a one bit out-
put which alternates from low to high as the analog input
passes through those reference inputs. A more detailed
schematic of the comparator C3 and its associated exclusive-O~
gate 38 is shown in Figure 2.
The comparator C3 includes a pair of differential
transistors associated with each reference level Al, A3, A5
and A7. ~ssociated with reference level Al is a pair of
differentially connected transistors including an input tran-
sistor Ql and a reference transistor Q2- The analog input
Isignal is app].ied to input transistor Ql and the reference
I].evel signal Al i.s applied to the base of transistor Q2- The
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transistor emitters are connected in common to the collector
of current sink transistor Q3. Transistor Q3 is base biased
by a constant voltage Vl and thus acts as a current sink in
the usual manner. The collector of transistor Ql is connecte
to a connector 50 and the collector of transistor Q2 is con-
nected to a connector 52.
Similarly, a pair of transistors including an input
transistor Q~ and a reference transistor Q5 is associated
with the reference level A3, The emitters of transistors Q4
and Q5 are connected to transistor Q6 which is base biased
by voltage Vl to serve as a current sink. The collectors of
transistors Q4 and Q5 are cross coupled with respect to those
of transistors Ql and Q2~ That i5, the collector of input
transistor Q4 is connected to common connector 52 and the
collector of reference transistor Q5 is connected to common
connector 50.
A third paîr of differential transistors including
input txansistor Q7 and reference transistor Q8 are associ-
ated with the reference level A5. The collectors of these
transistors are cross coupled to lines 50 and 52 with respect
to the transistor pair associated with level A3 but are
parallel coupled with respect to the pair associated with
level Al.
Differential transistor pair Qlo and Qll' associ-
ated with reference level A7, has a current sink transistor
Q12 base biased by voltage Vl. This pair of transistors is
collector cross coupled with respect to the Al and A5 refer-
ence pairs but is parallel coupled with respect to th,_ A3
reference palr.
It can be seen that the Al reference pair and the
A5 reference pair Make up a first se-t oE transistor pairs
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associated with a first set of non-successive reference in-
puts, the transistors in the first set of transistor pairs
being similarly collector coupled by common connectors 50
and 52. The A3 reference pair and the A7 reference pair
make up a second set of transistor pairs associated with a
second set of non-successive reference inputs. The transis-
tors within this second set of transistor pairs are similarl~
coupled to common connector lines 50 and 52 but are cross
coupled with respect to those transistors in the first set.
Further, the common connector means 52 connects the outputs
of the reference transistors of the first set o-f transistor
pairs in common with each other and with the outputs of
input transistors of the second set of transistor pairs.
And the second common connector-50 connects the outputs of
the reference transistors of the second set of transistors
in common with each other and with the outputs of input
transistors of the first set of transistor pairs. ~
The currenk drawn through the four differential
pairs is drawn through resistors Rg and Rlo, respectively
connected to common connectors 50 and 52 in series with the
parallel transistor pairs. The basic comparator circuit
further includes an additional current sink transistor Q13
common base connected with the other current sink transistor
and base biased by constant voltage Vl.
Assuming a proper bias to resistors Rg and Rlo and
a closed circuit to a negative supply from the current sink
emitters, the operation of the basic comparator circuit can
be set forth. With a constant current drawn through each
transistor pair, the portion of the constant current drawn
through respective collectors of each transistor in each
pair is determined by the level of the analog input signal
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VIN relative to the reference input associated with that
pair For transistor pairs in the first set, when the in-
put voltage is less than the reference level associated with
a transistor pair, the reference transistor of that pair
will conduct more than the input transistor, thereby draw-
ing current through line 52 and tending to create a voltage
drop across resistor Rlo greater than the voltage drop
across the resistor ~ . As the input voltage increases
past that reference level, the input transistor will conduct
more, thus increasing the voltage across resistor Rg rela-
tive to the voltage across resistor Rlo. On the other hand,
each transistor pair in the second set of transistors draws
more current through line 50 and resistor Rg when the analog
input is less than the respective reference level and more
current through line 52 and resistor Rlo when the analog
input is greater than the respec~ive reference level.
In the following description of the operation of
the circuit, it is assumed that each differential transistor
pair switches quickly as the analog input passes the associ-
ated reference level, that is, that with the analog input
less than the reference level substantially all of the
current drawn through the pair passes through the input
transistor and that with the input above the reference level,
substantially all current passes through the reference
transistor. It is also assumed that the differences in
: reference levels is sufficiently great so that when the base
voltages applied to the transistors of one pair are equal,
that is, where VIN equals a reference level, there is no
substantial change in current division in adjacent pairs.
Deviations Erom these assumptions will be accounted for
after the description of the basic circuit operation~
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~ith an initial input voltage less than reference
level Al, the current drawn through resistors R9 and Rlo by
the four transistor pairs is balanced due to the cross coupled
connections of successive transistor pairs. However, current
sink transistor Q13 draws an offset current through line 52
and thus increases the voltage across resistor Rlo. The value
of a one kit comparator output can be defined by the relative
voltage drops across resistors R9 and Rlo which provide means
for detecting the amount of current drawn through the first
common connector relative to the current drawn through the
second common connector. The increased voltage drop across
resistor Rlo due to the current through transistor Q13 can be
defined as a low or "0" output.
As the analog input voltage VIN increases past
reference level Al, a greater portion of the transistor Q3
current is drawn through transistor Ql relative to txansistor
Q2' Thus there is a shift in current from common connector
52 and resistor Rlo to common connector 5~ and resistor Rg~
With the analog input greater than the reference level Al, a ,-
unit of current is shifted from resistor Rlo to resistor Rg
by the ~irst transistor pair. Current is thus drawn through
resistor Rg by transistors Ql' Q5, and Qll and current is
drawn through resistor Rlo by translstor Q8 and offset tran-
sisto,r Q13- The shift of current results in greater current
through resistor Rg than through resistor Rlo, and this
condition can be defined as a high or "1" comparator output.
As the analog input signal further increases past
the A3 level, a greater portion of current is drawn through
transistor ~ relative to transistor Q in the second tran-
sistor pair. The current drawn through this pair shifts
from resistor Rg to resistor Rlo. Current is thus drawn
through resisto Rg by transistors Ql and Qll and current is
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drawn through resistor Rlo by transistors Q8 and Q13- With
three transistors drawing current through resistor R and
( only two transistors drawing through resistor Rg, the voltage
drop across resistor Rlo is greater than that across resistor
Rg and there is a low output.
As the analog input signal con~inues to increase
past reference level A5, the third transistor pair including
, transistors Q7 and Q8 shifts and the voltage drop across
, resistor R9 becomes greater than that across resistor Rlo ,
rendering a high condition. Finall~, as the analog input
signal passes reference level A7, the fourth pair of dif~er-
ential transistors shifts. This renders a low comparator
output with greater current through resistor Rlo than through
resistor Rg.
Thus the output of the above described basic com-
parator circuit C3 alternates between low and high ou'tputs
as the analog input signal VIN increases from zero lev~
through the four reference levels. The comparator C2 is of
similar circuit design but with only two differential tran-
sistor pairs. For a four bit code the fourth comparator
would include eight differential transistor pairs associated
with eight reference inputs and so on.
' The comparator output,'which includes the current
drawn through resistors Rg and Rlo, is connected to a differ~
ential exclusive-OR logic gate circuit 38 shown in detail in
Figure 2. The current through the resistor Rlo is drawn
through a gate differential transistor pair including tran-
sistors Ql~ and Q~5. The current through the resistor Rg is
dr,awn through a gate differential transi~tor pair includinc3
transistors Q16 and Q17~ A reference voltage V2 is applied
to the bases o-f transistors Q15 and Q16 and the output of the
exclusive-OR gate 3~ (Figure 1), bit s2, is applied to -the
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bases of the transistors Q14 and Q17 The collectors of
transistors Q14 and Q16 are connected to an input 54 of an
output buf~er 56. The collectors of transistors Q15 and Q17
are connected to a second input 58 to the output buffer 56.
With greater current through resistor Rlo then
through resistor R9, indicative of a low comparator output,
more current is drawn through the transistor pair Q14~ Q15
than thxough the pair Q16' Q17; hence, the pair Q14' Q15 ha5
a greater effect on the relative current signals on lines 54
: and 58. With a low bit B2 input applied to the bases of
transistors Q14 ana Q17~ transistors Q15 and Q16 conduct due
to the V2 bias. Because more current is drawn by the compar-
ator C3 through transistor Q15 than tlnrough transistor Q16
the current signal on line 58 is greater than that on line
54 and buffer 56 has a low output. This low output value of
bit B3 is in accordance with the table where there is a low
bit B2 and a low output from comparator C3. If bit B2 were
to go high, the signal would be shifted from the line 58 to
line 54 due to the increased conductance of transistor Q14
relative to transistor Q15- Thus buffer 56 would have a high 1`
B~ output which is again in accordance with the table.
With greater current flow through resistor Rg than
through resistor Rlo, the transistor pair Q16~ Ql~ has the
greater effect on the input to buffer 56. Hence, with a low
B2 input, transistor Q16 conducts greater current than does
transistor Q15 and the signal on line 54 is greater than that
on line 58. The buffer 56 provides a high B3 output. This
is the proper output indicated by the table for a low B2 value
and a high output from comparator C3. Finally, with a high
s2 value, transistor Q17 conducts more than does transistor -
Ql~ and the signal on line 58 is greater than that on line 54
resulting in a low s3 output.
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Thus the above circuitr~ provides the basic elemen
required for the comparator C3 and e~clusive-OR gate 38 in
the A/D converter of Figure 1
~ refinement in the above described comparator
circuitry is made by providing a latch circuit including
transistors Q18 and Ql9 These transistors are cross couple
as a flip-flop with the base of transistor Q18 connected to
common connector 52 and the Q1~ collector connected to common
connector 50. The Ql9 transistor base is connected to common
connector 50 and its collector is connected to connector 52.
The current bias for the flip-flop circuit is provided by a
transistor Q20 in a differential circuit. The differential
circuit, including transistors Q20 and Q21~ is in turn curre
blased by a current source 59 connected to a negative supply.
Transistor Q21 provides the total current drawn through the
current sink transistors Q3, Q6, Q9~ Q12 and Q13- Each of
these current sink transistors is connected to transistor Q21 -
through respective emitter resistors 60, 62, 64, 66 and 68
of equal resistances. Due to the equal emitter resistances
and the common base bias, the current flowing through tran-
sistors Q21 is divided equally among the five current sink
transistors.
The respective transistors Q20 and Q21 are base
biased by negative clock signals V3 and V3. With a high
V3 signal and thus a low V3 signal the current through curre t
source 58 is drawn through transistor Q20 to pro~ide bias
current in a latching mode to the flip-flop circuit of tran-
sistors Q18 and Ql9 However, with a low V3 input, and thus
a high V3 input, the current flows through the comparator
circuit and not the latching circuit in a comparison mode
The latching circuit accounts for the lack of
immedia-te switching of current frcm the reference transistor
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to the input transistors as the analog input increases past
the reference levels. If for example the analog input signal
is only slightly less than reference level Al, the transistor
Ql and ~2 are in a nearly balanced condition in the comparisor
S mode. Transistor Q2 does have a slightly greater amount o~
current flowing therethrough and thus there is a voltage drop
across resistor Rlo slightly greater than that across resisto~
Rg. But this slight difference would not be recognized by
the exclusive-OR gate. However, when con~rol signal V3 then
goes high, the voltage on line 50 at the base of transistor
Ql9 is slightly greater than the voltage on line 52 at the
base of the transistor Q18 A slightly greater portion of th~
current flowing through transistor Q20 will thus pass through
transistor Ql9 and a greater amount of current will be drawn ~,
by the latching circuit through the collector of transistor
Ql9 and resistor Rlo th=n through the collector of transistor
Q18 and the resistor Rg. This further increases the voltage
across resistor ~ 0 and thus decreases the base bias cf tran-
sistor Q18' ~n this regenerative fashion transistor Q18 is
driven to a substantially off condition whereas transistor
Ql9 is driven to a completely on condition such that the
current drawn by the current source 58 through transistor
Q20 flows primarily through transistor Ql9 and resistor Rlo,
a condition which can be recognized by the exclusive-OR gate.
Once the analog input signal has increased to a
level slightly above reference level Al, slightly more current
passes through transistor Ql than through transistor Q2 when
the circuit is in the comparison mode and, when the circuit
is switched to the latching mode, the resulting slight differ:
ence in base voltage is sensed as a slightly higher base
bias to transistor Ql~ Transistor Q18 thus draws more currer t
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through resistor Rg, thereby reducing the base bias to tran-
sistor Ql9 and providing a well defined high comparator ou~-
put. Hence, these two transistors regeneratively reinforce
the initial conditions established by even a small current
unbalance near one of the comparator critical reference pointc
In the initial analysis of the operation of the
basic comparator circuit, it was assumed that the reference -
levels were far enough apart to equalize the base voltages
of the transistors in a aif~erential pair without substantial
current flow through the input transistor of the differential
transistor pair associated with the next higher refèrence
: level. If this assumption were not valid, a shift in the
critical points where the comparator shifts from a low to a
high and a high to a low condition would be noted with
respect to the lowest and highest reference levels. This
would be due to the fact that, for example, the shift in the
comparator output at the reference Al level would be due not
only to the transfer of current flow from transistor Q2 to
transistor Ql but also, to a lesser extent, to the ~ransfex
of current from transistor Qs to transistor Q~. There would
be no shift in the critical point at reference levels A3 and
A5 because any interference from the next higher differential
transistor pair would be offset by the next lower pair. ¦
Hence, a possible remedy for the critical point shift in the
lower and upper critical points would be to provide buffer
differential transistor pairs below and above those shown.
A main advantage of the A/D converter of Figure 1
including the circuitry of Figure 2 is that only three com-
parator outputs are re~uired for a three bit code, and sim-
~0 ilarly, only four comparator outputs are required for a four
bit code. This leads to extremely simple decoding as has
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been illustrated with the two exclusive-OR gates in the three
bit code. Beyond the above is the advantage that in an inte-
grated circuit, a conservation of isolated collector regions
is possible with this A/D converter. In the conventional
parallel A/D converter a separate isolated collector poc~et
is required for each collector of each transistor in each of
the 2n-1 comparators. Hence, for a four bit code which re-
quires fifteen comparators, thirty separate collector pockets
are required. However, in the present converter only two
collector pockets are required for each comparator. For ex-
ample, for the circuit in Figure 2 one collector pocket would
be associated with common connector ~0 and another with com-
mon connector 52. With four comparators in a four bit con-
verter only eight collector pockets would be required as com-
pared to the thirty required by the conventional approach.
A further simplification in the integrated circuitr~
is possible with the multiple input comparators since the
bases of the input transistors in a comparator are in common,
Hence, the transistors Ql and Q7 in Figure 2 could be made by
forming two emitter regions in a single base region in one of
the collector po~kets. And transistors Q4 and Qlo could be
made by forming two emitter regions in a single base region
in the second collector pocket. The greater the number of
differential transistor pairs required in a comparator the
greater woula be the savings in the base regions.
The A/D converter described with reference to
Figures 1 and 2 offers great advantages in circuit simplifi-
cation and simplification of the integration of the circuit
in a multibit parallel A/~ converter. A three or four bit
parallel converter embodying this inven-tion may also be used
as the basis for a multibit successive approximation converker
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which converts three or four bits at a time~
While the invention has been particularly shown
and described with reference to a preferred embodiment there-
of, it will be understood by those skilled in the art that
various changes in form and details may be made therein with-
out departing from the spirit and scope of the invention as
.: defined by the appended claims.
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