Note: Descriptions are shown in the official language in which they were submitted.
Background of the Invention
l. Field of the Invention
This application is a division of application Serial
No. 338,851 filed October 31, 1979.
The present invention relates to apparatus and methods
pertaining to the encoding and decoding of a television
signal in a manner which deters unauthorized utilization
of the signal.
II. Description of the Prior Art
Present day subscription television systems are based
on the generally accepted fact that rendering a video
picture unviewable in a normal television receiver is most
easily and effectively accomplished by simply upsetting the
horizontal synchronization of the receiver. It is known
that horizontal synchronization can effectively be upset
for standard NTSC receivers by simply removing the
horizontal synchronization pulses or by suppressing the
horizontal synchronization pulses below the average video
level of the signal. This causes the television receiver
to try to lock horizontally on random video peaks trans-
mitted during the active or video trace line portions of
the video signal rather than on the actual horizontal
synchronization pulses. The fact that the horizontal
synchronization pulses are no longer consistenly processed
also destroys a receiver's ability to use a color reference
burst associated with the horizontal synchronization
signals, thereby causing inaccurate color reproduction.
However, known systems which employ removal or
suppression of horizontal synchronization pulses, require
employment of an encoding signal, such as a control code
or keying signal, to allow a decoder to reconstruct the
missing or suppressed horizontal synchronization pulses.
For example, the control
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I code or keying signal may take the form of negative going
'I encoding pulses inserted in selected locations of the
horizontal blanking pulses. In the ~lternative, a totally
,l independent signal, which contains the critical encoding
1 information needed to reconstruct the horizontal synchronizatiorl l -
pulses may be sent by a separate communication medium, such
as the audio portion of the television signal or a telephone
land line.
jj In addition to having the disadvantage of requiring
,~ transmission of an encoding signal to reconstruct the missing
or suppressed horizontal synchronization pulses, presently
known systems, which employ horizontal synchronization pulse
suppression or removal, generate pictures which during a
, sequence with a stationary vertical (gray or black) line
' will sometimes allow a normal receiver to horizontally lock
and display a recognizable picture, albeit with severe color 1-
distortion.
Some known subscription television systems employ
circuitry to invert all or selected portions of the video
;; signal to prevent unauthorized demodulation of the video
signal content. For example, systems have been described
which transmit even number fields with a conventional polarity
and transmit odd number fields with reverse polarity with
the resultant video signal generating a blank or washed-out
'5 , picture in a standard television receiver. Other systems -¦
' randomly invert ields or indi~idual lines of video to
estabiish a scrambled signal. To decode randomly inverted
video, as is the case with decoding missing or suppressed
horizontal synch pulses, kno~n systems generally require the
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generation and communication of an additional control code,
keying signal, or encoding signal, to allow a decoder to
correctly reinvert the randomly inverted portions of the
scrambled signal.
While systems have been described which employ aspects
of both horizontal synchronization modification and video
signal polarity modification to generate a scrambled
signal, such systems also require the further inefficient
process of generating, communicating, and decoding of some
form of encoding signal in addition to the scrambled video
signal.
It is therefore an object of the present invention to
economically and efficiently render the video portion of
the television signal scrambled to the point of being
effectively unwatchable when displayed on a standard
television receiver.
To this end the invention consists of a television
signal decoder for unscrambling a composite video signal
having a horizontal trace line of randomly selected
vertical intervals inverted and having the trace lines of
associated fields following said vertical intervals
inverted and further having randomly selected horizontal
synchronization and blanking pulses during fields of the
video signal suppressed in amplitude, the decoder
comprising: a) first means for detecting the polarity of
said trace line of vertical intervals of a video signal;
b) second means for detecting the amplitude of said video
signal during horizontal blanking pulses; c) third means
responsive to detection by said first means of said trace
line having an inverted polarity for inverting the
polarity of said associated fields; and d) fourth means
responsive to detection by said second means of said video
signal having less than a first amplitude for activating a
switch means for biasing said video signal with a second
predetermined amplitude siqnal for a selected time
interval following said detecting by said second means.
The invention also consists of a method for decoding a
scrambled video signal, which video signal has randomly
selected fields and a portion of the video section of a
vertical interval associated with said randomly selected
fields inverted and which video signal further has
randomly selected horizontal blanking pulses suppressed,
said method comprising the steps of: a) detectinq the
polarity of said portion of the video section of each
vertical interval; b) reinverting the polarity of fields
of said scrambled video signal upon detecting that the
polarity of said portion of the video section of said
associated vertical interval is inverted; c) detecting
the amplitude of the scrambled video signal during the
initial portion of each horizontal blanking pulse in said
fields; and d) activating a switch to bias the amplitude :
of the scrambled video signal with a predetermined
amplitude signal during the portion of each horizontal
blanking pulse in said fields following said initial
portion for each pulse for which said step of detecting
the amplitude reveals the amplitude as being below a
predetermined level.
Other features of the apparatus described herein are
claimed in the parent application and in divisional
application Serial No. 405,94~ ~iled ~une 24, 1982..
Brief Description of the Drawings
The accompanying drawings, which are incorporated and
constitute a part oE the specification, illustrate a
preferred embodiment of the invention and, together with
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the general description of the invention given above and
the detailed description of the preferred embodiment given
below, serve to explain the principles of the invention.
Fig. lA illustrates a portion of a video signal
including a vertical interval between the end of an even
field and the beginning of an odd field;
Fig. lB illustrates the portion of a video signal
including the vertical interval between the end of an odd
field and the beginning of an even field;
Figs. 2A and 2B illustrate inverting the polarity of a
video signal in accordance with the teachings of the
present invention;
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,j Fig. 3 illustrates suppressing the amplitude of a
i randomly selected horizontal blanking pulse in accordance
! with the teachings of the present inyention;
,I Fig. 4 is a block diagram of a video encoder incorporating
I the teachings of the present invention;
i Fig. 5 is a circuit diagram of a processing amplifier
incorporating the teachings of the present invention;
Fig. 6 is a block diagram of a transmitter exciter
, incorporating the teachings of the present invention;
Fig. 7 is a schematic diagram of one example of employing
the teachings of the present inven~ion in a differential j --
gain driver as illustrated in Fig. 6;
Fig. 8 is a schematic diagram of one example of incorporatj.ng
the teachings of the present invention in a differential
lS phase corrector as illustrated in Fig. 5;
Fig. 9 is a circuit diagram of a timing network employed
in an encoder in accordance with the teachings of the presen-t
invention;
Fig. 10 is a block diagram of decoder constructed in
accordance with the teachings of the present invention; l
; Fig. 11 is a circuit diagram of the synch and inversion ¦
control illustrated in Fig. 10;
Fig. 12 is a circuit diagram of the synch comparator,
video comparator, synch gate, and video gate illustrated in l
'S ~ Fig. 10; ¦
Fig. 13 is a circuit diagram Oe one example of the
timing net~ork illustrated in Fig. 10. ¦
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The above general description and the following detailed
description are merely illustrative of the generic invention
,l and additional modes, advantages, an~ partic~lars of this
l invention will be readily suggested to those skilled in the
l¦ art without departing from the spirit and scope of the
invention.
Description of the Preferred Embodiment
Reference will now be made in detail to the present
l preferred embodiment of the invention as illustrated in the
~ accompanying drawings.
Broadly, the present invention relates to a subscriber
television system and method for selectively communicating
, a standard television video signal. Specifically, a standard
;' television video signal may be defined as a composite video
; signal having fields with horizontal trace lines separated
by horizontal synchronization pulses and further having
; vertical intervals separating the fields, the vertical
intervals containing vertical synchronization information ¦
followed by horizontal lines separated by horizontal blankin~ ¦
' pulses.
,i For example, as illustrated in Figs. la and lb, a
composite video signal comprises even fields 10 and odd
fields 12. As shown in Fig. la, the end of each even field
10 is separated from the beginning of each odd field 12 by a
'5 I vertical interval 14 whereas as illustrated in Fig. lb the
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end of each odd field 12 is separated from the beginning of
each even field 10 by a vertical interval 15. Fields 10 and
12 include horizontal trace lines, s~veral of which are
, illustrated in Fig. la and lb by trace lines 16, 18, 20, 22,
' 24, 26, 28, and 30. In addition, the end of each odd field
12 and the beginning of each even field 10 contain half
trace lines 32 and 34, respectively. -
The horizontal trace lines of fields 10 and 12 are each
I separated by horizontal blanking pulses 36. A horizontal
, blanking pulse 36 is illustrated, for example, in Fig. 3 as
having a front porch 38 ~ypically of approximately 2 microseconcl
duration and a back porch 40 which typically carries on it a
color burst signal 42. Horizontal blanking pulses 36 each
l further carry a horizontal synchronization pulse 44 following
front porch 38 and preceding back porch 40. It is of course
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' to be understood that the present invention is also obviously
applicable to composite video signals which exhibit the
essential format in the above set out composite video signal,
although such other composite video signals may exhibit
additional features or minor modifications.
Vertical intervals 14 and 15 as illustratively shown in
Figs. la and lb typically contain vertical synchronization
i, information comprising, for example, equalizing pulses 46
followed by a serrated vertical synchronization pulse 48
li which in turn is followed by additional equalizing pulses
50. The vertical synchronization information is in turn
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typically followed by horizontal trace lines 52 which are
separated by horizontal blanking pulses 54 that contain
horizontal synchronization pulses 56.~ In additian, vertical
interval 15 which separates the end of odd fields 12 from
i the beginning of even fields 10, terminates in a half
horizontal trace line 58.
In accordance with the present invention, a subscriber
television system comprises video encoder means for randomly
~ inverting the polarity of the video signal by inverting the
polarity of a trace line of randomly selected vertical
intervals and by inverting the trace lines of associated
fields following said randomly selected vertical intervals,
the said encoder means further including means for suppressin~
the amplitude of randomly selected horizontal blanking
;, pulses during ~he fields of the video signal to form a
scrambled video signal.
In Figs. 2a and 2b, for example, a trace line 50 of
vertical intervals 62 is shown to have approximately a 75
amplitude level which in the art is normally indicative of a
black or blanking level. In Fig. 2b, trace line 60 is shown
, to have an inverted polarity such that an indication f
black or blanking level is now represented by an approximatel;
10% amplitude signal. ~ccordingly, the video signal of Fig.
! 2b represents one illustrative and not limiting example of a
' trace line of a vertical interval having an inverted polarity.
In Fig. 2a fields 64 follow and therefore may be said
to be associated with vertical intervals 62. Associated
fields 64, as was explained above with respect to fields 10
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and 12 in Figs. la and lb, contain a series of trace lines
66 separated by horizontal blanking pulses 68. Trace
lines 66 are represented in Fig. 2a to contain video
information which information, in accordance with standard
United States television practice, represents a white
signal at 10% amplitude and a black signal at 75%
amplitude. In Fig. 2b, however, trace lines 66 have been
inverted and therein represent a white signal at 75%
amplitude and a black signal at 10% amplitude signal.
Thus, while the video signal represented by Fig. 2a would
result in a normal television picture in a standard
television receiver, the video signal of Fig. 2b would
result in an inverted or "negative" television signal in a
standard television receiver. The video signal of Fig. 2b
therefore represents a partially scrambled video signal.
The subscriber television system of the present
invention further comprises a video encoder means
including means for suppressing the amplitude of randomly
selected horizontal blanking pulses during the fields of
the video signal to form a scrambled video signal.
Again, for purposes of illustration and not
limitation, attention is called to Fig. 3 wherein a
standard horizontal blanking pulse 36 of a field is
illustrated. Blanking pulse 36 is illustrated as
achieving approximately 75% amplitude for the entire time
duration 70 of the blanking pulse. In addition, following
front porch 38, a horizontal synchronization pulse 44 is
shown mounted on horizontal blanking pulse 36. A
suppressed horizontal blanking pulse 72 is illustrated in
Fig. 3 as having a constant 25% level amplitude during the
entire time duration 70. However, it should be noted that
while suppressed horizontal blanking pulse 72 has a lower
level amplitude than hori20ntal blanking pulse 36, the
differential 74 between the level of horizontal blanking
pulse 36 and the level of horizontal synchronization pulse
44 remains unaltered. Preferably, horizontal blanking pulse
36 is suppressed to a level such that horizontal synchronization
,, pulse 44 will fail to lock a standard television receiver
!! into horizontal synchronization.
In Fig. 4 there is illustrated a block diagram of one
example of video encoder incorporating the teachings of the
present invention to randomly invert a video signal as is
illustrated in Figs. 2a and 2b and to suppress randomly
selected horizontal blanking pulses as is illustrated in
; Fig. 3. The decoder of Fig. 4 comprises a standard television
camera 100 having a video output 102 coupled to the series
combination of processing amplifier 104, transmitter exciter
106, transmitter 108, and antenna 110. As is well-known to
those skilled in the art, processing amplifier 104 takes
video output 102, which comprises a composite video signal,
shapes and or reforms the color burst signal, controls the
gain and bandwidth of the video signals, and/or shapes
and/or reforms the synchronization signals to create a
reconstituted composite video signal on output line 112 to
exciter 106. ~s is also well-known to those skilled in art,
! exciter 106 continues to shape and form the reconstituted
video signal for suitable application to transmitter 10
which radiates the video signal by means of antenna llO.
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~ he encoder of Fig. 4 further includes a random signal
generator 114 and a timing network 116. As will be explained
! in greater detail below, a processin~ amplifier 104 is
l! modified to operate in connection with timing network 116 to
¦ randomly invert video output 102 by inverting the polarity
of a trace line of vertical intervals randomly selected by
generator 114 and by inverting the trace lines of associated
fields following the randomly selected vertical intervals.
Furthermore, as will be explained in detail below, exciter
1 106 is modified to operate in conjunction with timing net-
work 116 to suppress the amplitude of horizontal blanking
~ pulses during fields, which blanking pulses are also, but
" differently, randomly selected by generator 114. Thus, the
;i output of exciter 106 includes a scrambled video signal
whose polarity is randomly inverted as, for example, is
illustratively shown in Fig. 2b and whose horizontal blanking
pulses are randomly suppressed as is illustratively shown
in Fig. 3.
Timing information from video output 102 is transmitted
i from processing amplifier 104 to timing network 116 ovex
! line 118 while gating signals to randomly invert the video
signal are communicated from timing network 116 to processiny
l amplifier 104 over line 120 and gating signals to suppress
i randomly selected horizontal blanking pulse are transmitted
from timing network 116 to transmitter exciter 106 over line
122.
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j In accordance with the present invention, an encoder
includes means for generating an audio subcarrier signal,
means for generating an audio signal~ and means ~or modulatinn
I said audio subcarrier with said audio signal.
,l As also illustratively shown in Fig. 4, audio subcarrier
generator 124 is coupled between microphone 126 and transmittcl-
; exciter 106. Audio subcarrier 124 allows programmed audioto be transmitted on an audio subcarrier such as that used
for "store cast" or background music transmission by FM
radio as is well-known to those skilled in the art. Generator
124 may, for example, generate a 39.5 mhz subcarrier signal
which is modulated by audio from microphone 126. The thus
modulated signal is in turn used to modulate a 4.5 mhz
' oscillator in transmitter exciter 106.
Further in accordance with the present invention an
encoder preferably includes means for inserting data signals
into additional selected trace lines o the vertical intervals.
As also illustratively shown in Fig. 4, data register
128 is coupled ~o data gate 130. In data register 128 data
information may, for example, comprise 24 bits and be sent
at approximately a 500 khz bit rate. The format may, for
example, be 2 frame bits, 19 binary coded address bits, one
; parity bit and two command data bits. The command data bits
may serve to set or reset a magnetically latching relay in a
decoder which will either anable or disable the decoder
operation, and which will remain in its assigned state even
in the case of power interruption at the decoder as will be
explained more fully below.
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Under control of timing network 116, data gate 130
operates to pass digital information from data register 128
'I to processing amplifier 104 during s~lected trace lines of
I the vertical intervals of the video signal. For example,
three trace lines of each vertical signal may be employed to
transmit data information, and the information may be
transmitted in digital form with an uninverted portion of a
I trace line indicating a zero data bit and an inverted portion
~ of a trace line indicating a one data bit. Accordingly, the
, same mechanism utilized in processing amplifier 104 to
randomly invert the polarity of the video signal, as will be
explained in detail below, can also be employed by data gate
130 to generate data information during trace lines of the
, vertical intervals.
In Fig. 5 a circuit diagram is provided showing one
example of processing amplifier 104. In Fig. 5 processing
amplifier 104 is illustrated as comprising diplexer 200,
color burst processor 202, video processor 204, synch
detector 206, synch processor 208, and combiner 210. As is ¦
well-known to those skilled in the art, diplexer 200 may
operate to separate a color burst signal which is delivered ~¦
by line 212 to color burst processor 202 from a video signal
which is delivered by line 214 to video processor 204.
Color burst processor 202 essentiall~ reconstructs the color
I burst signal of the composite video received by diplexer
200, for example, by phase-locking a stable 3.58 mhz oscillator
to the incoming color burst signal. Video processor 204
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may, for example, control the gain and bandwidth of the
video signal. It may also extend low or high frequency
components, or cut-off unwanted port~ons of the ~ideo signal
, to give control over the formation a~d shaping of the video
I signal.
The video signal on line 214 from diplexer 200 is also
communicated to synch detector 206 which, as is well-known
, in the art, separates horizontal and vertical synch information
,I from the composite video signal introduced to diplexer 200.
The output of synch detector 206 is coupled to synch processor
208 which, like color burst processor 202, essentially
operates to reconstruct the synchronization signals by
phase-locking an internal oscillator to the incoming syn-
,, chronization signals. Signal processor 208 thereby recon- ~
15 I structs and shapes the synchronization signals of the ,
composite video signal.
In a standard processing amplifier, such as Grass
Valley Group Processing Amplifier, model 3240, the reconstru~t:e~l
color burst signals, video signals, and synchronization
signals are combined in a combiner 210 to form a reconstitute~l ¦
, composite video signal.
As explained above, the subscriber television system of
the present invention includes encoder means for randomly
Il inverting the polarity of a video signal. For the purposes
~5 of illustration and no-t limitation, a~tention is called to
analog switch 216, resistors 218, 220, 222, and 224, and
differential amplifier 226 in Fig. 5. The output of differential~
amplifier 226 is shown in Fig. 5 coupled to the video input
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of combiner 210. Feedback resistor 224 couples the output
! of amplifier 226 to the negative input. The negative input
of amplifier 226 is in turn coupled to incoming video from
video processor 204 through the series combination of first
~ pole 228 of analog switch 216 and resistor 218. The positive
input of differential amplifier 226 is coupled to the video
from video processor 204 through second pole 230 of analog
switch 216. First pole 228 of analog switch 216 is closed
:. upon receipt of a Q gating signal on line 120 from timing
-. network 116 whereas second pole 230 is closed upon receipt
. of a Q gating signal over line 120 from timing network 116.
In operation of processing amplifier 104 as illustrated
in Fig. 5, a Q gating signal from timing network 116 over
, line 120 closes second pole 230 of analog switch 216 and
l allows the video signal from video processor 204 to be
i transferred uninverted through differential amplifier 226 to
combiner 210.` ~ccordingly, a normal reconstituted composite
video signal is generated by processing amplifier 104 when a
Q gating signal appears on line 120. However, when a Q ¦
gating signal appears on line 120 second pole 230 is opened
and first pole 228 is closed communicating the video signal
from video processor 204 to the nega~ive input of differentia].
amplifier 226 and thereby causing inversion of the video .
signal resulting in a reconstituted composition video signal
~5 with an inverted video portion.
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It should be noted that since the reconstituted synchroni~atio~
components of the video signal are inserted into the composite
video signal by operation of synch d~tector 206 and synch
,I processor 208, the inversion of the video s.ignal from line
l 204 before introduction to combiner 210 has no effect on the
i polarity of the synchronization signals. Accordingly, first
pole 228 of analog switch 216 may be closed at the beginning
of the last full trace line of a vertical interval and
, remain closed throughout the subsequent field un'cil-the
i beginning of the next vertical interval without in any way inveKting
, or otherwise affecting the shape of the synchronization
signals of the reconstituted composite video output from
processing amplifier 104. Thus, all tha-t is required to
! achieve a desired random inverting of the polarity of a
].5 , video signal introduced to process.ing amplifier 204 is a
.. ... .... ,
gating signal ~ on line 120 which begins at the beginning of
a selected trace line of a randomly selected vertical interva!. i~
and continues throughout the succeeding field until the
beginning of the neY~t vertical interval. ¦
It should of course be understood that random inverting
of the polarity of a video signal by inverting the polarity
of a trace line of randomly selected vertical intervals and
by inverting the trace lines of associated fields following
the randomly selected vertical intervals can be achieved in
a number of alternative manners consistent with the spirit
and scope of the present invention. For example, an inverter
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may be inserted in the composite video signal path and
triggered during a selected trace line of randomly selected
vertical intervals and triggered during the trace lines of
, associated fields following the rand~mly selected vertical
intervals. This method of inverting the polarity of the
video signal, however, requires a gating signal which
disables the inverter during horizontal synchronization
signals which is not required in the processing amplifier
! 104 illustrated in Fig. 5.
10 j' As mentioned above, the video encoder means of the
subject invention further includes means or suppressing the
amplitude of randomly selected horizontal blanking pulses
during the fields of said video signal to, in conjunction
with the randomly inverted video signali form a scrambled
lS video signal. For purposes of illustration and not limitation,
attention is called to Fig. 6 wherein there is disclosed a .
block diagram of ~ transmitter exciter incorporating the
teachings of the present invention. ~¦
The example of exciter 106 shown in Fig. 6 comprises
the series combination of differential amplifier 300, video 11
gain control 302~ driver amplifier 304, differential gain !
driver 306, differential gain corre~tor; 308, differential
phase drive 310, and differential phase corrector 312.
j Differential gain driver 306 is limited during horizontal j -
synchronization pulses by operation of video clamp amplifier
314 which is in turn controlled by clamu pulse generator 316
and by differential phase corrector 312 over line 318. -¦
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Exciter 136 of Fig. 6 represents the basic design of
an RCA Exciter Model No. TTUE-4A. It is of course
intended that any comparable form of exciter may be
employed in connection with the teachings of the present
invention.
Any suitable point may be chosen along the video path
including differential amplifier 300, video gain control
302, driver amplifier 304, differential gain driver 306,
differential gain corrector 308, differential phase driver
310 and differential phase corrector 312 to suppress
horizontal blanking pulses in response to a gating signal
from timing network 116 of Fig~ 4. For example, in Fig. 6
a gating signal Q from line 122 of timing network 116 is
shown coupled to differential gain driver 306. Gating
signal Q, as will be explained below, appears during
randomly selected horizontal blanking pulses and operates
to alter the bias of differential gain driver 306 by a
fixed amount during such randomly selected horizontal
synchronization pulses. Furthermore, since video clamp
amplifier 314 attempts to clamp the horizontal
synchronization pulses at a fixed level, it is necessary
to also introduce gating signal Q to differential phase
corrector 312 during the randomly selected horizontal
blanking pulses to effectively prevent the operation of
video clamp amplifier 314 ~rom attempting to rebias the
suppressed horizontal blanking pulses to their normal
unbiased level.
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Fig. 7 is a schematic diagram of one example of a
portion of differential gain driver 306 employing the teachinys
l of the present invention. Specifica~ly, Fig. 7 illustrates
'I a simple differ~ntial amplifier comprising transistors 320
il and 322 with video input coupled to the base of transistor
320 and video output taken from the collector of transistor
320. The video output, as can be fully appreciated by one
I skilled in the art, reflects the biasing level applied to
'i the base of transistor 322. Accordingly, the video output
'! from transistor 320 can be selectively biased by the employment
of an analog switch 324 in series with variable resistor
326 connected between the base of transistor 322 and a B+
voltage supply. The value of resistor 326 is chosen such
, that upon closure of analog switch 324 by gating signal Q
the video output from transistor 320 is biased a fixed
amount from normal biasing levels. For example, with
reference to Fig. 3, the value of resistor 326 may be chosen
such that upon closure of analog switch 324 during a horizontal
blanking interval, the level of the horizontal blanking
pulse is reduced from approximately 75% amplitude to 25%
,1 amplitude.
'! An example of a portion of differential phase corrector
' 312 is illustrated in Fig. 8. Specifically, a buffer amplifier ;!
which forms the output of differential phase corrector 312
~5 , is illustrated in Fig~ 8 as comprising transistors 328 and j
, 330 series coupled between a B+ and a B- voltage supply by
I resistors 332 and 334. The base of transistor 330 is
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coupled to the B+ supply by diode 336 and resistor 332 and
is coupled to the B- supply by resistor 337. The base of
'I transistor 328 is coupled to receive the video input whereas ',
buffered video output is provided toltransmitter 108 of Fig.
S ,l 4 through resistor 338 coupled to the junction of the
~ emitter of transistor 328 and the collector of transistor
; 330. A controlled video feedback is provided to video clamp
, amplifier 314 of Fig. 6 through resistor 340 which is also
coupled to the junction of the emitter of transistor 328 and
o ! the collector of transistor ~30.
To prevent operation of video clamp amplifier 314 from
, clamping the video signal in differential gain driver 306 oE
Fig. 6 to the normal bias level of a horizontal synchronizatio
pulse during randomly selected suppressed horizontal blanking
lS i pulses, the video output from resistor 3~0 in Fig. 8 is
selectively coupled to the B- bias by the series combination
of analog switch 342 and variable resistor 344. Analog
; switch 342 is controlled by the ~ gating signal from line
122 of timing network 116 to close analog switch 342 during
each randomly selected horizontal blanking pulse to effertively
trick video clamp amplifier 314 into believing that a normal
horizontal blanking pulse is present~ In this manner, the
video output from resis~or 338 of differential phase corrector
~I 312 will pass randomly selected horizontal blanking pulses
,, of suppressed amplitude.
It should of course be understood that the suppression
~i of randomly selected horizontal blanking pulses can be
achieved in accordance with the teachings and spirit of the
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present invention in many alternative manners and that the
i~ specific circuits of Pigs. 6, 7 and 8 are setout to illustrate
a single example of how suppression of the amplitude of
I randomly selected horizontal hlanking pulses may be achieved.
S '¦ Fig. 9 provides a circuit diagram of one illustrative,
,,
but non-limiting example o timing network 116 of-Fig. 4.
In Fig. 9, a video signal is provided on line 118 from
processing amplifier 104 in Fig. 4. The video signal on
I line 118 is shown coupled to the video input of tuner and
master oscillator 400. Tuner and master oscillator 400 is
known to those skilled in the art having a standard TV tuner
, and an internal oscillator which i~ locked to horizontal
; synchronization signals, either the horizontal blanking
signals or the horizontal synchronization pulses. Specifically, t
lS master oscillator 400 may comprise an Ml Module of Zenith
Corporation which is presently employed in many commercially
available Zenith televisions. The Ml Module employs a 503 5
kHz master scan oscillator which is phased-locked to 32
times the horizontal rate of a video signal received by the
, tuner section. A master clock output of ~he oscillator 400
is coupled by line 402 to synch signal generator 404. When
master oscillator 400 is an Ml Module, line 402 is coupled
to terminal B4.
I Synch signal generator 404, as is well-known to those
I skilled in the art, provides horizontal drive pulses and
vertical blanking synchronization pulses in response to
' receipt of a master clock signal and a composite synchronization
signal. Synch signal generator 404 may, for example, comprise
a Zenith 221-103 chip which is also presently employed in
~0 commercially availa~le Zenith televisions.
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A composite synchronization signal,is provided to synch
signal generator 404 from line 406 coupled to master oscillator 1,
400. ~ composite synchronization si~nal merely comprises
I the horizontal and vertical synchronization signals from the
~I video signal on line 118. For example, a suitable composite
, synchronization signal can be received from terminal B2 of
a Zenith Ml Module.
i Horizontal drive pulses are generated by synch signal
'I generator 404 in response to the master clock signal on line
' 402 and the composite synchronization signal on line 406.
' Horizontal drlve pulses are defined with respect to timing
network 116 as a square wave locked to the horizontal
' synchronization rate which passes from negative to positive
Il at or slightly before the beginning of each horizontal
blanking pulse. Vertical blanking synchronization pulses
from synch signal generator 404 are defined with respect to 1'
' timing network 116 as a signal which is negative going half- i
'' way through the vertical synchronization pulse o~ a video '~
signal and remains negative going un~il termination of the
20 ' vertical interval. I
In Fig. 9, with horizontal synchronization generator '¦
404 representing a Zenith 221-103 chip, output terminal 11
of synch signal generator 404 is coupled to the clocked
input of flip-flop 408. In addition, the master clock
' signal on line 402 is coupled through inverter 410 to the
input of counter 412, while a reset signal is supplied to
' counter 412 from the horizontal drive pulses of output ¦
terminal 11 of synch signal generator 404 through inverter -
i
z
414. Upon tlle beginning of each horizontal drive pulse
counter 412 is enabled to provide an output upon receipt of
six master clock signals to reset flipflop 408. The Q
; output of flip-flop 408, namely flyback pulses, are coupled
from flipflop 408 by line 416 to the Bl terminal of master
oscillator 400. This interconnection of master oscillator
400, synch signal generator 404, counter 412 and flip-flip
408 assures that the flyback pulses on line 416 are centerecl
, on the horizontal synchronization signals of the video
! signal and have a duration of six of the 32 oscillations of
master oscillator 400 which occur for each video line.
Accordingly, the flyback pulses on line 416 begin just
slightly before the beginning of each horizontal blanking
~' pulse and terminate just slightly after the termination of
each horizontal blanking pulse. -!
The timing network illustrated in Fig. 9 fur~her includes
integrating network 418, differential amplifier 420, flip-
flops 422 and 424 and counter 426. Integrating network 418
is coupled to receive the composite synchronization signal ¦
on line 406 and is designed to provide as an ou~put vertical ¦
synchronization signal to pin 12 of synch signal generator
404 and to the negative input to comparator 420. The
I application of vextical synchronization pulses to pin 12 of
I synch signal generator 404 assures generation of vertical
! blanking synchronization pulses at pin 7 of generator 404 as
is known to those skilled in the art. In addition, the
application of vertical synchronization to the negative
input of comparator 420 with the positive input of comparator
420 coupled to a reference point will generate at the output
of comparator 420 a signal pulse with positive transition after
!
; - 25 -
,:
5Z
I I .
the trailing edge of the vertical synchronization pulse if a
vertical synchronization pulse is in fact present in the
composite video signal. ~; ¦
I The output of differential amplifier 420 is coupled to
the clock input of flip-flop 422 which has a data input
coupled to receive the vertical blanking synch pulsés from
pin 7 of synch signal generator 404. Since flip-flop 422 is
clocked by the positive transition signal from differential
Il amplifier 420 if a vertical synchronization pulse is present
il in the video signal, the output of the flip-flop 422 will go
,' high and stay high when the vertical blanking synch pulses
from generator 404 are properly phase-locked to the incoming
video signal. The Q output o flip-flop 422 is coupled to
' the data input of flip-flop 424 whereas the vertical blanking
synchronization pulses are coupled to the clock input of
flip-flop 424. The reset of flip-flop 424 is coupled to the
output of counter 426 which, in turn, has as an input the
inverted horizontal drive pulses from inverter 414 and has
a reset coupled to the Q output of flip-flop 424. Counter
~ I 426 is designed to provide a short end of field pulse at the
! start of each vertical interval. Since flip-flop 424 is
! clocked at the end of each vertical interval and is reset at
the end of each field, the Q output of flip-flop 424 generates
a vertical interval signal which is ~igh during the vertical j
1 interval and low during the fields between vertical intervals. ¦
The timing network of Fig. 9 further comprises counter
428, OR gate 429, and flip-flops 430 and 432. Counter 428
i is coupled to receive the horizontal drive pulses from synch ¦
.
i .1
- 26 -
,~ I
z
l~
signal generator 404 as an input and to receive the vertical
! blanking synch pulses from generator 404 as a reset signal.
,Counter 428 therefore begins countin~ half way through the I -
'I vertical synchronization pulse of a vertical interval and ! --
~l continues to count horizontal drive pulses until the beginning
of a chosen trace line of the vertical interval, preferably
, the last complete trace line of the vertical interval.
The output of counter 428 is coupled to the clock input
'I of flip-flop 432 whereas the data input of flip-flop 432 is ¦
l coupled to random signal generator 114. Random signal
generator 114 may, for example, co~prise two separate random
signal generators namely synch random signal generator 434
and video random signal geneator 436. In that case, the
, data input to flipflop 432 is coupled to video random 1;
I signal generator 436. The reset of flip-flop 432 is coupled
to the output of counter 426. Accordingly, flip-flop 432
, operates to provide a high output at the Q terminal during
,i the last line trace of randomly selected vertical intervals '
' and to continue a high Q output during the field which
follows the randomly selected vertical interval. -The output
of flip-flop 432 is coupled over line 120 to processing '
amplifier 104 of Fig. 4, and specificallv is coupled to ,
analog switch 216 of Piy. 5 as dascribed above. '!
~ Flip-flop 430 has a clock input,coupled to receive i
'5 flyback pulses from line 416 and a data input coupled to
synch random signal generator 434. OR gate 429 is coupled to
, receive at a first input terminal the inverse of flyback pulsas ,¦
"
. .
,
.
.' '
`,1
- 27 ~
~,7 !
52
on line 416 from the Q output of flip-flop 408. OR gate
429 is also coupled to receive at a second input the vertical
interval signals from the Q output o~ flip-flop i24. The
Il output of OR gate 429 is coupled to the reset terminal of
1ll flip-flop 430. Flip-flop 430 accordingly operates to
I provide a high output or Q gating signal at line 118 during
randomly selected horizontal synchronization pulses since,
when synch random signal generator 434 is high at the
beginning of a flyback pulse on line 416, a high output is
generated at the Q output of flip-flop 430 until flip-flop
430 is reset slightly after the end of the horizontal blanking
i signal by the Q output of flip-flop 408 through OR gate 429.
,1 In addition, flip-flop 430 is disabled during vertical
l intervals by the operation o~ the vertical interval signal
' of flip-flop 424 applied to the second input of OR ga~e 429 1 -
whose output in turn drives the reset terminal of flip-flop
430.
;1 In summary, the output on lines 1~0 from flip-~lop 432
.~ .
,l in Fig. 9 is coupled to processing amplifier 401 of Fig. 4 ! .
zo ,l and provides inversion of the polarity o~ a trace line of
, randomly selected vertical intervals-and inversion of trace ,
lines of the field following the randomly salected vertical
intervals. The output on line 118 of flip-flop 430 in Fig. 9
j is coupled to transmitter exciter 106 in Fig. 4 and provides
~5 ,I suppression of the amplitude of randomly selected hori~ontal
blanking pulses during fields of the video signals. The
combination of the random inversion of the polarity of the
'j video signal and the suppression of randomly selected hori20ntal
blanking pulses provides a scrambled video signal to transmitter ¦
108 of Fig. 4 which signal is unintelligible at a normal
l! televisionreceiver
, -28 - I
. , .
In accordance with the subscriber television system of
the present invention, the system further comprises a decoder
means responsive to the polarity of ~he trace line of the
,I vertical intervals for detecti~ng the polarity of the trace
~ lines of said associated fields, the detector means being
, further responsive to the amplitude of the scrambled video
signal during selected time intervals for detecting ths
suppression of the randomly selected horizontal blanking
! pulses, and decoder means responsive to the detector means
for unscrambling the scrambled video signal.
As applicable to the speciic waveforms illustrated in
Fiqs. 2b and 3, a specific embodiment of the present invention
may, for example, include a decoder which is responsive to
I the polarity of trace line 60 of each vertical interval 62
for detecting the polarity of the trace lines 66 of associated
I fields 64. For the speciic illustrative waveforms shown ir,
- Pigs. 2b and 3, an example of a detector of the present
! invention is further responsive to the amplitude of the
scrambled video signal during time period 70 of Fig. 3 which
;~ is the time period of horizontal blanking pulses, for detectiog
the amplitude of the horizontal blanking pulses. Preferably
the detection occurs during the period of front porch 38 to
! detect the suppression of randomly selected horizonkal
, blanking pulses. In this specific example, a decoder is
~5 I also provided which is responsive to detection of an inver ed
trace line 60 of Fig. 2b and responsive to detection of a
suppressed horizontal blanking pulse during front porch 38
!' as shown in Fig. 3 for unscrambling the scrambled video
, signal.
il .,
,, ~
,1 .1
1 !
More specifically, a television decoder in accordance
with the present invention preferably comprises a detector
~enerating a video signal from the received composite video
signal. In the specific example of a decoder illustrated in
Fig. 10, antenna 500, UHF tuner 502, IF amplifier 504, tuning
and automatic frequency control 506, automatic gain control
508, and vide~ and audio detector 510 provide a video signal
on line 512 from a received composite video signal at antenna
500. More specifically, as is well-known to those skilled in
the art, UHF tuner 502 may, for example, convert a received
composite video signal to a standard 45.75 MHz television
intermediate frequency whereupon it is amplified and band-
limited by intermediate frequency amp~ifier 504. ~uning and
automatic frequency control 506 is coupled from intermediate
frequency amplifier 504 to UHF tuner 502 to set the tuner at
a specific received frequency which is preferably set at the
manufacturing facilities and not accessible to the viewing
public. The signal from intermediate amplifier 504 is then
demodulated to composite base band video by video and audio
detector 510 again a~ is well-known to those skilled in the
art. Video and audio detector 510 generates a standard
automatic gain control signal to automatic gain control 508
in order to keep the operation of UHF tu~er 502 and the
operation of intermediate frequency amplifier 50~ at the
proper level.
In accordance with the present invention, the decoder
preferably further comprises a video modulator, the modulator
having a first input terminal for the video signal and a
- 30 -
52
~ second input terminal for a referance level signal, the
modulator operable to generate a modulated television signal
responsive to the difference between~the video and reference
! level signals at the first and second terminals.
5 ! In the specific example illustrated in Fig. 10 a video
and audio modulator 514 is shown having a first input terminal
516 and a second input terminal 518. V.ideo and audio modula~or
. 514 may, for example, comprise video modulator chip number
LM 1889N which is normally currentl.y found employed in video
games to impress a video signal on a radio frequency carrier.
The output of modulator 514 is coupled to television receive~
532 and comprises a video signal proportional to the differelltial
! between the signal appearing at first terminal 516 and
' second terminal 518.
15 . In accordance with the present invention, the decoder !
preferably further comprises biasing means for establishin~
first, second, and third differential signals between the .
first and second terminals upon receipt of first, second,
and third control signals, respectively, the difference
,, signals comprising the difference between the video and
I reference level signals, the first d~fferential signal .¦-
, biasing the first and second terminals sufficiently for the
modulator to generate a normal modulated signal from the i
video signal, the second differential signal biasing the
'5 l first and second terminals the same as the first differential
signal but the video and reerence level signals interchanged .
at the input terminals, whereby said modulator generates an
- 31 -
5;~
,
inverted modulated television signal, and the third differential
,I signal biasing said first and second terminals sufficiently
for the modulator to generate a modu~ated television signal
l at a fixed level from the normal mod~lated signal.
S ! In the specific example of a decoder illustrated in
Fig. lO, synch and inversion control 520 is shown having one
output 517 coupled to first input terminal 516 of video and
I audio modulator 514 and another output 519 coupled to second
¦ input terminal 518 of modulator 514. As will be explained
, in greater detail below, synch and inversion control 520
operates in response to first, second, and third internal control~
signals to provide differential signals between first and
. second terminals 516 and 518 of video and audio modulator
li 514. 1;
Further in accordance with the present invention the
decoder also comprises first means for detecting the polarity
of a selected trace line of vertical intervals of the video
signal, and second means for detecting the amplitude of the .
video signal during the initial portion of horizontal
. blanking pulses during the fields of the video signal. In
the specific example of the decoder illustrated in Fig. lO, ¦
a video comparator 522 continuously detects the polarity of
! the video signal appearing on line 512 and synch comparator
524 continuously detects the amplitude of the video signal
I appearing on line 512.
,,
:, I
I ~ 32 ~
~7 i!
~, !
5~ ,
The detector illustrated in Fig. 10 further comprises a
~i timing network 526, a synch gate 528, and a video gate 530.
Timing network 526 received an input~,signal from video and
audio detector 510 and generates gating signals to synch i-
,I gake 528 and video gate 530 Video gate 530 is coupled
~etween video comparator 522 and synch and inversion control
520 whereas synch gate 528 is coupled between synch comparatox
524 and synch and inversion control 520. Timing network 526
Il operates, as will be explained below, to pass the output of
video comparator 522 through video gate 530 during a selected
trace line of vertical intervals of a video signal. As will
also be explained below, timing network 526 operates to pass
the output of synch comparator 524 through synch gate 528 ¦
,~ during an initial portion of horizontal blanking pu~ses
during the fields of the video signal. ¦
Further in accordance with the present invention, the -¦
decoder includes control means for normally coupling the
first control signal to the biasing means, the control means
being responsive to detection by the first means of the
! selected trace line of a vertical interval havi~g an inverted ,
polarity to couple the second control signal to the biasing
means during the line txaces of an associake field following
the vertical interval, and the control means being responsive
to detection by the second means of the initial portion of
horizontal blanking pulses having an amplitude below a
, predetermined level to couple the ~hird control signal to
the biasing means during the portion of the horizontal
blanking pulse following the initial portion.
'i i
- 33 -
,,,.
,a~5;~ '
- - l
`; As will be explained below with respect to the specific
I example of the decoder generally illustrated in Fig. 10,
.I synch and inversion control 520 oper~tes to normally generate
j a first control signal which operates to establish a first
i differential signal biasing first and second terminals 516
;j and 518 of video and audio modula~or 514 sufficien~ly for
modulator 514 to generate a normal modulated television
; signal from the video signal on line 512. In addition, it
will be explained below how synch and inversion control 520
; generates a second control signal upon the detection by
video comparator 522, in conjunction with video gate 530 and
timing network 526, of a selected trace line of a vertical
interval having an inverted polarity and in response to the
! second control signal generates a second differential signal
biasing first and second terminals 516 and 518 the same as j.
upon generation of the first control signal but with the
' video and reference level signals interchanged at irlput .
! terminals 516 and 518, whereby modulator 514 generates an
; inverted modulated television signal to television receiver .
,l 532. .
Il Finally, as will be explained beLow, synch and inversion . .
i control 520 is responsive to detection by synch comparator
~¦ 524 and synch gate 528 of an initial portior~ of a horizontal
' blanking pulse having an amplitude below a predetermined
25 '~ level to generate a third control signal which results in.
, coupling of a third differential signal to first and second
, terminals 516 and 518 sufficie~tly for modulator 514 to
I generate a modulated television signal at a fixed video
~ level above the normal video signal to thereby effectively
1, re-establish the correct level of the suppressed horizontal
blanking pulses for the period following the initial period.
34 -
s~ :
It is also preferred that the decoder of the present
,~ invention include means for detecting a received audio
,I subcarrier signal, means for demodul~ting said subcarrier
Il signal to generate an audio signal i~ response to detecting
'I said audio subcarrier signal, means for coupling said audio
!I signal to said second input terminal of said modulator, and
, said modulator operable to generate a modulated television
signal with audio. ~ -
,l In the speci~ic example of the decoder illustrated in
Fig. 10, audio ou-tput from video and audio detector S10 is
,l provided, as is wellknown to those skilled in the art, on
'I line 534. The audio on line 534 is coupled to audio switch
I 536, audio carrier decoder 538, and audio carrier detector
Il 540. Audio carrier detector 540 may, for example, comprise
15 1 a Decod~r ~umber LM567CN, tuned by adjustment well-~nown to !
those skilled in the art to a 39 kEIz audio subcarrier signal.
, ~udio carrier detector 540 operates to generate a control
signal to audio switch 536 upon detection of the audio ¦
subcarrier. Audio carrier decoder 53.8 operates to demodulate ¦
the audio subcarrier to provide demodulated audio to audio ¦
switch 536 which is passed through audio switch 536 upon ¦
operation of detector 540. However, upon failure of detector
5~0 to indicate the presence of an audio subcarrier, the
~ audio signal on line 534 is passed directly thxough audio
switch 536. The output o~ audio switch 536 is coupled to
, second input 518 of video and audio modulator 514.
! In accordance with the present invention, the decoder
,I further comprises means responsive to data signals appearing
., ',
,
Il - 35 ~ I
y ,1 . `I
, ,~,
5Z
!
i
,l in the received composite video signal during selected trace
, lines of the vertical intervals to selectively enable or
! disable the modulator. The specific~;example of the decoder
,1 illustrated in Fig. 10 includes a data gate 542 shift register
'I 544, address comparator 546, storage 548, and terminal
on/off memory 550. The input of data gate 542 is coupled to
the output of video comparator 522 whereas the output of
i data gate 542 is coupled to shift register 544. Data gate
Il 542 is opened by operation of timing network 526 to pass the 1-
,, output from video comparator 522 during selected trace lines
" of vertical intervals of the video signal appearing on li~le
512. Data on these selected trace lines is sequentially
' loaded into shift register 544. As was explained above, the
I data may preferably take the form of 24 bits of digital
,j information. The first two bits are frame bits, foll,o,wed by,,, ,,,,
j 19 binary coded address bits. The next two bits are data
, bits which are used to enable or disable the decoder. The
; last bit is a parity bit wh~ch relates to odd parity of the
19 address bits only, not the frame ~its or the data bits.
, Address data is preset into the decoder storage 548 and the
preset address is compared against the received address in
shift register 544 by address comparator 546. When the
I address preset into s~orage 548 matches the address which is
l! loaded into shift register 544, the two data bits loaded
into-shift register 544 are examined by terminal on/off
~, memory 550. If both data bits are low, the output of terminal
!
`!
j - 36 _ I
,~,, ,1 . 1
. . - I ~
52
.
on/off memory 550 enables video and audio modulator 514.
However, if both data bits are high, the output of terminal
on/off memory 550 disables video and~audio modulator 514.
Il No change is made in the previous setting of terminal on/off
~! memory for any other combination.
The enable or disable signal from terminal on/off
memory 550 is preferably accomplished by a pulse of approxima~ly
1 millisecond duration to either set or reset terminals of a
,j magnetic latching reed relay used in memory 550 to switch
1 power to video and audio modulator 514. If the memory is
commanded to the reset or disable state, voltage is removed
from modulator 514 such tha~ no signals, video or sound,
scrambled or unscrambled, are delivered to television recei~e~
532. Since the relay is magnetically latching in either
mode, as i5 the case for example wlth latching ~eed Relay
model number 961A12YlL manufactured by the C. PO Clare
, Company, disconnecting power to tlle decoder in general, for
either short or long periods, will not affect the setting of
the relay and therefore will not afect the enable or disable li
setting of memory 55C. ¦
In operational practice, it is anticipated that all
decoders will initially be se~ in the enable state before
installation and that a disabling signal will be sent to the !
i! appropriate decoders on a rotationally continuing basis at
25 ,¦ least during the transmission o~ scrambled programs. Since ¦
only the power to the modulator 514 is affected by memory
I 550, address comparator 546 i8 operable at all times when ¦
!~ I
. 'i
_ 37 _
5~ '
; there is power to the decoder. Thus, any unauthorized
decoder attempting to receive scrambled programs can be
disabled. Enabling of a decoder may~?occur any time thereafter,
I but typically will be done prior to scrambled program
5 : ! transmission.
In operation of the decoder illustrated in Fig. 10,
audio and video signals appear on lines 534 and 512 from
. video and audio detector 510 upon xeceipt of a composite
! television signal at antenna 500. If the audio signal
!! contains an audio subcarrier, audio subcarrier detector 540
operates to switch audio switch 536 such that the detected
-- audio from decoder 538 is passed through audio switch 536 to
second input ter~inal 518 of modulator 514. However, if an
audio subcarrier is not detected, audio switch 536 operates
lS . to pass audio directly from video and audio detector 510
onto second input 518 of modulator 514.
The video signal on line 512 is coupled to first input
516 of video and audio modulator 514 through synch and inversion ¦
, control 520 for normal operation. As ~ill be explained
below, synch and inversion control 520 normally sets a :i
reference differential between terminals 516 and 518 such . .
that modulator 514 generates a normal modulated television
signal to receiver 532.
Video comparator 522 also receives video signal from
line 512 and compares the magnitude of that video signal
l against the magnitude of an uninverted black signal. The i
! output of video comparator 522 is gated by video gate 530 to
:!
!
, '
,i i
~ -- 3 8
,, i,
5~ j
,,
pass to synch and inversion control 520 only during a selected
trace line of vertical intervals. For example, the output
! f video comparator 522 may be passe~ to synch and inversion
'¦ control 520 only during the last complete trace line of a
~, vertical interval. If the magnitude of the video during
' such last complete trace line indicates an uninverted black
level, synch and inversion control 520 will continue to
maintain normal operation of modulator 514. However, if
video comparator 522 detects that the last complete trace
o l! line of a vertical interval is below the uninverted black
, level, synch and inversion control 520 will operate to bias
, inputs 516 and 518 and interchange the video signal and
reference level inputs such that the video signal appearing
! on line 512 is inverted by video and audio modulator 514
during the line traces of the subsequent field. In this ;
manner, a randomly inverted video field is restored to
normal withoùt the necessity of employing control codes,
keying signals, or other encoding signals independent from
l the actual inversion of the video si~nal. In the decoder of
Fig. 10 it is ~he inv~rsion of the video signal itself
,' wi~hout additional encoding sig~als which is detected and
utilized to reinvert randomly inverted selected fields.
Synch comparator 524 operates to continuously monitor
!, the level of the video signal to determine when that level i
;! falls below the level of a standard hori70ntal blanking
pulse. Synch gate 520 is operated to transmit the output of I`
! synch comparator 524 to synch and inversion control 520 1-
i I .
,1 ;.
'I - 3
'!
"
.. . .
.~ i
,I during the initial or front porch period of each horizontal
blanking pulse during a field. Upon detection of a subnormal
¦ initial period or front porch portio~ of a horizontal blanking
l¦ pulse, synch and inversion control 520 immediately operates
,I to rebias first and second inputs 516 and 518 to a level
which assures that the remaining portion of the horizontal
I blanking pulse will be restored to normal level. Furthermore,
; a signal from synch and inversion control 520 is transmitted
, upon detection of a suppressed horizontal blanking pulse to
, automatic gain con~rol 508 to rebias the automatic gain
control in a manner which a-~oids adverse effect on the
; automatic gain control by the remaining portion of the
suppressed horizontal blanking pulse. It is this rebiasing
of automatic gain control 508 which allows timing network
526 to continually and accurately determine the expected
location of the next horizontal blanking pulse.
Turning now to Fig. 11 there is disclosed illustrative
but non-limiting examples of terminal on~off memory 550, ;
I video and audio modulator 514, and synch and inversion
'0 ' control 520. ¦
f In Fig. 11, an example of vide~ and audio modulator 514
is shown to comprise a video modulator chip 600. As was
explained above, video modulation chips 600 prefexably
' comprises semiconductor chip LM1889N which is typically
~I presently found in video games. Chip 600 has a first input
, 602 at pin 12 and a second input terminal 604 at pin 13.
,1, `. .
'' i
., .i,
- 40 -
""~
~: ,'
First terminal 602 is coupled to a tap point of variable
resistor 603 which is coupled between bias terminal 618 of memory~
550 and ground. Second terminal 604~;is coupled to receive
j audio through a circuit comprising resistors 606, 608, 610,
ll and 611, inductor 612, capacitors 614 and 615, and varactor
diode 616. Specifically, re.sistors 606 and 608 are coupled
between terminal 618 of memory 550 and ground. The anode of
diode 616 is coupled to the junction of resistors 606 and
! 608 while inductor 612 is coupled between bias terminal 618 1 -
o ~! and the cathode of diode 616. Both capacitor 614 and resistor
610 are coupled in parallel with inductor 616. The cathode
of diode 616 is also coupled through the series combination of
capacitor 615 and resistor 611 to input 604 o chip 600.
The circuit comprisiny resistors 606, 608, and 610, inductor
' 612 capacitor 614, and varactor diode 616 operates to match
audio which appears at the junction of resistors 606 and 608 ¦-
to a standard television requency of modulation for receipt
' at input terminal 604 of chip 6~0.
i The output of chip 600 is coupled through a surface
acoustic wave filter 620 which removes lower si-le bands of
modulation from chip 600 as will be readily apparent to '¦
those skilled in the art. Filter 620 may, for example,
co~prise a monolithic crystal filter number CI155B from
Crystal Téchnology, Inc. The output of filter 620 is
Z5 ,I transmitted to a standard television receiver.
Terminal on/off memory 550 is shown in Fig. 11 as
comprising transistors 622 and 624, voltage regulator 626,
;1 and a latching relay 628 which comprises coils 630 and 632
,i 1
" i
- 41 -
"
!
and switch 634. Voltage regulator 626 a~.ld switch 634 are
coupled in series between a source of n . c . voltage a!.ld
terminal 618. Coil 630 is coupled in series with the emitter-
i coll~sctor path of transistor 622 between the D~C. source and
I ground while coj.l 6~2 and the emitter-collector path o~
trans.istor 624 are coup ed n ssri.es bet~een the D.C. source
and ground. The base of transis_or 622 is coupled ~G receive
a disable signal from addresr. comparat~_ 546 whereas the
; base o r transistor 6~.4 is coupled to receive an ena-a~e
signal from address comparator 546 of Fig. 10. Thus, upon
receip,- t~f d disable sign21 transistor 622 temporarily
conducts causing ol~ening of switch 6:~4 and removal of any
power to termina~. 618. On the other hand receipt Gf an
, enable si~nal at the base of transistor 624 close~ switch.
1 63~ and provides for power at terminal 518 through vo:tage
regulator 626. ............................................. .. ....
Synch and inversion control 520 is illus~rated in Fig.
11 as comprising an analog switch 636 having normally open
~irst, second, third, and fourth internal switches 6~8, 640, ¦:
' 642 ~nd 644.
Switch 638 is coupled in series with resistor 645 between
a pick-off point of resistor 646 and second input terminal
604 of chip 600. Switch 640 is coupled bet~een video line
512 and first input terminal 602 of çhip 600. Switch 642 is
'5 I, coupled in series with resistor 645 between video line 512 and
,~ input terminal 604. One side o~ switch 644 is coupled to
ground through variable resistor 656 while the other side of
;, switch 644 is coupled to a bias point in automatic gate
,, control 508. Resistors 646 and 649 are series-coupled
.I between texminal 618 of memory 550 and ground and the junction .:
I of resistors 646 an~ 649 is coupled through resistor 64S ~o
¦ second in~ut terminal 604.
, - 42 -
;
,; '
The operation of switch 640 is governed by receipt of a
first control signal on line 650, the operation of switch
642 is governed by a second control ~ignal on line 652, and
, the operation of switches 638 and 644 is governed by a thirc~
'~ control signal appearing on line 654. Analog switch 636
may, for example, compri~e semiconductor chip number 4066B.
Upon receipt o~ a first control signal on line 650,
;I switch 640 is closed providing input 602 of video modulation
,. chip 600 with a video signal from line 512 while input 604 ' ¦
,~ is provided with a bias determined by the voltage drop
across resistor 649. This bias is selected to result in a
normal modulated television signal generated by chip 600
responsive to the video signal appearing at terminal 602 and
, the audio signal appearing at 604.
However, upon receipt of a second control ~ignal on
line 652 which closes switch 642, switch 640 is opened and
the video from line SR is applied to second terminal 604 of
chip 600 and terminal 602 is provided a bias determined by .¦.
the setting of the pick-off point of.resistor 603 which
creates a reference differential between input 602 and 604
il which is equal in magnitude and opposite in polarity to the
; differential created upon receipt of the first control
signal on line 650. This new bias and change of video input
' on pins 602 and 604 results in a modulated television
j signal at the output of chip 600 in which the video portion
is inverted.
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, Vpon receipt of a third control signal on line 654,
, switches 638 and 644 are closed, switch 642 is opened and
jj switch 640 is closed. Closure of sw~tch 638 causes a bias
, i
Il to appear at pin 604 equal to the voltage drop across a
i portion of resistor 646 and across the whole of resistor 649.
This bias results in an increase in the level of the video
portion of the modulated television signal generated by chip
600 which increase is designed by setting a variable resisto~:
'i 649 to precisely offset the amount of suppression introduced
by the encoder to randomly selected horizontal blanking
pulses. In addition, upon xeceipt of the third control
ignal on line 654, closure of switch 644 generates a bias
signal from resistor 656 to automatic gain control 508.
Thus, if the third control signal is received on line 654
during the initial or front porch portion of a suppressed
horizontal synchronization pulse, the signal to automatic
gain control 508 from resistor 656 will assure that the
! automatic gain control will rebias the suppressed horizontal
blanking pulse to a normal blanking pulse level thereby
'0 allowing for normal operation of the automatic gain control.
Generation of first, second and third control signals
on lines 650, 652 and 654 is achieved by operation of invert.er
! 660, NAND Gate 664, and NOR gates 666, 668, 672, and 674. Invert~idr
i! 660 is coupled to receive horizontal flyback pulses from
'5 1I timing network 526 of Fig. l0, one input of NOR gate 666 is
designed to receive a synch compare signal from synch gate
528 of Fig. l0, one input of NAND gate 664 is designed to
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~eceive a vertical interval signal from timing network 526
I of Fig. 10, and the other input of NAND 664 is designed to
Il receive a video compare signal from yideo gate 530 of Fig.
! lo The output of inverter 660 is coupled to a second input
of NOR gate 666, and to ~oth inputs of NOR gate 668. The
output of N~ND gate 664 is coupled to the first input of NOR
' gate 6720 The output of NOR gate 668 is coupled to a secon~
input of NOR gate 672. The output of NOR gate 672 is coupled
! to both inputs of NOR gate 674.
1' As will be explained in detail below, the horizontal
flyback pulses delivered to the input of inverter 660 go
positive slightly after the initiation of each horizontal
! blanking pulse of a field and remain positive for the
l duration of each horizontal blanking pulse. The vertical ~ -
lS interval signal appearing at the first input of NAND gate
664 is low during each vertical interval. In addition, a I -
synch compare signal is defined as a signal which begins
- during the inital portion or ~ront porch portion of each
suppressed horizontal blanking pulse and conti~ues for the
~ duration of each such pulse. ~ video compare si~nal is
¦ defined as a signal which goes positive during a selected
trace line of each vertical interval wherein the trace line
is inverted in polarity and r~mains positive for the duration
of the succeeding field.
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.
In accordance with standard logic, a first control
signal from the output of NOR gate 674 i5 normally present
¦ on line 650. A second control signal from the output of
! NOR gate 672 appears during trace lines of a field following
¦ a vertical interval in which the selected line trace exhibits
a reverse polarity. A third control signal appears from the
output of NOR gate 666 following the initial or front porch
period of each suppressed horizontal synchroni~atio~ pulse
,, and continues for the duration of each such pulse. Synch
lll and inversion control 520 therefore operates to reestablish
; the correct polarity of randomly inverted video signals and
the correct biasing of randomly selected suppressed horizon-tal
blanking pulses and achieves this end without the employment
! of any control codes, keying signals, or encoding signals
!~ independent of the actual scrambled video signal itself.
Turning to FigO 12 there is disclosed a circuit diagram
. of one example of synch comparator 524, video comparator
522, synch gate 528, and video yate 530. In Fig. 12, synch
comparator 524 is shown to comprise resistors 700 and 702
' and differential amplifier 704. Resistors 700 a~d 702 are
~I series-connected between a po~itive supply of voltage and
ground and their junction point is coupled to the positive i
input of differential amplifier 704. The negative input of
differential amplifier 704 is provided with a video signal
1i from line 512 of Yig. lOo The bias provided by resistor 700
and 702 is preferably set just above the black level, typically
at approximately 3 l/2 volts. Accordingly, when a suppressed
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horizontal blanking pulse appears at the negative terminal
of amplifier 704, a negative signal is generated at the
output whereas, if a normal pedestal~is received, a positive
1, signal is generated at the output of the amplifer 704.
!I The output of amplifier 704 is coupled to synch gate
528 which in Fig. 12 is illustrated as comprising a flip-
. flop 706. Specifically, the output of amplifier 704 is
! coupled to the data input of flip-flop 706. The clock input
~ of flip-flop 706 is coupled to receive horizontal flybacX
~ pulses from timing network 526 and the set terminal of flip- j
,' flop 706 is coupled to receive a vertical interval signal
,li from timing network 526. If a negative output is received
i from amplifier 704 at the beginning of a horizontal flyback
,; pulse indicating existence of a suppressed amplitude horizont~l :
blanking pulse, a low synch compare signal is generated at
the Q output of 1ip-flop 706. However, in the event of a .
' normal amplitude horizontal blanking pulse ~eing received at .
the beginning of a horizontal flyback pulse and at all times .
, during the vertical interval, the Q ~utput of flip-~lop 706
;' remains high.
! Video comparator 522 is illustrated in Fig. 12 as
comprising resistors 708 and 710 and diferential amplifier
712. Resistors 708 and 710 are coupled in series between a
I positive source of D.C. voltage and ground. The junction of
'5 ~ resistors 708 and 71Q is coupled to the positive input of .
differential amplifier 712. The negatlve input of amplifier
i 712 is coupled to receive video from line 512 of Fig. 10.
. The bias provided by resistors 708 and 710 is preferably set
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at approximately half way between black and white level in a
video signal or approximately 37 1/2% amplitude. Typically,
! this level may be in the order of 5 ~/2 volts. When the
I video is black or approximately 3 volts, the comparison is
5 1I positive and a positive output is generated from amplifier
712. However, when the video is white the comparison in
negative and a negative output is generated by amplifier
702.
I The output of amplifer 712 is coupled to video gate 530
, which, in Fig. 12, is illustratively shown to comprise
inverter 714, counter 718, AND gate 720, and flip-flop 722.
, The output of amplifier 712 is coupled through inverter 714
jl to one input of AND gate 720. Horizontal drive pulses are
Il defined as with respect to timing network 526 a s~uare wave
! locked to the horizontal synch rate slightly after the
beginning of each horizontal blanking pulse. These horizontal
drive pulses are coupled from timing network 526 to the
input of counter 718. The reset of counter 718 is coupled
' to a vertical blanking synch signal ~rom timing network 526
20 !i which is defined as a signal which goes negative half-way ¦
¦¦ through a vertical synchronization pulse and goes positive
at the termination of the vertical interval. Counter 718 is
therefore reset half way through each vertical synchronization
' pulse and is designed to count horiz~ntal drive pulses until
! a selected trace line of thP vertical interval is reached.
Preferably t~le selected trace line i5 the last complete
trace line of each vertical interval. ¦
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I The output of counter 718 is coupled to a second input
of AND gate 720. The output of AND gate 720 is coupled to
the clock terminal of flip-flip 722.l~ AND gate 720 accordingly
il provides to the clock terminal of flip-flop 722 a positive
I going signal during the selected trace line of a vertical
interval whenever a selected trace line is inverted.
The data terminal of flip-flip 722 is coupled to a
, constant positive signal source. The reset of flip-flop
¦ 722 is coupled to receive end of field pulses from timing
, network 526 which end of field pulses are designed to occur
at the end of each field of the video signal. Since counter
718 can provide a positive input to the ~ND gate 720 only
; during the selected line trace of each vertical interval,
l flip-flop 722 provides a positive going video compare signal
at output terminal Q only when the selected video line trace
of a vertical interval is inverted. The video compare
signal, as a result of end of field pulses supplied to the
; reset terminal of flip-flop 722, continues throughout the
subsequent field. I
~0 In Fig. 13 there is illustrated a circuit diagram of
one example of timing network 526. This example of timing
network 526 is essentially the same as the example of timing
network 116 illustrated in Fig. 9 above. Specifically,
, timing network 526, as illustrated in Fig. 13, is provided !:
with a video signal on line 800 from antenna 802. The video :!
signal on line 800 is shown coupled to tuner and master
oscillator 804. Tuner and master oscillator 804 is known to
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those skilled in the art as having a standard TV tuner and
an internal oscillator which is locked to the horizontal
synchronization signals of the receiyed video signal.
! Specifically, master oscillator 804 may comprise a Ml Module
I of Zenith Corporation which, as was explained above, employs
a 503.5 kHz master scan oscillator which is phased-locked to
32 times the horizontal rate of a video signal received by a
tuner section. The output of master scan oscillator 804
' includes an audio signal suitable for use on line 534 of
' Fig. 10 and a video signal suitable for use on line 512 of
Fig. 10 as is well-known to those skilled in the art. A
master clock output of oscillator 804 is coupled by line 806
to synch signal generator 808. When master oscillator 804
~, is an Ml Module, line 806 is coupled to terminal B4.
! Synch signal generator 808, as is well-known to those
; skilled in the art, provides horizontal drive pulses and
verticle blanking synchronization pulses in response to
receipt of a master clock signal and a composition synchronization
I signal. Synch signal generator 804 may, as was explained
' above, comprise a Zenith 221-103 chip. A composite synchronizati~n
signal is provided to synch signal generator 808 fxom line 810
coupled to master oscillator 804. A composition synchronization i~
signal as explained above merely comprises the horizontal
,j . 1
~ and vertical synchronization signals from the video signal
; on line 800. For example, a suitable composite synchroni~ation ;
signal can be received from terminal B2 of a Zenith Ml
Module as would be perfectly apparent to one skilled in this
art.
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Il The timing network illustrated in Fig. 13 further -
comprises an inverter 812 which corresponds to inv~rter 410
of Fig. 9, a counter 814 which corre~ponds to counter 412 of
,I Fig. 9, a flip-flop 816 which corresponds to ~lip-flop 408
' of Fig. 9, an inverter 818 which corresponds to inverter ~14
,
of Fig. 9, an intesrating network 820 which corresponds to
integrating network 418 of Fig. 9, a differential amplifier
822 which corresponds to differential amplifier 420 of Fig.
,' 9, flip-flops 824 and 826 which correspond to flip-1Ops 422
, and 424 of Fig. 9, and a counter 828 which corresponds to
counter 426 of Fig. 9.
' Each of the above-identified elements of the timing
network of Fig. 13 is connected in the same manner as the
corresponding element of the timing network in Fig. 9. The
primary difference between these elements resides in the
fact that counter 814 of Fig. 13 is reset to provide an
output upon receipt of only five master clock signals to
reset flip-flop 816 as opposed to the six master clock ¦
signals employed in counter 412 to reset flip-flop 408. As
' a result of employing only five maste~ clock signals, the Q
output of flip-flop 816, namely flyback pulsec~ is centered '
on horizontal synchronization signals of the video signal
; and has a duration of only five of the 32 oscillations of I -
master oscillator 804 which occur for each video line.
~! Accordingly, the flyback pulses from flip-flop 816 begin
just slightly after the beginning of each horizontal blanking
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pulse and terminate slightly before the termination of each
¦ horizontal blan~ing pulse. Thus, the horizontal flyback
, pulses from flip-flop 816 can be employed, as discussed with
~I respect to Fig. 12, to assure compar~son of the level of
~¦ each horizontal blanking pulse sligh~ly after the beginning
! of each horizontal blanking pusle, for example, during the
front porch of each horizontal blanking pulse.
The additional outputs of timing network 526 illustrated
~l in Fig. 13 include horizontal drive pulses ~rom synch signal
'¦ generator 808, vertical blanking synch pulses from synch
¦ signal generator 808, end of field pulses from counter 828,
and vertical interval signals from the Q output of flip-flop
826. The horizontal drive pulses from synch signal generator
¦ 808 are defined with respect to timing network 526 as a
, square wave locked to the horizontal synchronization rate
which, because of counter 814 being set to only 5 rather -
! than 6 master clock counts, passes from negative to positive
at or slightly after the beginning of each horizontal
blanking pulse. The vertical ~lanking synchroniza~ion
pulses from synch signal generator 808 are defined with
respect to timing network 526 the same as with respect to
timing network 116, namely as a signal which is negative
going half-way through th~ vertical synchronization pulse of
, a video signal and remains negative until termination of the
~I vertical interval .signal. The vertical interval signals
I from flip-flop 826 are the same as the vertical interval
l! signals from flip-flop 424 Fig. 9, name~y, they are signals
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¦ which are high during the vertical interval and low during
'¦ the fields between vertical intervals. Finally, the end of
jj field pulses from the output of counter 828, like counter
!¦ ~, . i
Ij 426 of Fig. 9, are designed to provide a short end of field
,I pulse at the start of each vertical interval.
The horizontal drive pulses, horizontal flyback pulses,
l vertical interval signals, end of field pulses, and vertical
'I blanking synch pulses from timing network of 526 of Fig. 13
l are coupled to synch gate 528 and video gate 530 as illustrate~
1~ I in Fig. 12 and operate as explained above. Furthermore, tlle
horizontal flyback pulses and vertical interval signals from
timing network 526 illustrated in Fig. 13 are coupled to
, synch and inversion control 520 as illustrated in Fig. 11
,i and operate as explained above.
I The above-described subscription system is uniquely
suitable for use with a standard television transmitter for''' '"'
'I several reasons. First, no transmitter power reduction is
;, required since the picture video is transmitted at exactly
the same level as in normal NTSC transmissions, the only ¦-
!I difference being that the actual video is sometimes revexsed
to provide the equivalent of a negative image, and some '
horizontal blanking pulses are suppressed preferably ap
proximately 6db. Second, no change whatsoever is re~uired
or desirable in the setting of predistortion circuits of a
~5 '¦ transmitter over that used for standard NTSC transmission.
Even during horizontal blanking pulse suppression, the pulse
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is being transmitted in the predistorted and linearized
I portion of the transmitter characteristic. Accordingly,
Il only one exciter tuned for standard pTSC transmission is
required. All the modifications to the signal are done in
' the video domain and consist of simply a blanking pulse
offset and a signal inversion on a controlled basis. No
gain change is introduced into the transmission system at ',
any time. Even the blanking pulse suppression is accomplished
i with a simple bias level offset, as opposed to gain change, I -
I thereby preserving the transmitted fidelity and linearity of
the pulse.
In the decoder, the signal is restored to its original
state, before modulation onto an output carrier by a series
Il of switching controlled bias changes at a modulator. The
, decoder simply follows the random suppression format by
sampling each horizontal blanking pulse dur~ng the "front
porch" in order to determine its level. If it is below
' blanking level, the decoder automatically switches in the .
correct bias level to bring the pulse back to its original
~0 state. Conversely, if the pulse is at a blanking level, it
is deemed normal and no change is re~uired. .¦
Video inversion is accomplished on a random field by ~!
, field basis. The decoder simply samples a particular line !'
i in the vertical interval of each ~ield to determine whether
'5 1¦ that line is at the black or white level. Ii that line is-
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¦ at the white level, the decoder assumes video inversion from
the subsequent field and will invert each active video
portion of every line of the followi~g field. Conversely,
,¦ if the line is at the black level, normal video is assumed
5 1l and no inversion is required. ~hus, the decoder may be said
to be format agile in that it changes to suit whatever
format is transmitted.
It should be noted that the starting point and reference
I for the decoder is the vertical interval in each field
' wherein ini~ial synchronization and timing are established
since the format during this interval is always known.
Another important feature of the described system is that,
since the decoder is forma~ agile, no signal is required to
I switch the video from scrambled to standard NTSC broadcastO
However, since it is desirable to switch the sound, the
presence of the audio subcarrier signal will cause the sound
to switch from`normal base band audio ~o subc~rrier audio
during scrambled transmission, and can also be used to
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switch the video scrambling cir~uits~
2n 1 Even though it is possible to alter the video inversion
! and synchronization suppression formats at random and at any
! order, in practice, standard non-inver~ed video preferably
will not be sent unless synchronization suppression is in
effect. This assures that one form of scrambling is present
~S ' at all times.
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ll The suggested rate of change for video inversion is
i,, approximately 3 consecutive but randomly chosen fields of
standard or non-inverted video out o~ every 100 fields. The
I¦ rate of change for suppressed synchronization should be
~l approximately one fielcl of non-suppressed synchronization,
randomly chosen (but never corresponding to a field of non- ,
inverted video) out of every 60 fields of suppressed synchronization
I No two fields of unsuppressed synchronization should be
1 consecutive. The preferred operational combination will
1 tend to yive the scrambled picture a flashing effect which
is quite annoying. It will also tend to produce the same
interruption of the picture for unauthorized or "bootleg
decoders" which are not quite sophisticated enough to handle
! the full format agility re~uired in the subject system. The ¦-
; 15 l, two interacting forms of scrambling plus the random variations .,produce a very effective form of scrambling and produce a
high degree of security.
Additional advantages and modifLcations will readily
i occur to those skilled in the art. The invention in its
20 1i broader aspects is therefore not limited to the specific j
details, representative apparatus, and illustrative examples !
" !:
,i shown and described. ~ccordingly, departures may be made
from such details without departing from the spirit or scope
of applicant's general inventive concept.
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