Note: Descriptions are shown in the official language in which they were submitted.
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Background of the Invention
The present invention rëlates to a means for optimizing
the utilization of a waveform analyzer. More specifically
it pertains to a means of modifying a repetitive input
signal through programmed variations of offset and gain
such that the dynamic range of a waveform analyzer may be
more effectively utilized.
This invention is particularly, but not exclusively,
useful for video broadcast applications where it may be
used to analyze complex video signals or video test
signals. The invention may be readily applied to other
testing requirements such as audio equipment or the like.
The design of waveform analyzers capable of accurate
and repeatable measurements of complex signals has long
been a goal of instrument designers. Prior efforts have
resulted in waveform analyzers incorporating special
purpose circuits and complex filtering. Also, test setups
must be changed in order to accurately analyze different
parts of a complex waveform.
In accordance with an aspect of the invention there is
provided a waveform analyzer for analyzing complex wave-
forms comprising: a summing point one input to which is
the complex waveform to be analyzed; a programmable
amplifier responsive to gain data for controllably
amplifying the output of said summing point; a signal
analyzer coupled to receive the output of said programmable
amplifier for producing therefrom gain and offset data and
time and control data; means for receiving and storing said
gain and offset data; means for receiving said time and
control data and producing therefrom an address of gain and
offset data stored in said receiving and storing means,
said addressed gain data being applied to said programmable
- amplifier; and means for converting said addressed offset
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data to an analog offset signal which is fed to said
summing point for combination with the input complex
waveform.
According to an embodiment of the present invention,
nominal offset and gain values are stored in an instruction
store. The signal to be analyzed is applied via a summer
such that the signal plus the nominal offset value is
applied to a digitally programmable amplifier. The
resulting output signal is analyzed in a signal analyzer
where a list of offset and gain values needed to provide
optimum resolution is compiled, along with a list of the
times at which these values should take effect. The gain
and offset data are stored in the instruction store. The
time data are
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computed by counting clock pulses with reference to a
pulse at the repetition rate of the input signal.
The time data are sent to a controller which, by
counting clock pulses with reference to the trigger
pulse, determines when to send the address of the
optimum gain and offset data to the instruction store.
The addressed data are sent from the instruction store
to a digital-to-analog converter (DAC) to produce the
offset signal and to the digitally programmable ampli-
fier to alter the gain thereof. The resulting output
signal more effectively utilizes the dynamic range of
the signal analyzer.
It is therefore an object of the present inven-
tion to provide a signal analyzer which utilizes a
plurality of offset and gain values to dynamically
pre-process an analog signal.
It is another object of the present invention to
provide a signal analyzer which can easily process a
complex waveform.
It is a further object of the present invention
to provide a signal analyzer which makes full use of
its dynamic operating range.
Brief Description of the Drawings
Various features and advantages of the present
invention will become apparent upon consideration of
the following description, taken in conjunction with
the accompanying drawings wherein:
Fig. l is a block diagram of a waveform analyzer
according to the present invention;
Fig. 2 depicts the processing of a typical video
test signal by a waveform analyzer constructed accord-
ing to the present invention;
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Fig. 3 is a block diagram of one embodiment of
signal analyzer 30 of Fig. l; and
Fig. 4 is a block diagram of one embodiment of
controller 60 Fig. 1 and Fig. 3.
Detailed Description of the Preferred Embodiment
Referring to Fig. 1, therein is illustrated a
block diagram of a preferred embodiment of the present
invention.
The signal to be analyzed enters the waveform
analyzer at terminal 5 which is connected to one input
of summer 10. Summer 10 may be any suitable summing
point such as a summing amplifier. The output of
summer 10 is coupled to a digitally-programmable ampli-
fier such as that disclosed in United States Patent
No. 4,335,356 which issued to P.S. Crosby on June 15, 1982.
The amplified output signal is fed to signal analyzer 30.
5ignal analyzer 30 may be any conventional wave-
form analyzer including manually controlled or com-
puterized analyzers. It may comprise an oscilloscope
for monitoring and a human operator for providing gain
and offset information to instruction store 50 and
timing and control information to controller 60. Or
signal analyzer 30 may comprise a computer-based wave-
form digitizer which digitizes the input signal and
generates the gain and offset and timing information
based upon computer analysis of the digitized wave-
form. Signal analyzer 30 receives clock pulses 45 and
trigger pulses 55. Trigger pulses 55 may be generated
by some external source, however the frequency thereof
must be an integer submultiple or equal to the repeti-
tion rate of the input signal. A known number of clock
;~ pulses 45 occur after each trigger pulse.
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Instruction store 50 is preferably a random
access memory (RAM) in which is stored the gain data
produced by signal analyzer 30 for programming
digitally-programmable amplifier 20.
Controller 60 receives time and control data from
signal analyzer 30. It also receives clock pulses 45
and trigger pulses 55 in order to synchronize it with
signal analyzer 30. Controller 60 utilizes this data
to select the address of the required gain and offset
data stored in instruction store 50. The addressed
gain data are fed to the control input of amplifier 20
and the offset data are sent to DAC 40 where it is
converted to an analog equivalent. DAC 40 may be any
converter suited to the particular application of the
invention. For example, in a preferred embodiment DAC
40 comprises a high-precision (0.01 percent accuracy)
converter. The output of DAC 40 is coupled to one
input of summer 10 where it is algebraically combined
with the next repetition of the input signal.
In order to aid in understanding the operation of
the system of Fig. 1, several initial operating condi-
tions must be assumed. Namely, that amplifier 20 is
programmed for minimum gain and DAC 40 is programmed
to midscale. This is accomplished by nominal gain and
offset values stored in instruction store 50. The
first repetition of the signal is summed with the
nominal offset value and then analyzed by signal
analyzer 30. The peak-to-peak amplitude of the signal,
for example, may be measured. Other signal parameters
may also be analyzed in order to determine the new
values of offset and gain. Typically, the peak-to-peak
value of the input signal will be such ~that the
dynamic range of the signal analyzer will not be fully
utilized. Another common occurrence is that the input
signal will have a dc level (offset).
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The signal analyzer will output a list of offset
and gain values needed to make optimum use of dynamic
operating range of the signal analyzer. Also included
in the output of signal analyzer 30 are data speci-
fying the time at which the new offset and gain valuesshould be applied to DAC 40 and amplifier 20, respect-
ively. The time data are computable by counting clock
pulses 45 with reference to trigger pulses 55. These
time and control data are sent to controller 60, which
by counting clock pulses 45 with reference to trigger
pulses 55, determines when to address the gain and
offset data in instruction store 50 and whether the
store is in the read or write mode. The selected gain
data are sent to amplifier 20 to adjust its gain to
compensate for the dc level of the input signal. The
selected offset data are sent t~ DAC 40 where they are
converted to an analog equivalent before being summed
with the next repetition of the input signal. The
signal out of summer 10 is the original input signal
with its dc level removed. This corrected signal is
then amplified by amplifier 20 according to the gain
data from instruction store 50. The signal at the
output of amplifier 20 now makes better use of the
signal analyzer~s dynamic operating range.
The above-described process is graphically illus-
trated in Fig. 2 by showing the processing of a
typical input signal. The signal depicted is the well-
known linearity stairstep test waveform. This waveform
is designed to measure nonlinear distortion of a video
system. The waveform consists essentially of a series
of high frequency sinewaves arithmetically added to a
lower frequency varying dc stairstep signal.
The input test waveform 300 is summed in summer
10 with the offset signal 310 generated by DAC 40 from
data stored in instruction store 50 to produce wave-
form 320. It can be seen that although the dc com-
ponent has been removed from the input signal the
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dynamic range of waveform 320 is less than that of
waveform 300. Consequently, the gain in the region of
the subcarrier packets (designated A in waveform 300)
may be increased, in this example, by a factor of
approximately 3.5 without exceeding the dynamic range
of the signal analyzer. This increase in gain is
provided by amplifier 20 which has been programmed by
gain data from the instruction store. The resulting
waveform 330 may now be analyzed with greater resolu-
10, tion by signal analyzer 30.
Fig. 3 illustrates an embodiment of signal
analyzer 30 which may be used in the above-described
system. The signal analyzer is configured around
analog-to-digital converter (ADC) 410. Maximum utiliza-
tion of the dynamic operating range of ADC 410 is
achieved by applying dynamic offset and dynamic gain
to the input signal before it is digitized.
In this embodiment, the offset data are generated
- by microcomputer 400 and loaded into instruction store
(RAM) 50 via address and data bus 405. Microcomputer
400 may be comprised of commercially available com-
ponents such as those of the Motorola M6800 series.
Detailed discussion of the interconnection, operation,
and programming of the microcomputer is not presented
herein because extensive information on such units,
including timing diagrams, block and extended block
diagrams, details on reading data from or writing data
in memory, flow charts, and signal descriptions is
given in the "M6800 Microprocessor Applications
Manual" copyright 1975 by Motorola, Inc. This micro-
processor is also described in U.S. Patent No.
3,962,682, which issued to T.H. Bennett on June 8, 1976.
Using the foregoing references it is believed that a
person skilled in the art could construct a micro-
computer such as that used in the embodiment of Fig. 3
without undue experimentation. Signal RAM 420, ROM
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430, and real time clock 440 are conventional also and
will not be described for that reason. Memory con-
troller 415 governs the flow of digitized signals by
determining which signals are stored in signal RAM 420.
An analog offset waveform is produced by out-
putting the offset data stored in RAM 50 to DAC 40
where they are converted to an analog signal. RAM 50
also stores dynamic gain data for programming ampli-
fier 20. Controller 60 determines when the gain andoffset data should be outputted.
A controller suitable for use in the present
invention is illustrated in Fig. 4. As previously
, 15 mentioned, the controller receives time data from
signal analyzer 30. These data are stored in time
stack 500 which is preferrably a first-in, first-out
memory. The time data stored are digital words repre-
senting the time at which the gain and offset data
stored in instruction store 50 should be accessed. The
controller also receives as inputs clock pulses 45 and
trigger pulses 55 for purposes of synchronization with
the other elements of the waveform analyzer.
Time stack 500 has its output connected to one
input of digital comparator 510 the other input of
which is connected to receive the output of counter
520. Counter 520 is driven by clock pulses 45 and
reset by trigger pulses 55. The output terminal of
comparator 510 drives the clock (CK) input of counter
530 and the strobe input of time stack 500. Counter
530 is also reset by trigger pulses 55. The output of
counter 530 is the address of the offset and gain data
required to adjust the input waveform.
By way of operation, the initial repetition of
the input signal is analyzed by signal analyzer 30 and
the gain and offset data are stored in instruction
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store 50 and the time data are stored in time stack
500. The first time value in the time stack is placed
at one input of comparator 510 and the output of
counter 520 is present at the other input of compara-
S tor S10. When the count out of counter 520 is equal tothe first time value, a logical "one" is generated by
comparator 510. This "one" clocks counter 530 and
advances its output state to the next address in
instruction store 50. The gain and offset data stored
at the addressed location are output to the program-
mable amplifier and the DAC, respectively. The logical
"one" output of comparator 510 also strobes the time
stack and causes it to place the next time value on
its output bus. The above-described sequence of events
lS repeats and the gain and offset values are adjusted
according to the data in instruction store 50.
It may be observed in the foregoing specification
that such specification has not been burdened by the
inclusion of large amounts of detail and specific
information relative to such matters as circuitry,
timing, and the like since all such information is
within the skill of the art. It should also be noted
that the particular embodiment of the invention which
is shown and described herein is intended to be illus-
trative and not restrictive of the invention. There-
fore, the appended claims are intended to cover all
modifications to the invention which fall within the
scope of the foregoing specification.
