Note: Descriptions are shown in the official language in which they were submitted.
- . ~iS45~2
EM-23~3 S~LF VERIFYING I.OGIC SYSTEM
This invcntion rclc~tts gcncrcllly to fault ~etection
systems, ~nd rnore particularly r~:latcs to Çault d~tecting in
VI,SI chips, circuit boards carrying such chips ~Ind colrplete
computer systems in which faults heretofore not successfully
dealt with are detectable with a high degree of accuracy which
permits rapid diagnosis of the source of the fault so that
trouble shooting diagnosis and maintenance times are substan-
tially reduced.
/0 Computer systems have progressed in stages first
from circuits made up individually of discrete circuit elements,
then to circuits made up of discrete basic logic structures
such as gates and registers discretely interconnected by wiring
tec~miques, and then to higher density circuits utilizing inte-
grated circuit packages. Malfunctions in finished equipment
arise from several areas, one area being defects in the indi-
vidual components which make up the circuits, a second area
being improper wiring or interconnection of the components,
and the third area being failures which result~n the compon-
ents or wiring subsequent to manufacture of the finished as-
sembly.
The testing of the components which go into the cir-
cuitry was a relatively simple matter with discrete items such
as transistors and prepackaged counters and flip-flops. How-
ever, with the advent of integrated circuit packages containing
quite a number of circuit components, as the density increased,
the difficulty and expense of testing increased drastically
until at the present time the cost of testing of a large scale
integrated circuit package (LSI) by the manufacturer can ex-
3 0 ceed the cost of manufacture by a substantial margin. Equip-
ment for testing some presently available integrated circuit
'`~' .
llS4~i4,'~
packages is extrernely expens;ve and at the same time is gener-
all~ inclpll)lc of ~l~kr~ ely t~-~in~ 1l pojsihle functiot1al
uses of sllch in~c~;r~tcd circu;t packages. According1y, com-
ponents which appear to test properly can iII fact Lail in a par-
- ticular application.
With the advent of very large scale integrated cir-
cuits (VLSI) containing in excess of five thousand gates per
chip, the testing problem has become somewhat unmanageable.
It is not economically feasible to test all possible combina-
/O tions of logic through such a dev-ice b~cause the cost of writin_
testing programs which can exercise all of the logic, and the
; time cost of actually carrying out such tests would be prohi-
bitive. Moreover, with VLSI circuits the logic density per
chip is so high that discrete access to all of thc logic is
impossible because of the limited availability of pin connect-
ions to the chip. For example, a ten thousand gate VLSI may
have 130 input-output pins. However, this excess of logic
capacity relative to access points makes it possible to utilize
some of the logic capacity to provide fault checking inside of
- ~ the chip by internal]y generating test signal routines at alldesired points along the logic chain so that the occurrence of
faults can be detected quickly in a chip, circuit board or in a
system by a relatively fast check-out procedure in which all chips
of a system self-verify simultaneously.
The basic concept of the present invention is the pro-
vision within each integrated circuit chip at various desired
points along the internal logic chain of fault detecting cir-
cuits and of a plurality of signal generators and supervisory
control circuits therefor integrally formed within the chip and
selectably actuatable to generate desired signals necessary to
llS~
exercise the logic by causing such signals to be processed
through the processing logic and the fault detecting circuits.
This provides the basis for substantially eliminating external
testing of VLSI chips and circuit boards and the saving of very
large amounts of money by dispensing with the need for extremely
; costly test equipment, the cost of developing test pattern data
bases and programming the test equipment.
Additionally, when a computing system is assembled
the power is turned on to make sure that it is ready for deli-
very to the customer, and what is done is to run confidencetests or "go/no-go" tests. Specifically, that is a battery of
tests that can take several hours to run and at the end of
which it is possible to determine that the system works. ~ow-
ever, such tests are based on stimuli at the system level and
not at the individual chip level, and all chips and intercon-
nections in the system may or may not have gotten an exhaustive
test. In contrast, in a system according to the invention, when
the power is turned on, all the chips throughout the entire
system self-verify simultaneously, in parallel, and also check
the interconnections between and among themselves. It takes
substantially less time and is much more exhaustive and much
more thorough than what is accomplishable with a battery of
generalized tests.
The use of multiple fault detectors and multiple
stimulus generators formed internally within the chip can pro-
vide a multiplicity of error signals which are multiplexed with-
in the chip to produce encoded output error signals each of
which designates the fault which has been detected within the chip.
These encoded error signals can then be routed to special error
handling chips which receive encoded error signals from a large
5~
number of places, such as a group of chips or circuit cards,
and by correlating the information contained in the encoded
error signals are able to identify the source of the fault.
Such sources might be identifiable as a particular VLSI chip,
the interconnections between VLSI chips, a particular circuit
card, a power supply line to a circuit card or a group of such
cards, or other faults. Consequently, trouble shooting diag-
nosis of machine malfunctions is greatly sim~lified and main-
tenance time reduced. Accordingly, it is a primary object of
the invention to provide a novel self testing system of fault
detecting in devices using very large scale integrated circuit
packages by utilizing integrated circuit chips structured to
incorporate integrally therewithin test routine generating
signal generators and fault detection circuits.
Another object of the invention is to provide a
novel self-verifying fault detecting system as aforesaid in which
both internal stimulus generation and fault detection are carried
out internally within a VLSI chip at least at one intermediate
point along the logic chain, and preferably at a plurality of
intermediate points along the logic chain.
Still another object of the invention is to provide
a novel self-verifying fault detecting system as aforesaid which
contains internally its own test circuits for completely test-
ing all system components and interconnections and requires no
external test equipment for system checking.
A further object of the invention is to provide a
novel self-verifying fault detecting system as aforesaid in
which duplicate functional logic or duplicate complementary
logic within the chip is utilized together with internal stimulus
generators and multiple comparators to provide fault detection.
- 4 -
`` ` ~15~542
Another object of the invention is to provide
a novel self-verifying fault detecting system in which
~ separately encoded error signals are generated within a
.; VLSI chip, which encoded error signals are utilized to
identify with a high degree of particularity the sources
of the particular faults which have been registered.
In accordance with an aspect of the invention
there is provided an integrated circuit chip comprising
internally in combination a data processing chain having
an externally connectible input circuit and an externally
connectible output circuit, internal stimulus generator
means having signal output circuits and control means
operable for activating said generator means to cause said
generator means to produce a predetermined signal pattern
at the said generator means signal output circuit, internal
stimulus generator supervisory control means having
actuating means and control signals output means, said
actuating means being effective when actuated to produce a
sequence of control signals at said control signals output
means, first coupling means connecting said signal output
circuits of said internal stimulus generator means
internally within the chip to said data processing chain
at an intermediate point along said chain so that said
generator predetermined signal pattern may be injected
into said data processing chain when said generator means
is activated by said generator supervisory control means,
second coupling means connecting said supervisory control
means controls signals output means internally within the
chip to said internal stimulus generator control means
effective for operating said control means to activate
said generator means.
- 5 -
1~54S~
The foregoing and other objects of the invention
will become clear from a reading of the following
specification in conjunction with an examination of the
appended drawings, wherein:-
Figure 1 is a functional block diagram of asingle VLSI chip embodying the invention;
Figure 2 is a functional block diagram of one
form of the ISG Supervisor shown as a single block in
Figure l;
Figure 3 is a functional block diagram of one
form of the ISGs each shown as a single block in Figure 1;
Figure 4 is an expanded functional block diagram
of Figure 1 illustrating one form of the combinational
and/or sequential logic network and FDCs each shown as a
single block in Figure l;
Figure 5 is a waveform timing diagram for the
implementation of the invention shown in Figures 2 to 4;
Figure 6 illustrates the assemblage of self-
verifying VLSI chips into a complete system for fault
processing; and
Figure 7 illustrates the application of the
invention to a duplicate logic VLSI chip.
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: - 5a -
115~542
In the several figures, like elements are designated
by like reference characters.
Turning now to the drawings, and ~irst to Figure 1,
there is seen a functional block diagram of a VLSI chip, with
all of the VLSI devices which go to make up the invention illus-
trated in broad functional block form. The normal processing
logic 10 is illu~trated as having a vertical information flow
moving from the primary inputs 11 through the network to the
primary outputs 12. Outputs from the Logic Network 10 are taken
- 10 to the Fault Detectors 13, 14 and 15 from selected points along
the logic network, with the outputs of the fault detectors being
routed to an Error Status Generator 16 where the various signals
from the fault detectors are encoded according to various occur-
rence combinations to produce error signals at the output of
the Error Status Generator 16 on the group of lines 17.
The Logic Network 10 could be any digital circuitry
as found in any computer. The Fault Detectors 13, 14 and 15
couldfor example be parity checkers, comparators, residue code
checkers, interval timers or any other of the many well-known
checking circuits. The Error Status Generator 16 could typic-
ally be a function table encoding matrix, as are commonly used.
While three fault detectors are illustrated, it should be under-
stood that any appropriate number of fault detector circuits are
utilizable in accordance with the best design criteria for the
: particular type of logic network with which such circuits are
being utilized. One use of a fault detector circuit configura-
tion as illustrated in elements 10 through 17 is fully described
~l5~S4Z
in United States Patent No. 4,233,682 which issued to H.L.
Liebergot et al on November 11, 1980. However, the system
according to the present invention does not require the
use of duplicate functional or complimentary logic, being
completely usable with a single chain logic.
To the right of the Logic Network 10 are shown a
plurality of Internal Stimulus Generators, ISGs 18, 19 and
20 which have outputs feeding into the Logic Network 10 at
various points along the network. The output signals from
the ISGs 18, 19 and 20 are respectively designated as
being delivered to the Logic Network 10 by the multiple
signal paths provided by each of conductor groups 18', 19'
and 20'. These conductor groups will of course have a
variable number of conductors dependent upon the type of
ISG utilized. Additionally shown is a Fault Detector
Circuit 18A which monitors ISG 18 for faults, and upon the
detection of such, sends signals to Error Status Generator
16. ISGs 19 through 20 are also monitored by fault
; detector circuits (not shown) which perform a similar
;20 function for these ISGs. The ISGs and some of the network
logic are controlled by signals received from the ISG
Supervisor 21 over a group of signal lines 22, 23 and 24
which are representationally shown as single lines but
which each constitute a conductor group. The signals
generated by the ISGs are also returned to the ISG
Supervisor via the lines 25, 26 and 27. While the ISGs
are illustrated as three in number, it is to be understood
that the actual number of ISGs utilized and their
`'particular locations and connections to the Logic Network
`-30 10 will be determined by the nature and complexity of the
particular logic network. A fault Detector Circuit 21A
monitors the ISG Supervisor 21 for faults, and upon
-- 7 --
:
1~L54S4Z
the detection of such, sends si~nals to Error Status Generator
16. Inputs to the ISG Supervisor for illustrative purposes in
the illustrated system are shown to the right of the ISG Super-
visor 21 and consist of the clock pulse signals 01 and 02, a
SYSTEM CLEAR signal representationally shown as being generat-
able by means of a switch 28, and an INITIATE SELF VERIFICATION
signal illustratively shown as being initiatable by a switch 29.
A functional block diagram of one particular possible type of
ISG Supervisor is illustrated in Figure 2, while a logic diagram
Of one particular possible type of ISG 18 is illustrated in Fig-
ure 3.
Consider now Figure 2 which illustrates one possible
form of ISG Supervisor 21. Within the ISG Supervisor is a PROM
(programmable read only memory) 30 which is "M" bits wide and
"N" words deep, the particular makeup of the output "M" bits at
any given time being controlled by the address sent to the PROM
from the PROM Address Counter 31. The "M" bits associated with
a particular address of the PROM 30 are held in a Control Regis~
ter 32 as the output signals 22A to 22I illustrated in Table 1
subsequently to be described, and as the output signals on con-
ductor groups 23 and 24. These signals are changed with the
occurrence of each of the clock pulses 01 after self verification
has been initiated, as will be subsequently explained. Self
' verification is illustratively shown as being initiated by closure
. of switch 29 which generates the INITIATE S.V. signal, clearing
: the PROM Address Counter 31 and Control Register 32. This signal
is also routed to the ISGs, being signal 221SV sent to ISG18.
The Control Register 32 LOAD input is actuated by a
signal from "and" Gate 33 when the latter receives a coincidence
`:
: - 8 -
~154S4Z
of the ~1 clock pulse and the SV signal from the Q output of
D Flip Flop 34. The Q output arises when the '`E" input of
Flip Flop 34 is triggered by the trailing edge of the INITIATE
S.V. signal. The SV signal or Q output from Flip Flop 34 is
also directed to "and" Gate 35 which also receives inputs fxom
the 02 clock pulse and Inverter 36. The input signal to Inverter
36 is generated by "and" Gate 37 when there is a coincidence of
zero detector signals occurring on ISG output lines 25, 26 and
27, this same output signal from "and" Gate 37 also being pre-
sented as one of the inputs to "and" Gate 38 which also receivesthe 02 clock pulse. The output of "and" Gate 38 is presented
as one input to "or" Gate 39 which also receives an input signal
from the System Clear Switch 28. Either signal into "or" Gate
39 produces an output signal to the "C" or CLEAR input of Flip
Flop 34, which, when it occurs, terminates the Q state of the flip
flop and the SV signal. One way of fault checking of the ISG
Supervisor 21 illustrated in Figure 2 could be by utilizing a
parity checker as the Fault Detector Circuit 21A, parity check
of the output lines 22A through 22H being provided by a parity
check bit on line 22I. Parity checking may be examined or
, strobed by each ~2 pulse. The operation of this particular ISG
Supervisor 21 will be more fully explained in conjunction with
an explanation of Figure 4, but before turning to that figure,
attention should be directed to Figure 3 which illustrates the
, internal logic of ISG 18.
Figure 3 illustrates one possiblP form that an ISG
might take, and for purposes of illustration is to be considered
as the ISG designated as 18 in the other figures of the drawings.
The ISG includes an 11 Bit Binary Gounter 40, the three most sig-
nificant output bits of which are routed in parallel to a 4 Bit
~lS~S~Z
Shift Register 41 while the eight least significant output bitsare routed in parallel to a 9 Bit Shift Register 42. The out-
put bits of the Binary Counter 40 are also respectively routed
to Parity Generators 43 and 44 and Zero Detector 45. Each of
the parity generators generates a paxity bit which is also appro-
priately inserted into the respective Shift Registers 41 and 42.
The parallel outputs of Register 41 and Register 42 are examined
for parity respectively by Parity Checker 41A and Parity Checker
42A, and upon detection of faults, signals are sent to Error
Status Generator 16. Parity checking is strobed by the 22H
signal. If checking of Counter 40 and Zero Detector 45 is de-
sired, duplication and comparison could be utilized.
The Zero Detector 45 generates a positive logic high
output on conductor 25 when the 11 Bit Binary Counter output
has been decremented to zero.
The Shift Registers 41 and 42 are parallel loaded
from the Eleven Bit Binary Counter 40 in the presence of a
PARALI~EL LOAD ENABLE Signal 22A received from the ISG Supervisor
?, 21, while readout from the shift registers on lines 18A and 18B
is a serial readout which takes place in the presence of SERIAL
LOAD ENABLE Signal 22B from the ISG Supervisor 21. The 11 Bit
Binary Counter is initially jammed to a state of all "ones" at
the output when the Counter 40 LOAD input receives the 22ISV
signal from the ISG Supervisor.
After the output of all "ones" from the 11 Bit Counter
` 40 has been processed through the logic, a 22G signal from the
ISG Supervisor 21 is presented to the Decrement input of the
Counter 40 thereby causing the count in the counter to be re-
duced by one, which changes the arrangement of the counter out-
put bits. The decrementing process continues under control of
the ISG Supervisor until the count in the Binary Counter 40 has
-- 10 --
~lS~4~
been reduced to zerol whereupon this condition is detected by
the Zero Detector 45 which sends a high signai ~ack to the ISG
Supervisor over line 25 to "and" Gate 37. W~en all of the ISGs
have completed their routines, whatever they may be and however
many stages they may take, all of the input signal to "and"
: Gate 37 in Figure 2 will be high and will gate through to the
input of Inverter 36 and "and" Gate 38. Inverter 36 then presents
a low output to "and" Gate 35, effectively closing the gate so
that no further incrementing of the PROM Address Counter 31 can
10 occur. The occurrence of the next 02 clock pulse arriving at
"and" Gate 38 is now gated through, and is gated through "or"
Gate 39 to the "C" input of Flip Flop 34, thereby clearing the
flip-flop and suppressing the Q state. This terminates the SV
signal, which in turn closes down "and" Gates 33 and 35. As
will be subsequently seen in connection with Table 1, the De-
crement signal occurs at the end of a cycle, and the PROM Add-
ress Counter will be at an address such that all of the output
signals from the Control Register 32 will be zeros, and the ISG
: and ISG Super~isor outputs will be such as to return the Logic
20 Network 10 to its normal processing state. At this point, the
. ISGs are effectively locked out of interaction with the Logic
Network 10.
Consider now Figure 4, which is an expansion of
: Figure 1, to illustrate a specific implementation of a ~ortion
of Logic Network 10 and the employment of Fault Detector Cir-
cuits 13, 14 and 15 as parity checkers. As shown, the primary
inputs to the Logic Network 10 are connected to the Parallel
Load inputs of a 9 Bit Register 46 which also includes a Serial
Load mode into which data from the ISG 18 can be serially
30 loaded from the ISG 9 Bit Shift Register 42 via line 18B when
the Serial Load input is enabled by ISG Supervisor control signal
~gt5~2
22B. The output of the 9 Bit Register 46 is presented to
the input of 8 Bit Shifter 47 and also to ~arity Check Fault
Detector 15, the parity b~t from Register 46 being also di-
rected to the Parity Check Fault Detector 15 and to the parity
bit input of 9 sit Register 48. The output of the Circular 8
Bit Shifter 47 is routed to the input of the 9 Bit Register 48
which has its Enable Data control input controlled from "or"
Gate 49.
: The Normal Enable signal for 9 Bit Register 48, which
is utilized in the normal operation of the logic, is presented
-' to "or" Gate 49 from "and" Gate 50 which has its other input
normally high from the output from Inverter 51 when the SV
signal from the ISG Supervisor is low, that being when self
verification is not in process. When self verification is in
process so that the SV signal is high, it enables "and" Gate 52
and inhibits "and" Gate 50 through inverter 51. The Normal
Enable signal is thereby prevented from controlling 9 ~it Re-
gister 48, this control coming from "and" Gate 52 when the ISG
Supervisor produces control signal 22E. The Shift Control for
the 8 Bit Shifter 47 is produced by 4 Bit Register 53 which has
its Parallel Load inputs connected to the outputs of another
point in the logic chain within the VLSI. The Serial Load Data
input of Register 53 is connected to the output of ISG 4 Bit
Shift Register 41 via line 18A while having its Serial Load
Enable circuits controlled by ISG Supervisor output signal 22C.
Referring now also to figures 2, 3, 5 and Table 1,
assume that the apparatus is to be turned on and that Figure 4
represents a part of a sin~le~ VLSI chip. Representational
switch 28 is first momentarily closed to clear the system, the
SYSTEM CLEAR signal passing to "or" Gate 39 and therethrough to
- 12 -
~lS4S4Z
the clear input "C" of D Flip Flop 34 -thereby insuring that the
flip flop is not in the Q state. With the ~ystem now cleared,
representational switch 29 is now momentarily closed to gener-
ate the INITIATE SELF VERIFICATION signal which is transmitted
to the CLEAR inputs of PROM Address Counter 31 and Control Re-
gister 32 tG clear the Control Register and clear the PROM add-
ress Counter to zero, and is also routed out of the ISG Super-
visor as signal 22ISV to the LOAD input of 11 Bit ~inary Counter
40 in ISG 18, thereby causing the latter to be set to a count at
its outputs of all "ones". The outputs of Binary Counter 40 are
presented to the inputs of the Shift Registers 41 and 42 in ISG
18 and to the Parity Bit Generators 43 and 44. However, this
data is not entered into the shift registers until the Parallel
Load Enable signal 22A is received from the ISG Supervisor.
As seen in the waveform timing diagram of Figure 5,
while the INITIATE SELF VERIFICATION signal cleared the PROM
counter 31 and Control Register 32 and loaded the ISG counter,it
.,
does not have any effect at the E input of Flip Flop 34 untilits
trailing edge appears. It is at this time that Flip Flop 34
is set to its Q state and the SV signal arises. The SV signal
is transmitted to Inverter 51 to inhibit Gate 50 and is also
transmitted to "and" Gate 52 to enable the latter, both as
shown in Figure 4. The SV signal together with the high out-
put of Inverter 36 enables "and" Gate 35 to pass the next 02
clock pulse and increment the Prom Address Counter 31 to step
it from its 0 Address to Address 1. Address 1 is shown in
Table 1, and the designated conditions on the Control Register
output lines 22A to 22I corresponding to Address 1 arise when
the next 01 clock pulse is passed through "and" Gate 33 to the
LOAD input of Control Register 32 to thereby trans~er these "M"
bits into the Control Register from the PROM 30.
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l~X4S~Z
TA,BLE I
. .
PROM PROM OUTPUTS 2 2
ADDRESS A B C D E F G H
_
O ~ - N O P -- -->
: 1 1 0 0 0 0 0 0 0
2 < NOP -
3 0 1 1 0 0 0 0
4 ~ --NOP- - - >
0 1 1 0 0 0 0 0 0
10 6 ~ NOP
:~ 7 0 1 1 0 0 0 0 0 0
8 ~ NOP -
9 0 1 1 0 0 0 0 0 0
` 10 ~ NOP ~'
''~ 11 0 1 0 0 0 0 0 0
12 ~ _ NOP-- >
13 0 1 0 0 0 0 0 0
14 ~ ~ NOP
.: 15 0 1 0 0 0 0 0 0
2016 ~ ~ NOP
17 0 1 0 0 0 0 0 0
18 ~ NOP
. 19 0 1 0 0 0 0 0 0
~ NOP
21 0 0 0 1 0 0 0 0
2 2 ~ NOP >
23 0 0 0 0 1 0 0 0
24 ~ NOP--
0 0 0 00 1 0 0
3026 ~, NOP
27 0 0 0 00 0 1 0
28 ~ NOP
29 < --NOP ~
< NOP 3,
31 < --NOP
NOP = ALL ZEROS
-- 14 --
S~
At Address 1 the 22~ signal goes high and causes
the respective outputs from the ISG Binary Counter 40 and
Parity sit Generators 43 and 44 to be parallel loaded into the
4 Bit and 9 Bit Sh~ft Registers 41 and 42. The PROM Address
Counter 31 now cyclically steps through the entire sequence
of PROM addresses under control of clock pulse 02 ~hich incre-
ments the Address Counter each time it subsequently occurs.
` After the Address Counter 31 is stepped to change the address
in the Prom 30, the ap~earance of the next 01 clock pulse trans-
fers the PROM output to the Control Register 32 to thereby change
the conditions on the output control lines 22A to 22I. As seen
in Table 1, all of the even addresses of the Prom 30 are desig-
.~
nated NOP or ALL ZEROS which creates pulses and insures stabili-
zation of the system before the next operation occurs. Under-
standing that this is what occurs, the progress of the checkout
can be observed by following the sequence of PROM addresses.
When the PROM address has stepped to Address 3 the
22B and 22C signals are generated. Registers 46 and 53 are
shown as being loaded serially in order that no additional
stages of logic need be added to the normal data path. The 22B
signal enables serial load of 9 Bit Register 46 and enables the
data in the ISG Shift Registers 41 and 42 to be serially shifted
one bit at a time out of the Registers on lines 18A and 18B to
the Serial Load Data inputs of the logic network Registers 53
and 46 respectively. The 22C signal enables serial load of 4 Bit
Register 43. Since only one bit can be shifted during each clock
pulse, the 22C signal persists for four successive odd PROM add-
resses so that the four bits from ISG Shift Register 41 may be
successively shifted into 4 ~it Register 53, after which the 22C
signal returns to the zero state and no further shifting can
occur from ISG Shift Register 41.
- 15 ~
~15~54Z
Similarly the 22B signal persists for nine succes-
sive odd PROM addxesses so that the nine bits in ISG Shift ~e-
gister 42 may be successively shifted into logic network Re-
gister 46. The data in the logic network Registers 46 and 53
being now complete, parity check is carried out at the next
PROM address which is Address 21 causing the generation of the
22D signal which actuates the parity check in checkers 14 and
15, the outputs from these checkers being routed to the Error
Status Generator 16.
The PROM Address 23 causes the generation of the 22B
signal which is transmitted to "and" Gate 52 producing an output
which is routed through "or" Gate 49 to the Enable input of 9 Bit
Register 48 so that the data from the Circular Shifter 47 is en-
tered into the 9 Bit Register 48. PROM Address 25 causes the
22F signal to be generated as a strobing signal which together
with the data and parity output bits from Register 48 are pre-
sented to Parity Checker 18, the output of which is also routed
to Error Status Generator 16. The outputs of all of the Parity
Checkers are examined in the Error Status Generator 16 and appro-
priate Error Signals 17, if any, are generated for subsequent
processing. This completes the checking of that segment of the
illustrated Logic Network 10 with respect to the first output
bit pattern from the ISG 18 which consists of all "ones".
It is now necessary to change the count in the 11 Bit
Binary Counter 40 in ISG 18 and repeat the entire process. This
occurs when the PROM Address Counter 31 is shifted to its next
odd count, which is Address 27, thereby generating the 22G sig-
nal. The 22G signal is routed to the Decrement input of 11 Bit
Binary Counter 40 of ISG 18 and thereby reduces the count at the
~o output of the Counter 40 by a count of one. The next four PROM
- 16 -
1~54~5:
addresses are illustrated in Table 1 as being NOP since in the
; illustrated case the PROM would be a standard 32 word device.
When the PRQM Address Counter cycles back to Address O and
then Address 1, the entire sequence already described is re-
peated. This sequence of events continues cyclically until the
22G signal decrements the count i~ the sinary Counter 40 to
zero.
At this point the Zero Detector 45 detects this
condition and sends a high signal back along Conductor 25 to
ISG "and" Gate 37. The high at "and" Gate 37 on line 25 is not
gated through unless there are also highs on lines 26 and 27 at
the input of the "and" Gate 37. Since ISGs 19 and 20 may be
structured differently than ISG 18, it may be that control sig-
nals are still being generated on some of their control lines
23 and 24 during PROM Addresses 28 through 31. When however
they have completed their sequences and have also produced
zero detection signals, the coincidence of all of these signals
at "and" Gate 37 passes therethrough to Inverter 36 thereby pro-
ducing a low at the input of "and" Gate 35 and closing the gate
20 to further incrementing of the PROM Address Counter 31. Addi-
tionally, the "and" Gate 37 output enables "and" Gate 38 so
that the next 02 clock pulse is gated through, and through "or"
gate 39 to clear Flip Flop 34 and suppress the SV signal, thus
also inhibiting "and" Gate 33.
At this point the self verification of this parti-
cular VLSI chip has been completed. Other VLSI chips may take
shorter or longer times or the same time to complete their self
verifying. However, Error Signals 17 generated from the Error
Status Generator 16 of each of the VLSIs will have been being
30 processed during the verification procedure and failure indica-
tions will have been recorded as to type and location.
- 17 -
~l54~5~;~
An extension of the just described fault pro-
cessing is illustrated in Figure 6 which shows the manner
in which such fault processing may be extended to an entire
: system. A plurality of Circuit Cards 54 are shown, each
of which carries a plurality of VLSI chips 55. The VLSI
chips on each card are of the same type as illustrated in
Figure 1, or Figure 7 to be subsequently described, each
including an Error Status Generator, which in Figure 6
have been labelled as 16A and 16B through 16N. The output
signal from each of the Error Status Generators 16 are
routed for processing to a Card Fault Generator 56 which
correlates the various signals from the different Error
Status Generators and encodes the various combinations of
signal occurrences to produce error signals at the output
which represent detected faults in all of the VLSIs carried
by that particular card, as well as the card wiring.
All of the signals from the assemblage of Card
Fault Generators 56 are routed to a System Fault Generator
57 which in turn correlates the signals from all of the
cards 54 and VLSIs 55. The card Fault Generators 56 and
System Fault Generator 57 may also be encoding function
tables, or any other desired type of encoding system. The
output signals from the System Fault Generator 57 are then
routed to the System Control Console for display and/or
recording in accordance with the nature of the detected
faults.
Figure 7 illustrates the invention as generally
shown in Figure 1 and as applied to the duplicate logic
VLSI fault detection circuit configuration described in
the aforementioned United States Patent No. 4,233,682.
All of the elements shown in Figure 1 are illustrated in
Figure 7, the
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` 1159L542:
same reference characters being preceded by the numeral 1.
FQr example the Logic Network 10 shown in Figure 1 is shown in
Figure 7 as the overall Logic Network 110 consisting of the
Functional Logic Network llOA and the Duplicate Logic Network
llOs, which latter may either he a duplicate of the Functional
Logic Network llOA or may be duplicate complementary logic,
all as set forth in the aforementioned copending patent appli-
cation.
When duplicate logic is utilized for the Logic Net-
work 110, the same system is employed for the ISGs and the ISG
Supervisor. Accordingly, the ISG Supervisor 121 consists of a
Functional Logic ISG Supervisor 121A and either a Functional or
Complementary Logic ISG Supervisor 121B, the particular type
of Supervisor 121B being the same as the type of logic used in
Network llOB, that is, Functional or Complementary. Each of
the ISG Supervisors 121A and 121B is organized with its own
set of ISGs 118 through 120 and 118' through 120' respectively.
The outputs of these ISGs are routed to the Logic Networks llOA
and llOB as already described in conjunction with Figures 1 to
4-
Outputs are taken from multiple points within the
Logic Networks llOA and llOB and are routed to an appropriate
number of Fault Detector Circuits 113, 114 and the plural de-
tectors 115, the outputs of which are fed to an Error Status
Generator 116 which examines the received signals and encodes
them to produce error output signals on lines 117. The Fault
Detector Circuits 113 through 115 in addition to checking for
faults solely within each of the Networks llOA and llOB, also
check the operation of the two Logic Networks llOA and llOB
against each other in order to insure that the same processing
results are being produced by both networks at comparable logic
~59~S~2
points in the two Networks llOA and llOB. This is shown re-
presentationally in Figure 7 by taking the outputs of the logic
networks to a given fault detector circuit from the same point
diagrammatically along the logic network. That is, it is ob-
served that the logic network outputs at 112A and 112B are both
compared in Fault Detector Circuit 118, while the inputs to
Fault Detector Circuit 114 are observed representally to be
taken from the same points along the processing chains in the
Logic Networks llOA and 110B, and similarly for the inputs to
Fault Detector Circuit 115.
It will be appreciated that the present invention is
subject to various modifications and changes which may be made
from time to time without departing from the essential spirit
or general principles of the invention, and accordingly it is
intended to claim the same broadly as well as specifically as
indicated by the appended claims.
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