Note: Descriptions are shown in the official language in which they were submitted.
~ l~'t5~g
INVERTER DRIVE CIRCUIT
Background of the Invention
~ any inverter circuits have previously been used including
those with pulse width modulation to establish variable output
power. The prior art has known circuits with feedback from the
output of the inverter to control the input drive signal in
accordance wi~h some electrical output condition suc'n as voltage
or current. The prior art has known a drive transformer used
with two alternately conducting semiconductors so that when the
drive transformer was energized of one polarity a first semi-
conductor conducted and when energized in the op~osite polaritya second semiconductor in the inverter conducted. The dif-
ficulty with such a unit was that the drive transformer had a
core material exhibiting a rectangular hysteresis loop and this
core material was capable of being saturated. A variable a~ount
of saturation in accordance ~ith variable conduction times, for
pulse width modulation, meant that the operation of the circuit
was erratic, especially under rapidly changing conditions, being
dependent upon the amount of conduction time in the ~revious
cycle because of the variable degree of saturation.
The prior art inverter circuits have also included those of
relatively high current carrying capabilitv, but where this has
been attempted to be combined with high frequency of operation,
the sem;conductors used, for example transistors, have been of
the type which exhibited a relatively high forward voltage drop
yet a relatively low reverse blocking voltage. This has made
the operation of such an inverter circuit subjec~ to potential
failure if the control voltage on a semiconductor should be too
hioh in the reverse direction. Also such inverter circuits have
often been ones wherein it was difficult to achieve a turn-off
--1--
5 ~ ~
of a particular semiconductor at the proper time in order to
control the width of the pulses in -the pulse width modulated
inve.rter. Still further in such prior art inverters, especially
during transient conditions, a suddenly applied load might tend
to cause the inverter to have a greatly increased output which
could overload the current carrying capabilities of the inverter
semiconductors.
Summary of the Invention
The problem to be solved is therefore how to construct a
pulse width modulated inverter circui-t to overcome these dis
advantages of the prior art. This problem is solved according
to the present invention by an inverter circuit comprising, in
combination, at least first and second semiconductors connected
forfull wave alternating output on output terminals from DC
input terminals, a signal source having an alternating signal
voltage, first and second drive transformers and first and
second capacitors connected to the control electrodes of said
first and second semiconductors, respectively, first means
connected to be controlled by said signal. voltage and connected
through said drive transformers to control the alternate
conduction of said first and second semiconductors and to drive
said drive transformers from a first saturated flux level to a
second flux level, second means including said first and second
capacitors, third means associated with said first means and
connected to establish a voltage across said first and second
capacitors, and said second means connected to be controlled
by said signal voltage and connected to apply the voltage of
said capacitors to the control electrode of the respective
A l~!~S ~g
semiconductor in a direction to supply reverse bias thereto
to turn off said respective semiconductor and also connected
to said transformers to apply a reset current thereto during
the non-conduction period oE the respective semiconductor to
reset the flux of the core of the transformers to said firs-t
flux level.
There is also disclosed an inverter circuit having
controllable semiconductors connected for a controllable
output alternating voltage, comprising, in combination; a
control circuit connected to control the conduction time of
said semiconductors, said control circuit having controllable
input means connected to control the conduction time of said
semiconductors, means establishing a voltage reference signal,
means connected to sense the amount of output current from
said semiconductors and to develop a current signal, rectifier
means having a plurality of outputs connected to rectify a
signal proportional to said current signal, a current limit
setting potentiometer connected to said reference voltage signal
to establish a reference signal representative of a maximum
value of inverter output current, a first current limit means
including an operational amplifier connected as a comparator
and having first and second inputs, means connecting said
comparator first input to one of the outputs of said rectifier
means; and means connecting said current limit setting poten-
tiometer reference signal to said second input of said comparator;
and means connecting the output of said comparator to said
controllable input means of said control circuit whereby the
output voltage of said inverter is decreased upon the output
1157~
of said comparator changing sta-te when said rectified signal
exceeds said reference signal.
In addition, there is disclosed an inverter circuit
having at least a first controllable semiconductor connected to
supply an al-ternating voltage from DC terminals comprising, in
combination; a drive transformer having a secondary, means
including a decoupling unidirectional conducting device connec-
ting said secondary to the control electrode of said first
semiconductor, turn-on means acting on said drive transformer
to cause conduction through said decoupling device to said
control electrode to turn on said first semiconductor, turn-off
means acting on said drive transformer to effectively terminate
the turn-on signal on said secondary to terminate conduction
of said first semiconductor, and said decoupling device having
a recovery time to achieve reverse blocking capability longer
than that of said first semiconductor to thus prevent reverse
bias being applied on the control electrode of said first
semiconductor.
An object of the invention is to provide a pulse width
modulated inverter drive circuit which provides for extremely
rapid current limit in view of rapidly increasing transient
output currents.
Another ob~ect of the invention is to provide~an inverter
circuit with an improved turn-on and turn-off means for control-
lable semiconductors.
Another object of the invention is to provide an improved
inverter circuit with drive transformers controlling the
conduction of first and second semiconductors wherein the
dri-ve transformers are reset to saturation in the opposite
direction between each power pulse of the semiconductors.
i 1S7~ l~
Another object of the invention is to provide an improved
inver~er circuit with a decoupling diode so as to prevent a
too high reverse bias being applied on the control electrode of
the semiconductor.
Other objects and a fuller understanding of the invention
may be had by referring to the. following description and claims,
taken in conjunction with the accomnanying drawi.ng.
Brief Description of the Drawing
FIG. 1 is a schematic diagram of a part of a drive circuit
for an inverter,
FIG. 2 is a schematic dia~ram of the remainder of the drive
circuit plus the inverter power circuit,
FIG. 3 is a schematic diagram of a modified bias circuit
for the semiconductors,
FIG. 4 is a schematic diagram of a circuit usable in the
control portion of the drive circuit of FIG. l; and
FIGS. 5 and 6 are graphs of voltage and current pulses in
the circuit of FIG. l.
Description of the Preferred Embodiments
FIGS. l and 2, side by side, illustrate an inverter circuit
11 which includes in general an inverter power circuit 12 in
FIG. 2 and a drive circuit 13 which ~enerally is the remainder
of FIGS. 1 and 2.
The inverter power circuit may include a center tapped
transfQrmer or separate decoupled transformers plus first and
second controllable semiconductors 14 and 15, or a half bridge
with two semiconductors, or it may be a three phase system with
at least three controllable semiconductors. However, as shown,
the power circuit 12 includes an inverter bridge circuit 18
whic~ includes the first and second controllable semiconductors
14 and 15 as well as third and fourth controllable semiconductors
16 and 17, respectively. In this preferred embodiment of FIG. 1
115'~5~g
these semiconductors 14-17 are ~ransistors. The inver~er
bridge 18 operates from positive and negative DC input terminals
19 and 20, respectively, and has an alternating current output
on terminals 21 and 22. The drive circuit 13 controls the in-
verter bridge 18 such that the first and second transistors 14
and 15 conduct alternateIy, and since this is a brid~e circuit,
transistors 14 and 17 conduct simultaneously and transistors 15
and 16 conduct simultaneously. A high frequency switching
transistor satisfactory for use in this high voltage, e.g. 300
volts, circuit is a type TTP 563.
A control circuit 26 is connected to regulate the conduction
time of the semiconductors 14-17. This control circuit is one
which controls the width of the output pulses of this inverter
bridge 18.
The control circuit 26 has output lines 27 and 28, and
these may be considered a signal source to control the conduction
times of the first through fourth semiconductors 14-17. The
control circuit 26 may be a commercially available controller
such as Motorola part number MC 3420, and has alternate output
pulses on the output lines 27 and 28, às shown by the graphs of
voltages 27A and 28A on FIGS. 5B and 5C, respectively. These
pulses are a logic zero or low condition from a normally high
output. The control circuit 26 has a variable width of these
pulses, in order that the drive circuit 13 will provide a
variable conduction time of the semiconductors 14-17. The width
of these pulses as shown in the graph 27A and 28A cannot be made
so wide that the pulses in~ersect or overlap, instead there is a
minimum deadtime 32 as shown in FIG. 5A. This is established by
a deadtime voltage 29 which intersects the triangular wave for~
36 shown in this FIG. 5A. ~he triangular wave form is caused
by an internal oscillator which, in this embodiment, causes a
--6--
11575~'3
ramp up volta~e f~om 2.0 volts and then a ramp down voltage
from 6.0 volts Resistors 30 and 31 are connected between a
voltage reference terminal VR and ground, and the junc~ion of
these resistors is connected to a deadtime adjust terminal DT
in order to set the length of this minimum deadtlme 32.
The requency of oscillation is set by a resistor 33 con-
nected between a terminal RE and ground and also set by a
capacitor 34 connected between a tenminal CE and ground. The
control circuit has controllable inPut means on conductors 37
and 38. Conductor 37 is connected to input terminal CV and
conductor 3~ is connected ~o inhibit terminal I~H.
The control circuit 26 has the ability to control the
width of the pulses on the output terminals 27 and 28. From a
review of FIG. 5A, one will note that if the value of the control
voltage on ~he conductor 37 is decreased, then the control
voltage 37A intersects more of the tip of the triangular wave 36
and hence this would increase the width of the output pulses.
The control voltage 37A is shown as making a sharp decrease at
the location 37B to a low level below the triangular wave form
36 in order to illustrate a maximum output condition of the
inverter drive circuit 13. If the normally high voltage on the
inhibit terminal to which conductor 38 is connected goes low,
then this forces the output on the output lines 27 and 28 to go
high.
The control circuit terminal VR is a constant voltage
reference from the internally generated voltage reference signal
and this is applied through an optional voltage follower circuit
42 in order to increase the power capabilities of this constant
volta~e reference. The voltage follower circuit 42 has an
output terminal 43 with a low impedance and this is supplied
through a potentiometer 44 to ground. The potentiometer 44
I15 75~3
supplies a controllable re~erence voltage to an output volta~e
regulator circuit 45. Terminals 46 and 47 are connected to all
or preferably a portion of the output o~ the inverter at the AC
output termir~als 21 and 22. This voltage is rectified by
rectifier 48 and filtered by an induc~or 56 and by a capacitor
49 in parallel with resistors 50 and 51. The inductor input
filter senses the average voltage rather than peak voltage across
the output terminals 21 and 22. The wiper of the potentiometer
44 is connected to ground throu~h a capacitor 52 and is also
connected through a resistor 53 to the inverting terminal of
a comparator 54. ~he non-inverting terminal of the comparator
is connected to the junction of resistors 50 and 51. The voltage
at the junction of resistors 50 and 51 is a positive voltage
which normally slightly exceeds the voltage from the wiper of
potentiometer 44. As a result the comparator 54 normally has
a small positive voltage output. This might be abou~ +5 volts,
for example, as shown in the control voltage 37A of FIG. 5A.
If the output volta~e increases somewhat, ~or example, as
caused by a decreased load current, this will increase the
error signal which is the output of comparator 54 and this is
passed by a diode 55 onto conductor 37 and the control voltage
terminals CV. As shown in FIG. 5A an increase in the voltage
37A will narrow the width of the pulse output on the conductors
27 and 28, and as shown on the curves 27A and 28A of FIGS. 5B
and 5C. This reduces the output voltage o~ the inverter power
circuit 12 to return the inverter output to a stable condition.
The inverter drive circuit 13 also incl.udes first and
second current limit circuits 61 and 62. The first current
limit circuit 61 has an input on terminals 63 and 64. These
terminals are shown in FIG. 2 as being the outp~t rom a current
1 1 5 tS ~9
transformer 65 connected in the output Leads of the inverter
bridge circuit 18. This current signal on the input terminals
63 and 64 in FIG. 1 i5 supplied to a rectifier 66, and the
rectified signal is supplied ~o a pair of voltage divider
resistors 67, 68 and then through a diode 69 to the non-
inverting input of an amplifier connected as a voltage follower
70. On the non-inverting input of voltage follower 70 a peak
charging circuit is provided which includes a small capacitor 71
in parallel with a resistor 72 to ground. In one practical
circuit constructed in accordance with the invention, the
capacitor 71 was 0.1 micro~arads and the resistor 72 was 220,000
ohms. Such a combination means that the small capacitor 71
is quick to charge with a sudden increase in load current and the
relatively high resistance of resistor 72 means that the
capacitor 71 is relatively slow to discharge. Under these
conditions, the peak charging circuit is stable and does not
readily pass any AC signal therethrough, but instead follows
-
the peak of the incoming current limit signal.
The output of the voltage follower 70 i.s supplied to
resistors 73 and 74 and the junction thereof supplies an output
to the non-inverting input of an op-amp 75 connected as a
comparator. This op-amp has the inverting input connected through
a resistor 76 ~o the wiper of a potentiometer 77 which is con-
nected to the voltage reference source at terminal 43. The
setting of the wiper on the potentiometer 77 sets the value of
the current limit and this is normally set at a higher magnitude
of voltage on the inverting input of op-amp 75 than the output
on the non-inverting input thereof rom the voltage follower 70.
Accordingly, upon an increase in current output of the inverter
bridge circuit 18 such that the signal on the non-inverting
input of op-amp 75 exceeds that reference current limit point
_g_
115~t5~
on the invertin~ input, the normally ne~ative output of
op-amp 75 changes to a positive output and this is passed
through a diode 78 to the conductor 37. This increasing
positive signal acts, as will be seen in FIG. 5A, to decrease
the width of the output pulse and hence decrease the output of
the inverter brid~e circuit 18. Accordingly, current limi~ing
is effected.
The second current limit circuit 62 includes a comparator
81 which has the non-inverting input thereof connected to the
same wiper of potentiometer 77 so that it is controlled by the
same current limit point as the first current limit circui~ 61.
The inverting input of the comparator 81 is connected to the
junction of resistors 67 and 68 to receive the current limit
signal from rectifier 66. A capacitor 82 is connected to
ground from this inverting input. Normally the voltage at the
non-inverting input exceeds the magnitude of the voltage at
the inverting input of comparator 81 and both are positive
voltages so that the output of comparator 81, connected to
conductor 38, is normally positive. The capacitor 82 is a
very small value capacitor, for example, in one practical
circuit embodying the invention this was 100 picofarads. As a
result this second current limit circuit 62 is an extremely
rapidly operatin~ circuit. Should the current output of the
inverter bridge circuit 18 suddently increase, for example,
as in a short circuit, then ~his second current limit circuit
62 acts much more rapidly than the first current limit circuit 61.
In the first circuit 61 the capacitor 71 must charge
before that first circult 61 can act and a typical response time
might be 50 microseconds. In the second current limit circuit 62,
since the capacitor 82 is a very small capacitor, the response
time might typically be two to five microseconds. This would be
-10-
~ 5~3
less than one cycle of operation at the frequency of the
regulator circuit which might be anywhere from 2KHZ to lOOKHZ.
Upon this rapidly increased current output from the inverter,
e.g. ~rom a short circu.t, the inverting input on comparator 81
would exceed that of the non-inverting input to reverse the
output thereof causing it to go from a positive or logic one
condition to a low or logic zero condition. This low on the
inhibit terminal INH of the control circuit 26 immediately
forces the output on both lines 27 and 28 to go high to cause
cessation of all ou~.put of the inverter brid~e circuit 18. Thus
the extremely rapid operation o~ the second current limit
circuit 62 is used to protect the entire inverter circuit 11
from damage and especially to protect the semiconductors 14-17
from burnin~ out. It also permits the various components to be
of a smaller power capability rating than would otherwise be
the case. For example, not only the transistors 14-17 may be
smalle,r in current rating, but other components carrying power
thereafter ~ay be smaller. For example, the output terminals
21 and 22 may supply some form of a rectifier. The components
therein also may be made smaller in current carrying capacity
because of the protection afforded by the very rapid action
of the second current limit circuit 62.
In the first current limit circuit 61 the voltage follower
70 has the advantage of having a satisfactory voltage output to
drive the resistors 73 and 74, yet it has a high input impedance
so that it does not load the resistor 72 and capacitor 71.
Accordingly, the time constant of resistor 72 and capacitor 71
will not be affected.
The error signal fro~ comparator 54 is shown above to be
that which controls the width of the pulses on the output lines
27 and 28 of the control circuit 26 and hence the width of the
l15'~5~
pulses which form the output of the inverter bridge circuit
18. The drive circuit 13, see FIG. 2, does control the conduction
time periods of the transistors 14-17 and the drive circuit 13
includes a tur-n-on circuit 90 and a turn-of~ circuit 91.
The turn-on circuit ~0 acts throu3h first through fourth
drive transformers 94-97 each connected in association with ~he
first through fourth controllable semiconductors 14-17,
respectively. The turn-on circuit 90 controls the set and reset
of these transformers 94-97. These transformers may be ones with
a substantially rectangular hysteresis loop so that the magnetiz-
ing current of the transormers is extremely small and therefore
in effect the transformers are essentially transparent, ~erely
giving a transformation of voltage and current in accordance with
the turns ratio. A feature of the present invention is that a
separate drive transformer is used for each of the controllable
semiconductors 14-17, rather than the common prior art practice
of one transformer for a pair of alternately conducting semi-
conductors. The drive transfo~mers are substantially identical
and in general only the transformer 94 and its associated circuitry
with the first semiconductor 14 will be described in detail. The
transformer 94 has a primary winding 99, a secondary winding 100,
a reset winding 101 and a regenerative winding 102.
The turn-on circuit 90 acts through a drive transformer
to the respective semiconductor. In the case of the ~irst trans-
former 94 and first semiconductor 14, it acts through the second-
ary 100 and what may be termed a bias circuit to a control
electrode of this semiconductor 14. The semiconductor is shown
as an NPN transistor havinv base drive. The secondary 100 has
terminals 104 and 105 with terminal 104 colmected through a
capacitor 106 to the base of the transistor 14. This capacitor
is a part of the turn-off means. Bias means is connected across
-12-
~ 51g
the capacitor 106 and in the preferred embodiment this bias means
is an impedance which limits the voltage across the capacitor 106.
The impedance in the preferred embodiment is a plurality of
diodes 107 and 108 which are poled to conduct current from
terminal 104 to the base o transistor 14. A resistor 109 is
connected across the secondar~ 100. The collector of transistor
14 is connPcted to the positi~e DC terminal 19 and the emitter
of tr~nsistor 14 is connected through the regenerative winding
102 to the collector of the next transistor in the bridge
circuit 18, transistor 16, and is also connected to the AC output
terminal 21
The turn-on circuit 90 includes first and second turn-on
transistors 111 and 112 shown in this preferred embodiment
as being PNP type with the emitters connected together and
through diodes 113 to a positive supply voltage at terminal 114.
This positive supply voltage terminal 114 is connected through
resistors 115 and 116 to the ou~put lines 27 and 28, respectively,
from the controL circuit 26. This connection makes these
lines normally high, until driven low by the pulse output on the
respective line from the control circuit 26 Resistors 117 and
118 are connected in these lines 27 and 28, respectively, to
convey the signal on lines 27 and 28 and to provide a proper
current to the bases of the transistors 111 and 112. The
collector of transistor 112 is connected to the anodes of a
group o diodes 121-124 and the collector of transistor 111 is
connected to the anodes of a group of diodes 125-128. Current
limiting resistors 129 are individually connected to the cathodes
of the diodes 123-126, respectively. Conductors 131-138 are
connected to the cathodes of the diodes 121-128, respec-tively,
with the resistors 129 interposed in such connection wit'n
respect to the diodes 123-126. These conductors 131-138 are
1 1575 1''3
connected to the various terminals on the Primary windings
and reset windings of the pulse transformers 94-97.
The turn-off circuit 91 includes irst, second and third
transistors 141, 142 and 143, respectively. The collector of
MPN transistor 141 is connected through a resistor 144 to the
positive supply terminal 114. The emitter of this transistor is
connected to the emitter of PNP transistor 142, the collector o~
which is grounded. The base of the transistor 141 is connected
through a diode OR circuit or ga~e formed by diodes 145 and 146
with the anodes connected to the base of transistor 141 and the
cathodes connected to the output lines 27 and 28, respectively.
The base of the transistor 142 is connected through another
diode QR circuit consisting of diodes 147 and 148 to the output
lines 27 and 28, respectively. A resistor 149 connects the
positive supply voltage terminal to the base of transistor 141
and a resis~or 150 connects the emitter of transistor 142 to
tl~e base thereof. This emitter is also connected to the base
of the NPN transistor 143 with the emitter of this transistor
connected through a plurality of biasin~ diodes 151 to ground.
The collector of transistor 143 is connected through a diode
QR circuit consisting of a group of diodes 153-156. The anodes
of the diodes 153-156 are connected to the conductors 133-136,
respectively. The emitter of transistor 143, in addition to
being connected t'nrough the biasing diodes 151 to ground, is
also connected to a clamping terminal 157 which in turn is
connected by clamping conductors 158 to the lower terminal
of each of the primaries on the transformers 94-97, such as
primary winding 99.
A constant curren~ source 162 is used in the preferred
embodiment as a current source for the reset windings such as
winding 101 on transformer 94. This constant current source is
-14-
11~75~
connected by conductors 163 to the upper end of the reset
windings on each of the transformers 94-97 and this constant
current source is also connected to ground. Protective diodes
164 are connected across the series combination of each o the
transistors 14-17 and its regenerative wi~ding, such as windin~
102, in order to limit the reverse voltage applied to the
respective transistors. A transient supressing capacitor 165
and resistor 166 are connected in series across the AC output
terminals 21 and 22.
' ~
The output lines 27 and 28 from the control circuit 26 may
be considered a signal source having an alternating signal voltage.
As shown in FIGS. 5B and 5C, this alternating signal voltage is
actually alternating pulses and the pulses are of variable width
in order to control the conduction times of the semiconductors
14-17. FIG. 5 is a diagram of graphs of various portions of the
circuit with FIG. 5D showing a graph lllA of the current
conducted by transistor 11~, and with FIG. 5E showing a graph
112A of the current conducted by the transistor 112. Transistor
143 may be considered a clamping transistor and FIG. 5F shows
a graph 143A of the current conducted by this clamping transistor
143. FIG. 5G shows a graph l4A of the base current conducted by
the transistor 14 and FIG. 5~ shows a graph 15A of the base
current conducted by transistor 15. FIG. 5I is a graph 21A of
the output voltage appearing at the output terminals 21, 22.
This is for the particular case of a resistive load, or the case
of a load consisting of a rectifier and an inductive input filter.
Referring to this graph 21A there is a sequence of three differ-
ent operations for each transistor in one alternating current
cycle. The first step is s~own by the rising ~ave front 170
whîch is caused by the set of thè transLormer 94 and practically
-15-
1157519
simultaneous turn-on of the respec~i~e transistor. The second
step in the sequence is the tu~l-off of the respective transistor
shown by the falling wave front 171. This is accomplished by the
clamp established on the transfo~mer 94 and this occurs durin~
the horizontal portion 172 of the output voltage curve between
positive and negative pulses. The third step in the sequence is
the reset of the respective transformer 94 which occurs during
the conduction period of the opposite transistor 15.
In more detail, the set of the particular transformer
will be described with respect to the first transformer 94. The
signal source on the control circuit lines 27 and 28 controls the
turn-on of the transistors 14-17. At the time that the output
line 27 goes low, as shown at portion 175 of graph 27A, this
turns on transistor 111 because the base thereof goes low.
Conduction of transistor 111 goes through the diode 125 and
resistor 129 to conductor 135. This makes current flow in what
will be termed the forward direction in the primary winding 99.
This sets the transformer core. The transformer is not driven
to forward saturation, instead, the flux level is partially
changed from the flux level at reverse saturation condition,
enou~h so that the secondary winding 100 emits a pulse out of the
terminal 104 which is passed by the diodes 107 and 108 to the
base of the transistor 14. This turns on this transistor almost
simultaneously with the beginning of the set of the core of the
first transformer 94.
FIG. SB throu~h 5I show that at time tl the control
circuit output line 27 has a low output pulse, the transistor 111
turns on, the transistor 14 turns on, and the out?ut of the
entire inverter circuit 11 has a positive ~oing output pulse,
due to conduction of both transistors 14 and 17.
The pulse from transistor 111 into the primary winding
99 continues, but it is not necessary in this particular circuit
-16-
1~575î~
because of the regenerative winding 102. A~ soon as the transis-
tor 14 begins to conduct, then current flows through the regen-
era~ive windinO 102 to supply current from the secondary winding
100 to keep transistor 14 turned on. This current flows through
the bias means which is the diodes 107 and 108 and this will
charge the capacitor 106 so that it is positive on the left side
as viewed in FIG. 2. It will be noted that transistor 17 is
also turned on by a similar action of turn-on of transistor
111 acting through diode 126 and resistor 129 to supply the
initial pulse to the fourth transformer 97 and turn on transistor
17. This energizes the two transistors 14 and 17 in the inverter
bridge circuit 18 so that an output voltage is supplied to the
terminals 21 and 22.
At time t2 in FIG. 5, the output pulse on the control
circuit output line 27 ceases and this line 27 goes bac~ to a
logi~ hi~h condition. The diode OR circuit 145-148 responds to
the change in the pulse and controls the turn-off circuit 91.
Since both lines 27 and 28 are hi~h, this turns off the transistor
142 and turns on transistors 141 and 143. The conduction of this
transistor 143 establishes a clamp or effective short circuit
across all of the drive transformers 94-97. To consider first
the transformer 94, the current through transistor 143 goes
through the clamping conductors lS~ to the lower end of the
primary winding 99, travels upwardly through this winding, back
through the conductor 135 and the diode 155 to the collector of
the transistor 143.
The capacitor 106 has previously been charged, during the
turn-on o~ transistor 14, so that it is positive on the left
side thereof, as viewed in FIG. 2. The voltage across capacitor
106 will be limited by the two diodes 107 and 10~. If these
are silicon diodes, the voltage will be about 1.4 volts. This
l 1575~9
voltage on the capacitor is trans~ormed by the ~ransformer from
the windin~ 100 to the wlndin~ 99 and this provides the voltage
causing current ~low throug~ the transistor 143. Transistor 143
in combination with diode 155 forms a low impedance circui~
which provides an effective short circuit on the transformer
winding 99, which in turn is transformed to the winding 100.
Thus even though the voltage on the capacitor 106 is a small
voltage, e.~. 1.4 volts, this is applied in the reverse direc-tion
to the forward or turn-on current, hence this is a reversely
applied bias on the base-emitter of the transistor 14 as shown
in FIG. 5G, to turn off this transistor. This reverse current
removes the stored charge of this transistor 14 and thus turns
it off. Durin~ this same time interval, the regenerative winding
102 is by transformer action short circuited by transistor 143
and diode 155 to eliminate the regenerative effect thereof.
The FIG 5 shows that at time t2 the control circuit
output line 27 goes high, the transistor lll turns off, the
transistor 143 turns on, the transistor 14 turns off, and the
output voltage of the inverter brid~e 18 ~oes to zero. The
clamp function on the trans~ormer 94 starts at time t2 and
continues as long as clean out or removal current is flowing
from the base of the transistor 14. This is shown as a small
pulse of current 143A in FIG. 5F. This cla~p is maintained,
without any substantial current flow, until time t3 when the
control circuit output line 28 goes to an on condition; namely,
goes low as shown in FIG. 5C. This is the start of the reset
func~ion of transformers 94 and 97.
At the time t3, because line 2~ goes low, the diode OR
circuit 145-148 causes transistor 142 to conduct and transistors
141 and 143 to cease conduction. FIG. 5E shows that transistor
112 now conducts and conducts current through all the diodes
121-124. That current through diode 124 sets the second drive
transformer 95 and turns on the transistor 15. That current
~ 157~9
throu~h diode 121 travels throu~h conductor 131 to the lower
end of the reset winding 101 on the first drive transforrner 94.
This current travels upwardly through this reset winding, as view-
ed in FIG. 2, then through the constant current source 152 to
ground. Since this is in a direction opposite to the previously
mentioned fo~ard direction of current in the primary winding 99,
this resets the flux in the core of the first drive transformer
~4 to a saturated condition in the reverse direction. This makes
sure that this transformer is fully saturated in the reverse
direction ready to again be set to turn on the transistor 14 at
time t5 as shown in FIG. 5. Current through the diode 122 from
tlle transistor 112 resets the fourth drive transformer 97 in a
manner similar to reset of the first drive transformer 94. It
will be noted that the resistors 129 limit the set current or
turn-on current to the primary winding and that the constant
current source 162 controls ~he reset current. The reset
voltage nay be made large for a positive reset of the transformer
no matter kow short the reset time available.
At the time t4 the clamping action of transistor 143 is
again reestablished on the first and fourth drlve transformers
94 and 97. In this case it does not perform any function on
these transformers because the capacitor 106 has now been
discharged. However, this clamp does perform a function on the
second and third drive transformers 9S and 96, because the
associated transistors have previously been conducting and the
capacitors associated therewith, similar to capacitor 106, have
previously been char~ed and are now supplying a volta~e for this
charge removal function.
Starting at time t5, FIG. 5 shows the condition of maximum
conduction periods for maxim~m output of the inverter bridge
circuit 1~. In this case the deadtime, shown in FIG. SI, is
the minimum deadtime 32.
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~ 1 575~g
The constant current source 162 is connected in the
circuit for the reset of each of the drive transformers 94-97.
This may be considered a constant current sink because the
positive supply voltage at terminal 114 passes through transistor
112 for example, diode 121, and passes upwardly through the
reset winding lOl and then through the constant current sink to
ground. This establishes constant current on each drive trans-
former reset winding during reset conditions~
FIG. 3 is a schematic diagram of a modified bias circuit
for use with the transistors 14-17. FIG. 3 shows only the
transistor 14 and identical circuits would be usecL with the other
transistors 15-17. Agaîn the fir~t drive transformer 94 is
shown with its windings 99, lO0, 101, and 102. The change from
the circuit shown in FIG. 2 is the addition of a decoupling
unidirectional conducting device; namely, a diode 180 and also
a protec~ive diode 181. A resistor 1~2 is connected between base
and emitter to provide a path for collector-base leakage current.
The decoupling diode is comlected in the bias circuit poled in
the same direction as the bias diodes 107, 108. The criterion
for the decoupling diode l~0 is that it have a longer recovery
time to achieve reverse blocking capability than that of the
base-emitter diode of the transistor 14. Diode 181 prevents
excessive reverse bias being applied on the base-emitter of this
transistor 14. The circuit of FIG. 3 has an advantage where
large currents and high frequency conditions are encountered.
In one practical circuit the inverter was supplying low
volta~e and high current at a frequency of about 20 kilohertz
with five volts output and 150 am?eres being supplied to the AC
output terminals 21 and 22. Under such conditions a transistor
is required which has high current conducting capabilities and
capable of being switched at high frequencies. A high frequency
-20-
llS 7S19
switching transistor to control this value o current ls a type
2~16277 transistor.
The transi~stors currently commerc:ially available for such
operating conditions have a fairly large forward base voltage
drop, e.g. as much as 3.5 volts and a relatively low reverse
blocking voltage, e.g. five vol~s. When one considers that
transient voltac,e spikes may occur, it is very difficult to
assure proper operation of the transistor without possibility of
failure due to exceeding the reverse volta~,e limitations. It
will be recalled that the application of reverse voltage occurs
because of the turn-off and even more because of the reset of the
drive transformer. During turn-off there was a clamp applying
a reverse voltage on the base-emitter of the transistor 14 in
order to cause it to cease conduction. This voltage came from
the capacitor 106. An even larger reverse voltage is applied
during reset conditions when the reset winding 101 is energized.
Now in FIG. 3, rapid resetting of the core of ~he drive trans-
- former results in a large voltage on all the wlndings o the
associated drive transformer. Because of the addition of the
decoupling diode 18Q, any reverse voltage on the secondary~100,
which is established during reset condition, is absorbed across
the decoupling diode 180, and hence no large reverse bias ls
applied across the base-emitter of transistor 14. The protective
diode 181 is also in the circuit to bypass any large reverse
bias voltages applied on the base-emitter of transistor 14 before
diode 180 stops conducting, limiti.ng such reverse voltages to the
forward voltage drop of this diode 181, e.g. 0.7 volts.
As stated above, the criterion for the decoupling diode
180 is that it should have a recovery time longer than that of
the transistor 14. The decoupling diode is therefore normally
considered a slow diode, that is, slow to recover reverse
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1~75~L9
blocking ca~ability, although this need not necessarily be the
case, it may be rather rapid so long as it is one which has a
longer recovery time than that o~ the transistor 14.
FIG. 6 illustrates the operation of the circuit of FIG. 3
on a time base expanded relative to that of FIG. 5. The ~ime
base in FIG. 6 has been expanded such that t~le time between t2
and t2 1 is less than two microseconds for a typical turn-of~
o a transistor 14. This FIG. 6 shows the same t2 as in FIG. 5
immediately above. The minimum deadtime 32 has been shown as
being muc~l longer, because of the expanded time base scale. At
the tîme t2 the graph 14B of the current passed by transistor 14
starts to decrease toward æero and passes on through zero to a
time t2 1 at which time the transistor 14 turns off due to the
reversely applied voltage from the dischar~in~ capacitor 106.
The diode 180 is still conducting, now in the reverse direction,
until a time t2 2 whereat the conduction of this decoupling diode
180 ceases. The current is now zero and remains at zero through
the remainder of the minimum dead~ime 32.
This illustrates another advantage of using the decoupling
diode 180. The reset time for resetting each of the drive
transformers may be made very short, for example, only a few
microseconds. This may be accomplished by applying a large
current on the reset winding in order to reset the core to the
negative saturation condition. Despite any large voltage
appearing on the reset winding and hence on the secondary 100,
the decoupling diode absorbs this voltage thereacross and prevents
it being applied as a reverse bias on the base emitter of the
transistor 14.
FIG. 4 illustrates an equivalent circuit ~or the control
circuit 26 which may be a ~Iotorola MC 3420 circuit. An internal
11~75~
voltage reference is generated by a re.Eerence source 185
operating ~rom a supply voltage input at terminal 114. This is
used internally and is also avallable at the voltage reference
terminal VR in order to set the minlmum deadtime 32~ see FIGS.
5A and 5I, at the deadtime adjust terminal DT. A ramp generator
186 produces a symmetrical triangular wave form r~mping up and
dswn between two fixed linits, e.g. 2.0 volts and 6.0 volts. The
frequency is determined by an external resistor connected to the
RE terminal and by an external capacitor connected to the CE
terminal. The outpu~ of the ramp ~enerator 186 îs available
externall~ at an R0 terminal and this is connected externally to
a ramp in terminal RI. This terminal leads to a Pl~ comparator
187 which compares the triangular wave form with the control
voltage on the terminal CV. This comparator 187 thus has a
positive pulse voltage for the length of time that the triangular
wave form exceeds the control voltage. Therefore this controls
the pulse width or the duty cycle.
A deadtime comparator 188 compares the triangular wave
form with the smaller voltage available on the deadtime terminal
DT. This is the deadtime voltage 29 as shown in FIG. 5A and
controls the amount of the minimum deadtime 32. A phase splitter
is included to obtain two 180 out-of-phase outputs in order to
control the two transistors 14 and 15. This phase splitter
consists of a toggle flip flop 189 with the clock signal supplied
through an ~D gate 190 from the outputs of the comparator 187
and the ramp generator 186. The output lines 27 and 28 are
fed by NPN transistors 191 and 192, respectively, so that when
turned on the output line is low. The output from the PW~I
comparator 187 is available on a terminal P~ and this is external-
ly connected to a symmetry correction terminal SC. Four-input
~ID gates 193 and 194 supply the transistors 191 and 192,
1'15~5~g
respectively, and permit base drive of these transistors only
when the triangular wave form exceeds the control voltage, when
the deadtime comparator has a high output, and when the flip
flop Q output is high. The inhibit signal ~ust al50 be high in
order to have an output on either of the two output lines 27 and
28, and this is controlled by an AND gate 195.
The presen~ disclosure includes that contained in the
appended claims, as well as that of the foregoing description.
Although this invention has been described in its preferred form
with a certain degree of particularity, it is understood that
the present disclosure of the preferred form has been made only
by way of example and that numerous changes in the details of the
circuit and the combination and arrangement of circuit elements
may be resorted to without departing from the spirit and scope
of the invention as hereinafter claimed.
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