Note: Descriptions are shown in the official language in which they were submitted.
1 157918
1 FIELD OF THE INVENTION
2 The present invention relates to a frequency-phase
3 comparator which permits derivation of frequency and phase
4 signals independently for application to a phase locked loop.
BRIEF DESCRIPTION OF THE DRAWINGS
6 Prior to the description of the invention, prior art
7 will be first described with reference to Figs. l, 3, 4a, 4b,
8 6, 7, 9 and lO follo~ed by the description of the invention
9 with reference to Figs. ll to 2~, wherein:
Fig. l is a circuit diagram of a priorart
11 frequency-phase comparator:
12 Fig. 2 is a circuit diagram of a charge pump circuit;
13 Fig. 3 is an explanatory graphic illustration
14 associated ~ith the circuits of Figs. l and ~;
Figs. 4a and 4b are explanatory grzphic illustrations
16 associated with the circuit of Fig~ l;
17 Fig. 5 is a block diagram of a phase locked loop
18 system;
19 Fig. 6 is a circuit diagram of a prior art charge pump
circuit;
21 Fig, 7 is a graphic illustration of an operating
22 characteristic of the Fig. l circuit combined with the charge
23 pump circuit of Fig. 6;
24 Fig. 8 is a graphic illustration of an idealized
operating characteristic of a frequency-phase comparator;
A.''
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__ __ _ _
,
, .
1 Fig, 9 is a circuit diagram of another prior art
2 frequency-p~lase comparator;
3 Fig. 10 is a waveform diagram associated with the
4 circuit of Fig. 9;
Fig. ll is a circuit diagram of a first embodiment of
6 the present invention;
7 Fig. 12 is a waveform diagram associated with the
8 circuit of Fig. ll;
g Fig. 13 is a modification of the Fig. ll embodiment;
Figs. l4 and 15 are waveform diagrams associated with
11 the circuit of Fig. 13;
12 Figs. 16 and 17 are modifications of the Fig. l1
13 embodiment;
14 Fig. 18 is a circuit diagram of a second embodiment of
the invention;
16 Fig. 19 is a waveform diagram associated with the
17 circuit of Fig. 18;
18 Fig. 20 is a modification of the Fig. 18 circuit;
19 Fig. 21 is a waveform diagram associated with the
circuit of Fig. 20;
21 Fig. 22 is a modification of the circuit of Fig. 20;
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1 15791~
1 DESCRIPTION OF THE PRIOR ART
2 United States Patent 3,610,954 discloses a digital
3 frequency-phase comparator which, as shown in Fig. 1,
4 compries a plurality of NAND gates interconnected to
respond to changes in logic level of two input signals~
6 the freguency/phase of which is compared. The co~parator
7 is responsive to changes in the trailing edges of the
8 input waveforms and produces outputs that are related to
g the repetition rate and relative phase of the inputs.
More specifically, the disclosed frequency-phase com-
11 parator includes first and second input coincidence gates
12 each of which has a first input thereof supplied with a
13 different one of two input signals, the phase and/or
14 frequency of which is compared. The outputs of each of
these input gates are connected to corresponding inputs
16 of first and second output coincidence gates, the outputs
17 of which are connected back to the second input of the
18 first and second input coincidence gates, respectively.
19 For controlling the operation of the logic system, a
first pair of cross-coupled control coincidence gates
~ , , .
.
1 15791~,
is used, each control gate having first and second
inputs and output. The second input of one of the control
gates receives the output of the first input coincidence
gate, and the output of that one of the control gates
also is supplied to one of three inputs to the first
output coincidence gate. A second pair of cross-coupled
control coincidence gates is provided and these gates
are interconnected in the same manner as the first pair
of control gates, with the second input of one of the
gates of the second pair being connected to the output
of the second input coincidence gate and the output of
that one of the control gates of the second pair is
connected to a second input of the second output gate.
The circuit is completed by a final contro7 coincidence
gate having four inputs which are obtained from each of
the afore-mentioned inputs supplied to both of the first
and second output gates. The output of this final control
coincidence gate is supplied as a third input to both
of the output coincidence gates and is supplied to the
second inputs of the other one of the gates in each of
the first and second pairs of cross-coupled coincidence
gates. The comparator is responsive to the same signal
transitions to effect the changing of states of the
various gates used in the circuits. I~hen one of the
input signals has a higher frequency than the other, the
1 1579~3
corresponding output gate provides a pulse output which
is repetitive at the lower frequency with the other
output gate providing a constant DC level output. When
both of the input signal frequencies are equal but differ
in phase, the pulse width of one of the outputs is equal
to the phase difference and occurs at the input frequency
rate, while the other output is a constant DC level.
The particular output providing the varying output signal
depends upon which of the input signals of equal frequency
and in phase, both of the output signals obtained from
the output gates are at the same constant DC level.
Although the comparator of Fig. 1 will assure a
wide capture range for a voltage controlled oscillator
of a phase-locked loop system, it has a number of dis-
advantages.
Firstly, the phase and frequency error signals arenot available independently from each other~ For example,
if the speed of an electric motor is controlled in response
to a signal derived from a phase-locked loop system using
a frequency generator connected to the motor so that the
generator can be considered as constituting a lowpass
filter and a voltage controlled oscillator, the starting
of the motor would cause the motor to overshoot or under-
shoot because of the inertia of its rotor. If a high
precision motor control is desired, a servo system would
1 1579 1 ~
be employed which generates a signal which applies brake
to the motor when it overshoots and a signal which
accelerates the motor when it undershoots. In this
instance, the comparator of Fig. 1 provides repetitive
transitions of voltage level or a constant DC level
through its output terminals. However, these signals
cannot be directly used as a switehing control signal
for purposes of acceleration and deceleration of the
motor beeause such control signal varies between two
discrete levels during the time other than the aceeleration
and deeeleration periods, and thus a lowpass filter is
required to smooth out sueh varying signals. Since the
lowpass filter ineludes a eapaeitor, the use of the
latter in large numbers is undesirable when the system
is fabrieated on an integrated-circuit ehip because the
number of connecting leads would beeome subs-tantial and
its operation would become unreliable.
- Although the eomparator of Fig. 1 has a frequency
discriminating feature, a large number of gates is required
as compared with the phase eomparator deseribed in Fig. 3
of The Bell System Teehnical Journal, Mareh 1962, pages
559-602 by C.J. Byrne, and additional gates are required
to provide a separate phase error signal.
Secondly, if a eharge pump eircuit of Fig. 2 is
connected to the output of the prior art frequency-phase
1 1~7gl~
comparator with the X and Y inputs of the charge pump
circuit being connected respectively to the X and Y
outputs of the comparator of Fig. l it appears that
the signal at the output terminal Z of the charge pump
will be at low constant DC level when the frequency of
one of the inputs to the comparator is higher than the
other and will be at high constant DC level when the
frequency relation is reversed, and deliver a repetitive
transitions of low and high voltage levels with a duty
cycle proportional to the phase difference when the
input signals are equal in frequency, thereby providing
a triple state output (There are some articles which
describe the operation of the above circuit combination
as functioning to deliver a triple state output signal~.
However, so long as the above circuit is used in an open
loop system, the output state of the terminal Z of the
charge pump circuit is one of high and low constant
DC levels, and no other signal is obtained.
More specifically, let it denote that the signals
to the input terminals A and B of Fig. l as fA and fB
respectively and assume that frequency fB is lower than
frequency fA at a point ~ in the operating characteristic
curve of Fig. 3, the output terminal of the Fig. l com-
parator is held at a constant high DC level with the
result that the drain electrodes of MOSFETs 1 and 2 of
1 15791~
Fig. 2 (which constitute an inverter circuit) become
low to cause MOSFET 3 (which constitutes a steering gate~
to turn off. At the X output of the Fig. 1 comparator
there appears a train of repetitive transitions of high
and low levels with the duty cycle related to the relative
phase of the input signals to the frequency-phase com-
parator, so that upon a low level transition at terminal
X, a p-channel enhancement MOSFET 4 is switched to an
ON state causing an output gate n-channel enhancement
MOSFET 5 to turn on so that the output termianl Z of the
charge pump circuit of Fig. 2 goes low, and upon a high
level transition at the same terminal X the MOSFET 4 is
turned off. However, because of the presence of the
constant high DC level at the Y terminal the drain electrode
of the MOSFET 3 is held at a high impedance level, so
that the carriers which have been accumulated in the
gate region of the MOSFET 5 are not di-scharged causing
it to remain in the ON state and thus the output terminal
Z is still held at the low level.
Assuming that the input frequency fB increase gradually
so that at a point fl of the coordinate axis fB of Fig. 3,
a reversal of the output states of the terminals X and Y
of Fig. 1 (that is, the X output terminal is then held
at a constant high DC level and at the Y output terminal
there appears a train of voltage level transitions when
1 ~579~
there are at least two leading edge transitions in the
input terminal B during the interval between two leading
edge transitions of the signal to the input terminal A
of Fig. 1).
Upon the presence of the constant low DC level at
the terminal Y, the p-channel MOSFET 1 is switched to
an ON state causing MOSFET 3 to turn on to allow the
carriers accumulated in the gate region of the MOSFET
5 to discharge and a p-channel MOSFET 6 to turn on so
that the output terminal Z is switched to a high DC level.
In summary, when frequency fB increases from the
point ~ until a point ~ in Fig. 3, the average signal
level ~ at both terminals X and Y adopts curves x and y
of Fig. 4a. However, the combined signal from the output
of the charge pump circuit of Fig~ 2 undergoes a rapid
change in level from low to high when frequenc fB coin-
cidense with fl, so that it is impossible to derive a
phase error signal when the frequency fB increases from
the points ~ to ~.
Conversely, when frequency fB is gradually decreased
from the point ~ the output states of the terminals X and
Y are reversed at a point f2 where frequency fB becomes
lower than frequency fA (that is, there are at least two
leading edge transitions in the input terminal A during
the interval between two ]eading edge transitions at the
l 15~91~3
input terminal B) and as a resul-t the average level of
the output signal from terminal X adopts a sawtooth
curve, while the average level of the output signal from
terminal Y is held at a constant high DC level as
illustrated in Fig. ~h.
Therefore, at the point f2 in Fig. 3 the output
level of terminal Z of Fig. 2 undergoes a rapid transition
from high to low levels, so that it is impossible to
deliver a phase error signal as the frequency fB decreases
with respect to frequency fA. It is thus appreciated
that so long as the frequency-phase comparator of Fig. 1
is used in conjunction with a charge pump circuit in an
open loop system it is impossible to derive an output
signal which represents the phase difference between two
input signals applied to the comparator.
If the combination of the above-mentioned comparator
and charge pump circuit having such open loop operating
characteristics is employed in a phase-locked loop system
as illustrated in Fig. ~, it is ascertained that the
output signal from the voltage controlled oscillator 8
contains a jitter component whose frequency is one-half
the fundamental frequency of the loop when capacitor 7
of the lowpass filter is chosen at a value close to zero,
and in this instance the output from the charge pump
circuit 9 is a phase error signal of which the frequency
1 157918
is one-half of the fundamental frequency and the average
signal level adopts a curve as indicated hy y in Fig. 3.
This phenomenon can be explained in more detail with
reference to Figs. 4a and 4b. With the output terminal
Z being at a low DC level when frequency fB corresponds
to Yl in Fig. 4a, the phase-locked loop system operates
such that the output frequency of the voltage controlled
oscillator 8 increases, so that after passing through
the frequency point fl the frequency fB reaches ~2 in
Fig. 4b whereupon the output terminal Z is driven to a
high DC level by an ou-tput signal from the Y terminal.
With the Z terminal being at the high DC level, the
phase-locked loop operates in such a way that the output
frequency of the VCO 8 decreases, and after passing through
the frequency point f2, frequency fB now returns to Yl
of Fig. 4a and the z output terminal is driven to a low
DC level by an output signal from the X terminal. This
process is repeated with the result that the output
signal from the VCO 8 contains the jitter component as
described above.
This phenomenon is not avoidable as long as the
frequency-phase comparator or charge pump circuit having
an output characteristic shown in Fig. 3 is employed to
constitute a phase-locked loop system, although an increase
in t'ne capacitive element of the lowpass filter or a high
_ 9
1 15791 8
quality lowpass filter may serve to improve the jitter
problem at the expense of -the response characteristic and the
carrier-to-noise ratio of the loop.
As far as the loop's response and carrier-to-noise
ratio are concerned, these characteristics can be improved
with an improvement over the comparator of Fig. 1 and
the charge pump circuit of Fig. 2. Since the factor
that contrlbutes to the degradation of the carrier-to-
noise ratio of the system of Fig. 5 resides in the fact
that the charge pump circuit 9 has such an output charac-
teristic as shown in Fig. 3, the use of a charge pump
circuit as shown in Fig. 6 which is disclosed in United
States Patent 3,748,589 or the use of a two resistor
network having equal resistances inserted in the source
and drain electrodes of the MOSFETs 4 and 3 of the charge
pump circuit oE Fig. 2 will result in an output charac-
teristic as shown in Fig. 7. Alternatively, by feeding
the output signals from the X and Y terminals of the
Fig. 1 comparator directly to a lowpass filter the output
characteristic x or y of Fig. 4a may be obtained and in
either case the jitter component of the signal from the
VCO 9 is drastically reducedO
However, the characteristic of Fig. 7 still falls
short of the ideal characteristic of a phase-locked loop
system as shown in Fig. 8 in terms of system response
-- 10 --
1 157918
and capture range.
United States Patent 3,069,623 discloses a frequency
comparator as shown in Fig. 9 using two set-re~et fllp-
flop circuits and two coincidence gates to provide
frequency error signal from output terminals Fl and ~2
Application of trains of input pulses as indicated by
; solid lines in Figs. 10a and 10b respectively to the
input terminals A and B of Fig. 9 will result in output
waveforms from NOR gates 10, 11, and gates 12, 13, ana
NOR gates 14, 15, as shown in solid lines in Figs. 10c
to 10h. More specifically, the presence of two or more
leading edge transitions in the pulse train applied to
terminal A during the interval between two leading edge
transitions in the pulse train applied to terminal B
causes an output pulse 13-1 to appear from the AND gate
13 causing the NOR gate 15 to go low and as a result the
i output of the NOR gate 14 undergoes a low-to-high level
transition. Conversely, the presence of two or more
leading edge transition in the pulse train applied to
terminal B during the interval between two leading edge
transitions in the pulse train applied to terminal A
results in an output pulse 12-1 from the AND gate 12 r
causing the NOR gate 14 to go low and hence the NOR gate
]5 to go high. Therefore the binary state of the bistable
device, comprised by the cross-coupled NOR gates 14 and
.,
-- 11 --
~ 157~1~
15, is an indication of which input frequency is higher
or lower than the other.
However, the frequency-phase comparator of Fig. 9
does not satisfactorily operate if the pulse duration
of the input train is exceeds a certain limit as shown
in broken lines in Figs. 10a and 10b. This will be
explained with reference to the waveforms shown in broken
lines with reference to Figs. 10a, 10b, l~e, 10f~ 10i
and 10j. Assume that NOR gates 10 and 15 are initially
at high DC level and NOR gates 11 and 14 are initially
at low DC level. Application of a positive pulse indi-
cated by broken lines al to the input terminal A will
cause NOR gate 10 to develop a low level output by the
leading edge of the applied pulse al after the delay
response time of that gate and cause NOR gate 11 to go
high at a point in time elapsed by the delay response time
of NOR gate 11, so that the high level condition at
terminal A in the presence of the high output level of
the NOR gate 11 results in an output pulse indicated by
broken lines 12-2 from the AND gate 12. Since NOR gate
14 is in the low output state at the instant the AND
gate 12 delivered the pulse 12-2, the binary state of the
NOR gate 14 and hence the NOR gate 15 remains unchanged.
However, application of an input pulse indicated by
broken lines bl to the terminal B will cause AND gate
- 12 -
A
$
-to go high producing a pulse 13-2 which in tu~n t~iggers
NOR gate 15 to go into a low output state and then NOR gate
14 to go into high output state s shown in Fig. 10i and
10j. Thereafter, the NOR gates 14 and 15 are alternately
caused to change their binary states in response to alter-
nate application of the input pulses to terminals A and B.
Therefore, the binary states of the NOR gates 14 and 15 no
longer represent the frequency difference between the two
input signals. It is apparent from the above that in order
for the circuit of Fig. 9 to operate satisfactorily the
pulse duration (the interval between the leadin~ and trail-
ing edge transitions of each input pulse) must be less than
the equivalent delay response times of two cascaded gates.
The aforesaid United States Patent 3.069.623 dis-
closes the use of a differentiator circuit for generatingtrains of short-duration input pulses. However, it is
usually difficult to generate pulses with the duration
narrower than the two-gate response time with the use of
the conventiona] RC differentiator circuit, and even
assuming that if such narrow pulses are possible there
would result in a failure to drive gates because of the
small input power.
According to the present invention there is pro-
vided a frequency comparator having first and second input
lines to which input pulses are supplied. This frequency
comparator comprises:
a first frequency detector for generating an out-
put signal in response to there being two or more
leading edge transitions of the input pulses supplied to
the first input line during the interval between two
leading edge transitions of the input pulses supplied to
the second input line;
a second frequency detector for generating an
output signal in response -to there being two or more
leading edge transitions of the input pulses supplied to
the second input line during the interval between two
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1 15791~3
leading edge transi.tions of the input pulses supplied
to the first input line;
a first bistable element arranged to be set in
response to the output signal of the first frequency de-
tector;a second bistable element arranged to be set
in response to the output signal of the second frequency
detector;
means for resetting the first and second bistable
elements in response to both of the first and second
bistable elements becoming a set condition; and
means connected to output terminals of the first
and second bistable elements for generating an output si-
gnal representative of the difference in frequency between
the input pulses supplied to the first and second input
lines.
According to the present invention there is also/
provided
,~
1 1579~8
1 a frequency-phase comparator having first and second input
2 lines to which input pulses are supplied~ comprising:
3 a phase detector for generating rectangular output
4 pulses as a function of the difference in phase between the
input pulses supplied to the first and second input lines;
6 a first frequency detector for generating an output
7 signal in response to there being two or more leading edge
8 transitions of input pulses supplied to the first input
9 line during the interval between the leading edge
transitions of successive input pulses supplied to the
11 second input line;
12 a second frequency detector for generating an output
13 signal in response to there being two or more leading edge
14 transitions of input pulses supplied to the second input
line during the interval between the leading edge
16 transitions of successive input pulses supplied to the
17 first input line;
18 a first bistable element arranged to be switched to
19 a set condition in response to the output signal of the
first frequency detector;
21 a second bistable element arranged to be switched to
22 a set condition in response to the output signal of the
23 second frequency detector;
24 means for resetting the first and second bistable
elements when the first and second bistable elements are
- 14 -
l 15791~
1 both switched to the set condition; and
2 means for combining the output pulses of the phase
3 detector with output signals from the first and second
4 bistable elements to generate a first DC level output when
the frequency of input pulses supplied to the first input
6 line is lower than the frequency of input pulses supplied
7 to the second input line, or a rectangular pulse output
a representative of the phase difference between the input
9 pulses supplied to the first and second input lines, or a
second DC level output when the frequency of input pulses
~1 suppliedto the first input line is higher than the
12 frequency of input pulses supplied to the second input
13 line.
14 Preferably the first frequency detector comprises a
third bistable element arranged to repeatedly change its
16 binary output state in response to the input pulses
17 supplied to the first and second input lines when the input
18 pulses to the first input line are supplied alternately
19 with the input pulses supplied to the second input line, a
delay means for completing the resetting operation of the
21 third bistable element after the trailing edge transition
22 of an effective input pulse supplied to the first or second
23 input line, said effective input pulse causing the third
24 bistable element to change its binary output state, and a
first coincidence gate having a first input terminal
15 -
1 15791~3
1 connected to said first input line and a second input
2 terminal connected to an output terminal of said third
3 bistable element for generating an output signal in
4 response to the leading edge transiti~n of an ineffective
input pulse supplied to said first input line, said
6 ineffective input pulse causing the binary output state of
7 said third bistable element to remain unchanged. The
8 second frequency detector preferably comprises said third
g bistable element, said delay means and a second coincidence
gate having a first input terminal connected to said second
11 input line and a second input terminal connected to an
12 output terminal of said third bistable element for
generating an output signal in response to the leading edge
14 transition of an ineffective input pulse supplied to saId
second input line, the last-mentioned ineffective pulse
16 causing the binary output state of said third bistable
17 element to remain unchanged.
18 DETAILED DESCRIPTION OF THE INVENTION
19 Referring now to Fig. ll, a first preferred
embodiment of the invention is illustrated as comprising a
21 bistable device comprised by a pair of NOR gates 20, 21
22 whicb are cross-coupled so that the output of eacb is
23 connected to an input of the other, the other input of NOR
24 gates 20, 21 being connected to input lines A and B,
respectively. The output of NOR gate 21 is further
,, ~
- 16
1 15791~
1 connected to the delayed input terminal Dl of a D-type
2 . flip-flop 22 of which the Ql output is connec~edto an input
3 of an AND gate 24 and the output of the NOR gate 20 is
4 further connected to the delayed input of a D-type
flip-flop 23 whose output is connected to another input of
6 AND gate 24. The output of ~ND gate 24 is used to reset
7 flip-flops 22 and 23 through their reset terminals Rl and
8 R2, respectively. The flip-flop 22 changes its binary
g state at the Ql output to the binary state at the delayed
input Dl in response to the leading edge transition of an
11 input pule applied to its clock input Cl connected
&~t / .,
- 16a -
~ t
9 ~ ~
to the terminal A. Similarly, the flip-flop 23 changes
its binary state of the Q2 out.put to the binary state of
thedelay~ input D2 in response to the leading edge
transition of an input applied to its clock input C2
connected to the terminal B. The flip-flop 22 constitutes
with its Dl, Cl inputs and Ql output a first frequency
difference detector to provide a high level output indi-
cating that the signal on terminal A is higher in frequency
than the signal on terminal s, while the flip-flop 23
constitutes with its D2, Cl inputs and Q2 output a second
frequency difference detector for providing a high level
output indicating that the signal on terminal B is higher
in frequency than the signal on terminal A. These D-
type flip-flops remain in the high output state by a
connection from the respective Q outputs to the respec-
tive set terminals (Sl, S2). The Ql and Q2 outputs of
the flip-flops 22 and 23 are further connected through
a NOR gate 25 to an input of an AND gate 26 which receives
as its other signal a signal from the output of the NOR
gate 21 and delivers a coincidence output to an input of
a NOR gate 27 to the other input of which is supplied a
signal from the Ql output of flip-flop 22, the output
of the NOR gate 27 being connected to an output terminal
Z of the phase-fre~uency comparator.
The operation of the comparator of Fig. 1~ is
- 17 -
1 15~8
visuali2ed with reference to the waveforms shown in Fig.
12. For purposes of illustration the waveforms of
Fig. 12 are exaggerated to show rapid changes in the
input frequencies. Assuming that the Ql and Q2 outpu-ts
are low, application of an input pulse al to the terminal
A causes the NOR gate 20 to go low and then the NOR gate
21 to go high by the leading edge transition of the
pulse al. In response to the leading edge transition
of a pulse bl on terminal B which follows the pulse al,
the NOR gate 21 is returned to the low level which causes
the NOR gate 20 to go high. The NOR gate 20 then responds
to the leading edge transition of a subsequent pulse a2
on terminal A by lowering its output level which in turn
causes the NOR gate 21 to go high. The above process
will be repeated as long as the pulses on the terminals
A and B appear alternately, so that the output of either
one of the NOR gates 20 and 21 is rectangular pulses
whose duty cycle is proportional to the difference in
phase between the two pulse trains and this phase error
signal is coupled through the A~D gate 26 when enabled
to the NOR gate 27.
Assume that the frequency of the signal on terminal
B is lowered so that a subsequent pulse a3 appears prior
to the occurrence of a pulse b2 on terminal B, the flip-
flop 22 is turned to a high DC level in response to the
- 18 -
leading edge transition of the pulse a3. This condition
will continue until the freqneucy of the signal on terminal
B becomes higher than the frequency of the signal on
terminal A. More specifically, when pulses b3 and b4
appear in succession between the leading edge transitions
of pulses a4 and a5l the flip-flop 23 changes to a high
output state in response to the leading edge transition
of the pulse b4, so that AND gate 24 provides a coincidence
output which resets the flip-flops 23 and 24 at the same
time. If the signal on terminal B becomes higher in
frequency than signal on terminal A, a pulse b5 will
cause the flip-flop 23 to go into the high state which
continues until the frequency of signal B becomes lower
than signal A. Therefore, the high DC level at one of
the outputs of the Elip-flops 22 and 23 is an indication
of the difference in frequency between the two input
pulse trains and the low DC level at both the outputs
of these flipf-flops is an indication that the input
frequencies are equal.
Since the NOR gate 25 generates a high DC level
output when both of its inputs are low, the high DC level
condition of NO~ gate 25 indicates that the two input
signals are of the same frequency and enables the AND
gate 26 to pass the phase error signal to the output
NOR gate 27 which combines the phase error signal with
~ 1579~18
the frequency error signal to produce a triple state
output. As shown in Fig. 12, when the two input signals
coincide in frequency the output from the NOR gate 27
is rectangular pulses with a duty cycle proportional
to the phase difference and when the frequency of signal
is lower than signal A the NOR gate 27 output is a low
DC level, and when the frequency of signal B is higher
than signal A, a high DC level output is delivered from
NOR gate 27. Therefore, the average output level of the
signal at the terminal Z is identical to that shown in
Fig. 8.
As seen from Fig. 12, the frequency-phase comparator
of Fig. 11 is responsive exclusively to the leading edge
transition of the input pulses, a lengthening of the
input pulses produces no changes in the logical sequence
of the comparator.
obviously, it is also possible to employ the frequency-
phase comparator of Fig. 11 in an open loop system provided
with a circuit which allows the flip-flops 22 and 23 to
be reset in response to a manual command signal.
Alternative embodiment of the comparator of
Fig. 11 is illustrated in Fig. 13 as comprising a fre-
quency and phase detector circuit which is generally
comprised of a bistable element 48, a pair of coin-
cidence gates 49 and 50, a bistable element 45
- 20 -
~ 1579~
and OR gates 51 and 52. The bistable element 48 comprises
a pair of NAND gates 46 and 47 which are so cross-coupled
that the output of each is connected to an input of the other,
the other input of NAND gates 46 and 47 being connected
to the input terminals A and B, respectively, to receive
negative going input pulses applied thereto. The NAND
gate 49 receives its inputs from the output of NAND gate
46, the input terminal A and from the output of NAND
gate 44 of the bistable element 45 and delivers its
output to an input of the NAND gate 43 whose output is
connected to an input of NAND gate 44. The NAND gate
50 takes its inputs from the output of NAND gate 47, the
input terminal B and from the output of NAND gate 43 to
deliver an output to the other input of the NAND gate
44 whose output is connected to the other input of the
NAND gate 43. The OR gate 51 takes its inputs from the
input terminal A and from the output of the NAND gate 44,
while the O~ gate 52 takes its inputs from the output of
the NAND gate 43.
The operation of the frequency and phase detector
circuit as described above is visualized with reference
to the waveforms shown in ~ig. 14. Assume that the outputs
of NAND gates 46 and 47 are low and high DC levels,
respectively, and the outputs of NAND gates 43 and 44 are
low and high DC levels, respectively. By the leading
- 21
~ 15791,¢3
1 edge transition of a negative going pulse al at the
2 input terminal B, the NAND gate 46 is switched to a high
3 output state which in turn causes NAND gate 47 to switch
4 to a low level. In response to the trailing edge tran-
sition of pulse al the NAND gate 49 is switched to a low
6 output level. Immediately following the negative edge
7 transitio~ of the output of NAND gate 49 (pulse 49-1),
8 the NAND gates 43 and 44 successively change their binary
g states, so that in response to the nega~ive edge tran-
sition of the output of NAND gate 44, NAND gate 49 re-
11 turns to the high output level, terminating the pulse
12 49-1. NAND gate 50 then goes low in response to the
13 trailing edge transition of a pulse bl, providing a pulse
14 50-1. By the leading edge transition of the pulse 50-1,
the NAND gates 44 and 43 successively change their binary
16 states to low and high output levels, respectively, and
1~ terminates the pulse 50-L. The above process will ~e
18 repeated so long as the input pulses on terminals A and
19 B occur at alternate ïntervals, and the output level of
the OR gates 51 and 52 is at a constant high DC level.
Z1 If the frequency of the signal on terminal B becomes
22 higher than the signal on terminal A so that a pulse
23 b2 appears on terminal B prior to the appearance of a
24 pulse a2 on terminal ~, the outp~t of the OR gate 52 is
switched ~
,:
~,,-~
A ,~
- 22 -
~ 1~79~ 8
to a low level producing a negative going pulse 52-1 .
because of the simultaneous presence of low level con- -
ditions to OR gate 52. It will be understood therefore
that if the frequency of the signal on terminal A becomes
higher than signal on terminal B, the output of the OR
gate 51 will be lowered.
The frequency-phase comparator of Fig. 13 further
includes a pair of bistable elements 36 and 39 and a reset
gate 50. The bistable element 36 includes a pair of
NAND gates 34 and 35 which are so cross-coupled that
the output of each is connected to an input of the other,
the other input of MAND gate 34 being connected to the output
of the OR gate 51 and the other input of NAND gate 35
being connected to the output of the reset NAND gate 40.
Likewise, the bistable element 39 includes a pair of
cross-coupled NAND gates 37 and 38, one input of the
NAND gate 37 being connected to the output of the OR
gate 52 and one input of the NAND gate 38 being connected
to the output the NAND gate 40. The NAND gate 40 takes
its inputs from the outputs of OR gates 51 and 52 and
from the outputs of NAND gates 34 and 37. The compa~ator
further includes an OR gate 41 which receives the phase
error signal from the output of the NAND gate 46 of
bistable element 48 and the output of the NAND gate 34
and delivers the phase error signal to an input of an
-- 23 -
1 15791~
AND gate 42 when the output of NAND gate 34 is low, the
AND gate 42 receiving as its other signal from the
output of the NAND gate 38 and the output of the AND
gate 42 being connected to the output terminal Z.
S The operation of the frequency-phase comparator
of Fig. 13 is fully visualized with reference to Fig. 15.
Assume that the frequency of signal on terminal A is
initially equal to the signal on terminal B and that
NAND gates 34 and 35 are initially low and high DC output
levels respectively and NAND gates 37 and 3~ are likewise
low and high DC output levels respectively. Thus, the
phase error signal from the output of NAND gate 46 is
applied through O~ gate 41 to the AND gate 42 and thence
to the output terminal z. If the signal A becomes higher
in frequency than signal B producing pulses 51-1 and
5-2 successively, the NAND gates 34 and then 35 change
their output binary s-tates by the leading edge transition
of the pulse 51-1, so that the output of the OR gate
41 and hence the output of AND gate 42 is at a constant
high DC level. When the frequency of signal A then lowers
so that a pulse 52-1 occurs at the output of the OR gate
52, the NAND gates 37 and 38 are successively caused to
change their output states by the leading edge transition
of the pulse 52-1. In response to the trailing edge
transition of the pulse 52-1, all the inputs to the reset
- 24 -
~ 1~7918
NAND gate 40 become low DC level causing it to provide
a low level output 40-1, thus resetting the NAND gates
34, 35, 37 and 38, so that OR gate 41 is again allowed
to pass the phase error signal to the AND gate 42 and
thence to the output terminal Z.
With the signal A becoming higher again in frequency
than signal B generating a pulse 51-3, the NAND gates 34
and 35 change their states to inhibit the passage of the
phase error signal to the output terminal Z so that the
latter is again held at a high DC level. With NAND gates
34 and 35 being at high and low DC output levels respec-
tively, the occurrence of a frequency difference pulse
52-2 will trigger the same circuit actions as occurred
in response to the pulse 52-1. Upon a subsequent pulse
52-3, the NAN~ gates 37 and 38 switch to high and low
output levels, respectively, and which conditions continue
in the absence of pulses from the output of OR gate 51
regardless of the presence of a subsequent pulse 52-4.
As a consequence the output of the AND gate 42 is main-
tained at a low constant DC level.
As illustrated in Fig. 16, the circuit of Fig. 13
can be modified so that the NAND gate 40 takes its inputs
only from the outputs of NAND gates 34 and 37. However,
the circuit of Fig. 13 is preferred because the logical
sequence of its operation is fully ensured against possible
- 25 -
1 15791~
1 occurrence of erratic circuit actions.
2 A modificatioD of the phase and frequency detector
3 circuit of Fig. 13 is illustrated in Fig. 17 in which
4 a pair of AND gates 55 and 56 and a pair of NAND gates
57 and 58 are provided. The AND gate 55 takes its inputs
6 from the input terminal B and the output of NAND gate
7 58 and the AND gate 56 takes its inputs from the input
8 terminal A and the output of NAND gate 57. The NAND
g gate 57 takes its input~ from the input terminal A, the
output from the AND gate 55 and from the output of NAND
1I gate 58 and delivers its output to an input of the OR
I2 gate 51 through a buffer amplifier 44, while the NAND
13 gate 58- takes its inputs from the input terminal B, the
I4 output of the AND gate 56 and from the output of the
NAND gate 57 to deliver its output to an input of the
I6 OR gate 52 ~hrough a buffer amplifier 45 and also to an
I7 input of OR gate 41 as the phase error signal as mentioned
I8 above. The buffer amplifiers 44 and 45 serve as delay
19 elements to stretch the output pulses from the OR gates
51 and 52, respecti~ely.
21 The circuits shown in Figs. 13, 16 and 17 are con-
22 structed to form frequency-phase comparators, and in
23 these circuits it is possible to constitute a frequency
24 comparator from which a triple state frequency differ-
ence signal is derived by appropriately combining ~he
26 output signals of the first and second bistable circuits.
~27 Such a frequency comparator is constructed from the
- 26 -
~ 157~8
1 circuit of Fig. 17 by modifying it so that an input to the
2 AND gate 42 is taken from an output terminal of the bistable
3 circuit 36 and the OR gate 41 i5 dispensed with, and that
4 two output terminals are provided, one from the output of
AND gate 42 and the other from an ~utput terminal of the
6 bistable circuit 39. When the two input pulses are of
7 equal frequencies, the output terminal of AND gate 42 is
8 at a hi~h voltage level, and when the frequency of input
g line A is higher than the frequency of input line B this
output terminal goes low. Since the prior art frequency-
11 phase comparator of Fig. 1 includes first and second
12 frequency detectors, a frequency comparator o~ the invention
13 can be constituted by coupling the X and Y output terminals
of Fig. 1 to the bistable devices 36 and 39 of the~modified
Fig. 17 circuit.
16 Referring now to Fig. 18, there is shown a second
17 embodiment of the present invention which comprises a
18 first bistable element or flip-flop FFl including a pair
19 of cross-coupled NOR gates 60 and 61, a second flip-flop
FF2 including a pair of cross-coupled NOR gates 64 and
21 65 and a third flip-flop FF3 including a pair of cross-
22 coupled NOR gates 68 and 69. The NOR gate 60 has its
23 one input terminal connected to an input terminal A and
24 its other input terminal connected to the output of the
NOR gate 61, and the NOR gate 61 has its one input terminal
7-
~ 15791~
connected to another input terminal B and its other
input terminal connected to the output of the NOR gate
60. The output terminals of the NOR gates 60 and 21 are
connected to phase signal output terminals Pl and P2,
respectively, and also to inputs of NOR gates 62 and 63,
respectively. The NOR gate 62 delivers its output signal
to an input of the NOR gate 64 of the second flip-flop FF2
whose output is connected on the one hand to an input
of the NOR gate 65 and on the other hand to an input of
an AND gate 67. Likewise, the NOR gate 23 delivers its
output signal to an input of the NOR gate 65 whose output
is connected on the one hand to an input of the NOR gate
6~ and on the other hand to an input of an AND gate 66.
The outputs of the NOR gates 64 and 65 are further con-
nected to an input terminal o-f NOR gates 62 and 63,
respectively. The AND gates 66 and 67 have their other
inputs connected to the input terminals A and B, respec-
tively, and deliver their outputs to an input of the
NOR gate 68 and 69, respec-tively, the output terminals
of the NOR gates 68 and ~69 being connected to frequency
signal output terminals Fl and F2, respectively.
The operation of the frequency-phase comparator of
Fig. 18 can be visuallized with re~erence to waveforms
shown in Fig. 19. Assume that the output sta-tes of the
NOR gates 60 and 64 are high and those of the NOR gates
- 28 -
, ,~ .,
1 15791~
61 and 66 are low, application of a pulse al to the input
terminal A causes the NOR gate 60 to go low by the ;~
trailing edge of the pulse al. The NOR gates 62 and 63
both remain in the low output state due to the high output
signal present at their inputs, and AND gates 66 and 67
both remain in the low output state. In response to the
trailing edge of the applied pulse al, all the inputs
to the NOR gate 62 go low to cause it to provide a high
level output which in turn causes NOR gate 64 to go low
and then NOR gate 65, causing the NOR gate 62 to return
to the low output state.
Application of a pulse bl to the terminal B causes
the NOR gate 61 to go low in response to the leading
edge of the pulse bl, causing the NOR gate 60 to switch
to a high level output. In response to the trailing
edge of the pulse bl, all the inputs to the NOR gate 63
are low to cause it to switch to a high output state
which in turn causes the NOR gate 65 to go low and the
NOR gate 64 to go high, so that NOR gate 63 is switched
to the low output level. So long as the input pulses
on terminals A and B occur alternately, the first flip-
flop FFl is caused to change its binary state and as
a result the outputs of the AND gates 66 and 67 are
held at a constant low DC level.
If there are two leading edge transitions of pulses
- 29 -
,~
~ 1~7~1~
b2 and b3 between two leading edge transitions of pulses
a2 and a3, the pulse b3 will cause the AND gate 67 to
provide a positive pulse 67-1. Similarly, if there are
two leading edge transitions of pulses a4 and a5 between
two leading edge transitions of pulses b4 and b5, the
AND gate 66 will be caused to provide a positive pulse
66-1 by the pulse a5. Therefore, the output of the NOR
gate 69 becomes a low DC level in response to the pulse
67-1 causing the NOR gate 68 to become a high output
DC level, and these output states of NOR gates 69 and
68 continue until the occurrence of the pulse 66-1.
The signals on output terminals Pl and P2 are thus
rectangular pulses with a duty cycle being proportional
to the difference in phase between the input frequency
signals to terminals A and B, while the signals on output
terminals Fl and F2 are a constant DC level signifying
the difference in frequency between said input signals.
As seen from Fig. 19, the rectangular pulses derived
from the second flip-flop FF2 can also be used as the
~0 phase error signal, so t~at the terminals Pl and P2 can
be connected to the output of the NOR gates 64 and 65,
respectively, as shown in dotted lines 64', 65' instead
of being connected to the outputs of the NOR gates 60
and 61.
Since the first flip-flop FFl is responsive to the
- 30 -
,,. ,.,, .,~
~ 15791~
leading edge transition of the input pulses to the
terminals A and B, while the second flip-flop FF2 is
responsive to the trailing edge transitions of the
applied input pulses so as to ensure that AND gates 66
and 67 deliver output pulses only in response to the
leading edge of an input pulse, the operation of the
frequency-phase comparator of Fig. 18 is logically
ensured against a malfunction caused by the leng-
thening of input pulses. Furthermore, the advantage
of the present invention is that phase and frequency
error signals can be derived independently from the
terminals Pl, P2 and Fl, F2 as shown in Fig. 18, since,
when the fre~uency-phase comparator of Fig. 18 is used
in a phase-locked loop system for purposes of controlling
the speed of a motor, these error signals can be directly
employed for acceleration or deceleration of the motor,
which could otherwise be realized only with the use of a
waveform filtering circuit if the prior art comparator
of Fig. 1 is employed tending the system to be unsuitable
for integrated circuit fabrication.
A modification of the circuit of Fig. 1~ is illustrated
in Fig. 20 in which NOR gates 72 and 73 are so cross-
coupled that the output of each is connected to an input
of the other to form a first bistable element. OR gates
70 and 71 have one of their inputs connected to the input
- 31 -
~'
.L
1 157918
terminals B and A, respectively, and the other input
connected to the output of NOR gate 73 and 72, respec-
tively. The NOR gate 72 further takes its input from
the output of OR gate 70 and from the input terminal A,
and the NOR gate 73 further takes its inputs from the
output of OR gate 71 and from the input terminal s. An
AND gate 74 receives its inputs from the output of NOR
gate 72 and from the input terminal A, and an AND gate
74 takes its inputs from the output of NOR gate 73 and
from the input terminal B. A second bistable element
is provided which comprises a pair of cross-coupled NOR
gates 76 and 77 and receives its inputs from the outputs
of AND gates 74 and 7S to deliver frequency error signals
to output terminals Fl and F2. The first bistable element
delivers phase error signals to output terminals Pl and
P2.
Referring to Fiy. 21, it is assumed that NOR gates
72 and 73 are low and high. The occurrence of a pulse
al at the input terminal A causes OR gate 71 to go high
causing NOR gate 73 to g`o low, which in turn causes OR
gate 70 to go low. These binary states are reversed
in response to the leading edge of a pulse bl on terminal
B, and these processes will be repeated so long as the
pulses on terminals A and B appear alternately. If pulses
b2 and b3 appear between the leading edge transitiolls of
- 32 -
,,~,,.
l 15791~
pulses a2 and a3, AND gate 75 is activated in response
to the leading edye of the pulse b3 providing a pulse
75-1 which is terminated by the trailing edge transition
of NOR gate 73. Responsive to the pulse 75-1 the NOR
S gate of the second bistable element 77 is switched to a
low output level turning the NOR gate 76 to a high output
level. The binary state of the second bistable element
is reversed to the original state in response to a
pulse 74-1 which is generated by the leading edge tran-
sition of a pulse a5 subsequent to pulse a4 which occursprior to a pulse bS. Therefore, the output of the second
bistable device is a constant DC level indicating the
frequency difference el-ror, while the output of the first
bistable device is rectangular pulses indicating the
phase error. The phase error signal is also available
from the output of the OR gates 70 and 71 as indicated
by connections 70' and 71' as is seen from Fig. 20..
To ensure the generation of pulses from the AND
ga-tes 74 and 75, buffer amplifiers 80 and 81 may be
connected to inputs of AND gates 74 and 75, respectively,
as a delay element to introduce a delay to the outputs
of NO~ gates 72 and 73, respectively, as shown in Fig. 22.
- 33 -
~ 15791~ ~
SUPPLEMENTARY ~IS~LOSURE
The following disclosure is given to exemplify a
further modification applicable to the present in~ention A
In the drawings accompanying this disclosure:
Fig 23 is:a diagram of.a further modification of
the embodiment of Fig. ll;:and
Fig. 24 is a waveform diagram associated with the
Fig. 23 embodiment.
Fig. 23 shows a further modification of the embo-
diment of Fig 11 shown as comprised of a frequency compara-
tor (which can easily be modified to function as:a frequen-
cy-phase comparator). The comparator of Fig 23 includes a
first frequency detector 90 which generates an output si-
gnal in response to there being two or more leading edge
transitions of input pulses supplied to the input line B
during the interval between the leading edge transitions
of the input pulses successively supplied to the input line
A, and a second frequency detector 91 which generates an
output signal in response to there being two or more leading
edge txansitions of input pulses supplied to the input line
A during the interval between the leading edge transitions
of the input pulses successively supplied to the input line
B. A first bistable circuit 92 is connected to the output
of detector 90 to be set in response to an output signal
therefrom. To the output of the detector 91 is connected
a second bistable circuit 93 which is set in response to
an output signal from the detector 91. To the output of
the first bistable circuit 92 is coupled a delay circuit
94 which supplies a delayed signal to an input of an AND
gate 95 which constitutes with the delay circuit 94 a first
resetting circuit 96. This resetting circuit functions to
reset the second bistabl.e circuit 93 in resp
- 34 -
9~ ,
1 157~1~
1 a~ output signal from the first frequency detector 90 beinq
2 generated again after the first bistable circuit 92 is
3 switched to the set condition~ A second resetting circuit
4 99 of a similar construction to the resetting circuit 96
is included which comprises a delay circuit 97 connected
6 to the output of the second bistable circuit 93 to apply
7 its output to an input o~ an AND gate 98. The second
8 resetting circuit 99 fu~ctions to reset the first
g bistable circuit 92 in response to an output signal
from the second frequency detector 9l which is gener-
11 ated again after the second bistable circuit 93 is
12 switched to the set condition.
13 The comDlementary and true output terminals Q1 and
14 Q2 of the first and second bistable circuits 92 and 93,
respectively, are connected together through respecti~e
16 coupling resistors lO0 and lOl to the output terminal Z
17 at which there appears an analog voltage signal of the
18 combined outputs of- the bistable circuits 92 and 93
19 The operation of the circuit of Fig. 23 may be more
fully understood with reference to waveforms shown in
21 Fig. 24~ Assume that the output states of the first and
22 second bistable circuits 92, 93 are both at high voltage
23 level. An output pulse a from the first frequency
24 detector 90 will cause the AND gate 95 to switch to a
high voltage level in response to the leading edge
- 35 -
1 15791~
1 transition of the pulse a and the second bistable circuit
2 93 is reset to cause its Q2 output to go low. The AND
3 95 will be again caused to generate a reset pulse for
4 the second bistable circuit 93 in response to the next
pulse b, but the low output state of the bistable circuit
6 93 remains unchanged. A pulse c from the second frequency
7 detector 9l will cause the second bistable circuit 93
8 to switch to a set condition providing a high voltage
g signal at its Q2 output terminal. secause of the delay
interval introduced by the delay circuit 97, the input
11 conditions of the AND gate 98 are not satisfied, so that
12 it continues to deliver a low voltage output. The second
13 bistable circuit 93 will be reset again in response to a
14 pulse d from the first frequency detector 90 and set in
response to a pulse e from the second frequency detector
16 91. A pulse f, which is delivered rom the second fre-
17 quency detector 9l in succession to the previous pulse e
18 before the first frequency detector 90 delivers an output
19 pulse, will cause to AND gate 98 to go high and reset the
first bistable 92. The next pulse ~ from the second fre-
21 quency detector 91 will only cause the AND gate 98 to
22 generate a xeset pulse without causing the bistable 92
23 to change its binary state
24 A pulse h fro~ the first frequency detector 90 will
set the first bistable 92 and a pulse i from the second
.~.;
- 36 -
1 15791~
1 frequency detector 9l will reset it again. The first
2 and second bistable circuits 92 and 93 will be suces-
3 sively caused to cha~ge t~eir binary states in response
4 to pulses i and k delivered successively from the first
detector 90. The output states of the first and second
6 bistable circuits remain unchanged in the presence of a
7 next pulse Q delivered from the first detector 90 in
8 succession to the previous pulses i and k.
g Therefore, the combined waveform of the complementary
output of bistable 92 and the true output of-bistable 93
11 which appears at the terminal Z is an analog voltage which
12 assumes one of three DC levels depending on the frequency
13 difference between the input pulses applied to terminals
14 A and B. More specifically, when the frequency of pulses
on terminal A is higher than the pulses on terminal B,
16 the combined output level is a low DC level, and when
17 the two frequencies are equal the combined output takes
18 on a medium DC level. When the frequency of pulses on
19 terminal A is lower than the pulses on terminal B, the
combined output is a high DC level.
. .~
~,
