Note: Descriptions are shown in the official language in which they were submitted.
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BACKG~OU~D OF THE INVENTION
This invention relates to the processing of microcircuits
in general and more particularly to an automatic mask alignment
system for use in apparatus in which an image on a mask
is projected on to a substrate coated with a resist in order
to expose the resist for further processing of the substrate.
In the making of micro-circuits the general process
followed is that of generating an oxide film on the scmi-
conductor substrate; coating the oxide film with a photoresist
and then illuminating the photoresist through a mask ~o expose
selected portions of the resist. After exposure, the photo-
resist is developed creating a pattern corresponding to either
the exposed or unexposed portions depending on the type of
photoresist. The remaining photoresist forms a protective
cover for the oxide layer which is then etched, for example, in
hydrofluoric acid, to expose the layer below the oxide film,
whereupon impurities can be infused into the substrate for
doping purposes to form transistors and the like. Once this
is done, the process may be repeated numerous times with
additional oxide films formed, more resist deposited, the resist
exposed, developed, and the oxide film etched with further
steps of doping or depositing carried out.
The exposure of the photoresist is carried out by using masks
which are prepared for that purpose. Separate masks are used
for each of the successive steps. If everything is to appear in
the proper place on the micro-circuit a high degree of alignment
is necessary between steps.
Typically, the su~strate which is exposed is in the f~rm of
a wafer which will contain thereon a plurality of identical
chips or micro-circuits. The mask, similarly will contain
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numerous identical patterns, one for each of the chips. The
mask is made by taking the pattern to be imaged on each one
of the micro-circuits and forming it numerous times following
a step and repeat process. Thus, the same pattern is found
- across the rows and columns of the mask.
One system which is used in carrying out exposure of
wafers in this manner is disclosed in detail in U.S. Patents
4,011,011 issued March 8, 1977 to Offner, et al.; 4,006,645
issued February 8~ 1977 to Newell; for example. The system
disclosed therein is one which utilizes manual alignment,
- with the operator viewing the mask and wafer through an op-
iical system~ The system includes a fine alignment system
and coarse alignment system along with the projection system.
The actual element for alignment is carried out by the de-
vice disclosed in U.S. Patent 4,006,645.
Proper alignment requires the ability to align at least
two targets, one on each side of a wafer. This is accomp-
lished with the viewing system of the type illustrated on
figure 4 of U.S. Patent 4,011,011 in which the viewing field
~0 contains two images derived from the wafer and mask. This
then requires that alignment targets be printed on the mask
for this purpose.
The first mask imaged on the wafer does not require
alignment since there is no previous pattern on which to
align. For subsequent automatic alignment, it is necessary
to print targets on at least two sites on the wafer. A~ter
processing is carried out, these targets are present and then
are used in the next processing step to accurately align the
wafer with the next masks. When aliynment is done manually,
the nature of the targets is not particularly critical; how-
ever, if this `alignment is to be carried out automatically,
certain problems arise. In automatic alignment, it has gen-
erally been the practice to make large targets, i.e., targets
which take up
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the space of two or more micro-circuits. This requires that
during the step-and-repeat process of making the mask, the
micro-circuit pattern be interrupted in at least two places
so as to include the large alignment target patterns. Since
the relative position of the circuit and alignment pat-terns
can change from one rnask to another, alignment of the alignment
patte ns can lead to misalignment of the circuit patterns.
Furthermore, at least two spaces which would normally yield
micro-circuits are lost to the target.
Thus the need for an impro~ed automatic alignment
system which avoids these difficulties becomes evident.
SUMMAR~ OF THE INVENTION
The present invention provides a solution to this
problem. In its broadest aspect, the present invention com-
prises utilizing a small target, i~e., a target of such a size
that it can be printed on a single micro-circuit chip itself
without interfering with the normal lines thereon. In order
that the target can be reliably detected, the target has a
diamond shape and consists only of lines at an angle to the
chip edges. Since the lines made on the micro-circuit for
processing purposes are normally horizontal and vertical, the
target is thus distinguishable from the normal micro-circuit
photography. Alignment is carried out by initially exposing
a larger diamond on the mirco-circuit and centering it around
a small diamond contained on the next mask. It is sometimes
preferred that the new wafer targets be printed each time there
is an exposure. This will avoid the loss of resolution which
can occur as additional layers of silicon oxide are formed over
the targets and will also prevent confusion caused by the mask
target exposed after the previous alignment. Furthermore, al-
though the target may be a solid or filled-in diamond, a
hollow target is preferable. Furthermoxe, it is
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preferred that the diamond not be complete but tha-t each of
the diamonds forming the mask target and the wafer target have
missing sections in order to permit easier identification.
Through the use of such a target, various detection schemes
are possible.
A method and apparatus for accurately detecting these
patterns on the wafer are claimed in our co-pending Canadian
Patent Application No. 345,271 of which this application is a
divisional.
Although it is only necessary that the targets be pre-
sent on two sites of the wafer, it is preferred, in order not
to have changed images in the step and repeat camera, that the
target be printed on each chip. The target being there does
no harm even if it is not used. Alternatively, the targets,
rather than being somewhere inside the chip, can be in the
sections of the wafer between chips. Normally these areas are
masked out but it is no problem to include the targets therein.
Such is possible only by using the small target of the present
invention.
In broad terms, the system for detecting the presence
of targets includes a TV camera using a very sensitive vidicon,
a circuit which detects the presence of a target line in the
video signal, a digitizer which digitizes those locations r
i.e., digitizes the x and y locations thereof, and includes
a memory buffer, and a micro-computer system which receives
the digitized data and from this data locates diagonal lines,
determines the end points of the diagonal lines, reconstructs
the diamond and therefrom determines alignment. If alignment
is not within preset tolerances, the micro-computer system
provides outputs to the align~ent motor drive, the alignment drive being
as described in the afore~entioned U.S. Patent 4,006,645.
Also disclosed is a digital preprocessor to aid in filtering out
data which is not associated with diagonal lines.
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BRIEr DESCRIP~ION OF THE DRAWING5
FlG 1 is a view c~mparing the large ~cale t~rget ~f the
prior art with the small scale target of the present invention.
FIG. 2 is a view of a first embodiment of the alignment
target of the present invention.
YIG. 3 is a view of a second embodiment of a patterm
according to the present invention.
FIG. 4 is a view of a hollQw pattern according to the present
invention.
~10 FIG. 5 is a basi~ block diagram of a system for detecting the
patterns of FIGS. 2 and 3~
; FI~. 6 is a diagram illustrating the principle of position
detecting used in the present invention.
FIG. 7 is a diagram of a circuit for aetecting line position.
FIG. 8 is a block diagram of a preprocessor unit using
diyital shift registers.
FIG. 9 is a schematic diagxam of a digital corxelator for
target lines having a 1.~:1 vertical to horizontal digitization
ratio.
FIG. 10 is a schematic diagram of a digitizer and memory
buffer.
DETAILED DESCRIPTION OE' THE INVENTION
As previously indicatea, the essential feature of the present
invention lies in the use of a small target and in the use of
a target which is diamond shaped. This is best illustrated by
~ FIG. 1 which is a comparison of the small and large target
approaches. A wafer 11 is shown broken down into a plurality
of squares, each s~uare.representing a micro~circuitO As
indicated previously, there is a need for a target on at least
two sites on the wafer. Tnus, there are shown conventional
target arrays 13 on each side of the wafer 11. The target
axray 13 on the left hand side of the wafer is shown in an
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enlarged presen~atiO~. NOte that the tar~e~ array 13 consists
of a rectangular block containing three separate targets 15
and that each array displaces one integrated circuit on the wafer.
In accordance wi~h the present inventi~n, however, small targets
are used. Such a small target is shown within the enlarged
view of the circuit 17. Note that a much smaller area of the
wafer 11 is circled and includes parts of four micro-circuits.
Visible on the micro-circuitsare typical bonding pads 19 which
are typicall~ 5 mils square. Shown is an unused alignment target
10 21 and an alignment ~arget 23 which has been previously used.
Note that the alignment targets are printed on each of the
sections or micro-circuits 25 on the wafex. Thus they are between
other components ~n the wafer and do not require the displacement
of a pair of integrated circuits therefore resulting in a
greater yield.
FIG. 2 illustrates a first embodiment of the alignment
pattern of the present invention. Each time a pattern for
processing is printed on the wafer for each microcircuit,
an alignment pat~ern 27 is also prin~ed. On the next succeeding
mask~ an alignment pattern 23 is provided of the same diamond
shape and in the corresponding position as the pattern 27, but
of smaller size. When the two are aligned, they take the
relative posltion shown by the overall diagram 30. The mask
may, of course, in addition to containing a smaller pattern
28, contain somewhere else one or more copies of pattern 31
. which will be available for the next steps in the process.
Although the closed diamonds of FIG. 2 may be used, it
is preferred that the patterns shown on FIG. 3 be used.
In these patterns, the diamond 27 is replaced by a pattern
which has a diamond outline but in which the corners are cut
away. Thus, on each of the sides of the diamon~ there only
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remains a segment 31. Similarly, with the small diamond only
the segments 33 xem~in so that the resulting pattern 34 is an
sh~wn on the figure when alignment takes place. The dimensions
of the targets 31 and 33 can be varied to suit the resolution
of the imaging system and the field of the viewing system and
might typically be as given on FIG 3. Furthermore, although
the pattern shown on FIGS. 2 and 3 are hollow patterns which
have certain advantages, it is possible to use solid patterns.
FIG~ 4 illustrates hoth target types.
As noted, it is through the use of such patterns that
automatic alignment is possible and thus, in its broadest
aspects the presen~ invention comprises the use of such patterns
for alignment. ~ow~ver, another aspect of the invention is
the manner in which these patterns are used to carry out
automatic alignment. This will now be explained.
FIG. 5 shows the basic block diagram of the sy~tem
of the pre~ent invention. In conventional fashion the wafer
is disposed on a stage 41. Though the optical s~stem of the
`i aforementioned patent, the wafer 41 and mask 43 can both be
20 observed. A tele~ision camera is installed to view two portions
of the mask and wafer through a split field optical syst~m using
dark field illumination. Viewing the targets under dark
field illumination results in edges providing consistent bright
images on a dark background due to the topography inherent in
IC fabrication. This type of ill~nination also allows for
e~ficient use of a technigue known as video integration to
increase the video signal to noise ratio. Video integration is
implemented by blanking the electron readout beam in the vidicon
image tube for a desired number of frames allowing the TV
image in the form of a photocathode charge or conductivity
difference to build up with time resulting in an increased
video signal when the vidicon target is first allowed to be
sampled.
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Initial mechanical positioning is carried out by the wafer
loading mechanism to bring the mask and wafer into general
alignment. The television camera scans over the portions of
the mask and waf~r in the viewing field and provides its video
output to a line position detector 47 during one frame. The
detector, in a manner to be more fully described below, detects
the presence of the lines on the alignment patterns. Upon
detection, these positions are digitized and temporarily
stored in a memory buffer 49 and then in a microcomputer
memory. The digitized information is then available to a
- microcomputer 51 in which computations are carried out in
order to determine whether or not the mask pattern is aligned
with the wafer pattern. Depending on the degree of misalignment,
outputs are provided to an alignment motor drive 53 which
drives the wafer staye, in the manner described in the afore- ;
mentioned U.S. Patent 4,006,645.
; The line position 47 detector, a~ the television camera
scans horizontally will detect not only diagonal edges of the
pattern but will tend to ~lso detect any vertical lines.
The principle on which it operates is illustrated by FIG. 6.
The video signal 55 from a typical hollow tar~et line 56
illuminated by dark field illumination has a characteristic
voltage versus time wave shape 59 as shown in FIG. 6 as VI.
~ Detection is carried out as follows:
1 1. A second signal V2 is derived fro~ Vl by delaying it
for a time ~ T.
2. The crossover point 61 when V2 becomes greatex than Vl,
is used to generate a signal (V out) which causes the contents
of a counter to be stored in memory.
3. The output si~nal (Vout) is qualified by requiring that
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the signal V2 be above a threshold voltage VT (i.e., noise level).
~ he resulting p~sitive gDi~g edge ~ the VOUt pulse 63
will be ~enerated at a time delayed by a constant amount after
the center of the waveform is encountered. This constant delay
is equal to one half of the t~tal delay line time a t. The
optimum time delay~tvaries for different target line-widths
but small variations in line sizes ~r edge profiles can be
readily accommodated by a fixed time delay. FXG. 7 shows a
schematic diagram of ~he line position detector.
Figure 10 ~hows a way in which the edge position signal
Vout is converted to a number corresponding to its hor~zontal
position which may be stored in ~he microcomputer memory.
Digitization of the horizontal position of a line or edge
is accomplishea by starting a counter at the beginning of each
horizontal scan line and incrementing it at a 10 MHZ rate.
When an edge is detected, its position is stored in the micro-
computer memory as an eight bit word corresponaing to the count
when the edge was detected. The 10 M~2 counting rate permits
each horizontal TV line to be divided into 2 acguisition zone~
each having 256 possible line positions. Each line has 16 words
of comp,u,ter memory reservea allowing as many as 15 eage positions,
and a zero word designating ena of valid data. If one uses 170
~, l'ines in each acquisition zone, a total of 16 by 170 or 27~0 woras
of memory are required for each acquisition zone.
' -At the end of the digitizing, there will be stored in a
memory associated with the micro-computer the locations of each
of the edge crossings. The magnitude of the word in memory
represents the horizontal position coordinate; ~nd the memory
location indicates the vertical position coordinate.
A computer program for the microprocessor needed to ca ~ out the
identification of t ~ ets and a positioning of the wafer sta~e to bring the ~gets
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into alignment, basically does the following:
:
1. Searches through the raw data stored in the memory
looking for diagonal lines. All diag~nal lines having three ox
more consecutive points are listed.
2. The endpoints and y-intercepts of each diagonal line
are computed.
3. Close-by, like slope diagonal lines are combined;
thus reducing the number of endpoints and y intercepts~
~10 .4. The known mask target size is used to predict y-intercept
- spacing for mask targets. Y-intercept spacings from like-slope
line pairs corresponding to the mask spacing are listed and
. .
a mid-point calculated for each pair. If more than one line
pair is found for each slope, the lines with the largest
number of data points are used.
` ~ 5~ From the midpoints of oppositely sloping diagonal
pairs, the center of the mask target is computed.
6. The same procedure is used to find the wafer target
center and the ~ask and wafer target separation is cal~ulated~
7. The information from the other side of the split
field viewing system is used to find its mask and wafer target
separation in the same fashion.
8. The separations from both viel~ing sites are used to
compute the worst alignment error.
9. If the error is greater than the predetermined limit,
e.g., l.O~m, an output is provided to drive the wafer stage
to correct the misalignment and the procedures to put another
alignment picture into mem~ry and compute the alignment error
are repeated. If the error is under the limit, the exposure is
allowed to take place.
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In order t~ further reduce computer memory storage require-
ments, further processing of edge positio~ data before storage
in memory is possi~le. FIG. 9 illustrates one possibility.
In this scheme, a plurality of 256 bit shift registers 101
are provided and connected such that the output of the first
shift register 101 is the input to the first stage of the
second shift register and so forth. Each shift register stores
one line of data. Outputs are taken from the first stage of
the first shift register 101, the second stage of the second
shift 101 and the third stage of the third shift register
101 to an AND gate 103. A 10 MHZ output from a clock provides
the shift command into the shift registers. The data input
is the output of the line position detector 47O Thus, this
data is sampled and loaded into the register and continually
shifted therethrough. Each shift register 101 will contain
one line of data in digital form, "ls" indicating narrow lines
or edges and the absence of a "1" indicating the absence of
narrow lines or edges. If a diagonal line is present, a diagonal
of "ls" should appear as shown on the figure. When this
occurs, a diagonal line, which normally only appears in the
alignment target geometries has been detected and an output from
the AND gAte 103 occurs, which output can then be stored in
memory. In other words, there will be storea in memory a value
- corresponding to the horizontal location of the "1" which has
been identified as belonging to a diagonal. A slightly
different arrangement of the AND gate inputs is required to
detect lines or edges of opposite slope.
If the horizontal digitization rate and the vextical
spacing between the readout lines in the TV camera do not
correspond to the same distance on the TV picture, then
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some modification of the above scheme is necessary. One
possibility is simply to choose a diagonal line having a
slope so that the intersection by two adjacent horizontal
readout lines corresponds to an integral number of digitization
spaces (equal vertical to horizontal digitization ratio). This
results in a digitization error of half of the digi~ization
increment. (If the increment is one micron and the line is
assumed to lie in the middle of the increment but lies instead
at the edge then the error is half the increment.) The digi-
tization error can be reduced by choosing a target line slope
and a read~ut and aigitization scheme that does not possess
an integral number of digitization spaces between adjacent
horizontal TV readout lines. For example, if 45 target lines
are used with a digitization scheme having a 1.5 micron space
between horizontal lines and a 1.0 micron digitization increment
along each line (1.5:1 vertical to horizontal digitization ratio),
then the worst error due to digitlzation will be 0.25 micron
averaged ~ver two adjacent lines. With this scheme, the
correlator would have to include two possible edge locations
on every other line. This is illustrated in Figure 9.
A schematic of the digitizer and memory buffer is shown
in Figure 10. The vertical and horizontal synchronization
pulses generated by the TV camera are used by the memory
address logic to determine when the TV signal being read
out is contained in either of the two acquistion z~nes.
Typically, each acquisition zone is a rectangular area spanning
most of one or the other halves of the split viewing field.
Once the TV camera readout beam crosses the edge of an acquisition
zone, an edge position counter 105 is incremented at a 10
megahertz rate by a clock 106 and an edge counter 107 is enabled.
A signal indicating the presence of a target edge causes the
count in the position counter 105 to be held in a latch 108
and the edge counter 107 to be incremented, I~ the nu,mber in
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the edge counter 107 is less than 16, then the memory address
logic 109 causes the number in the latch 108 to be stored in
the computer memory 110 at an address which is offset by 16
times the hori20ntal line number plus the edge counter number.
If the computer memory is sufficiently fast, the line edge
position can be stored directly without using a fast buffer
memory.
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