Note: Descriptions are shown in the official language in which they were submitted.
1 3 ~2254
MEI'HOD AND APPARAIIJS FOR DErrP.CIING THE CARRIER ONLY SIGNAL IN AN EQUALIZER
Back~round of the Invention
The subject invention relates to data communication
equalizers and more particularly to automatiç adaptive
equalizers utilized in high speed data modems. The equalization
scheme of the subject invention is particularly adapted to
implementation under microprocessor control and provides a
1! ~ 6225~
, method and apparatus for performing highly accurate, ultra-fast
2 e~ualization by operation on the channel response to only a
3 single transmitted test impulse,
4 The equalizer of the invention is particularly ~lted
to high speed polling applications. In such applications, it is
6 customary to rapidly successively address 2 number of remote
7 stations, for example in different cities, from a cen'~al site.
8 Tran~ssion from each remote statio~ inv~lv~ ~ n~w transmission
9 line such that equalization must be re-established each time a
new remo~e site is polled. Therefore, it is hig~ly desirable
11 to shor~en the equalization time as much as possib1e in order
12 to increase data throughput.
13 Many prior art e~ualizers have been relatively slo~
14 to equalize when first connected to a new transmi'ssion line and
have thus wasted valuable data throughput time. Typically,
16 ~.any time consuming incremental adjustments of the equalizer
17 tzi~s are required during analysis of a relatively long period of
18 random data or a training pattern containing numerous test pulses.
19 One prior art system proposes to equalize on 2 sincle
transmit~ed test pulse but act~ally requires a multiplicity of
21 test pulses. This sys~em is disclosed in the Bell System ,
22 Technical ~ournal, Vol. 50, No. 6 pp. l969-2041, in an article
23 by Robert W. Chang titled "A New Equalizer Structur~ for Fast
24 Start Up Digital Communications.~ '
Another prior art system, disclosed in U.S. Patent No.
26 3,962,637 issued to David Motley et al, achieves equalization
27 during the duration of the response to two transmitted impulses
281 utilizing a technique which approxi~ates the well-~nown zero-
29 forcing scheme and does not employ correlation of signal samples.
30~,
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1 1 B2254
Equali~ation in this system requires an extra impulse to adjust
the phase of the line signal so that proper sampling will occur.
Because this system uses a zero-forcing scheme and then only an
approximation thereto, it will not work on a highly distorted
line or when high precision is necessary. While the Motley
system suggests itself for operation at 4800 bps, it is not
suitable for operation at the much higher data rate of 9600 bps
at which the equalizer of the subject invention can operate.
In IEEE Txansactions On Communications, Vol. Com-23,
la No. 6, June 1975, P. Butler et al disclose a method permitting
a direct solution of a matrix equation in real variables
describing the sQttingS of cqualizer tap constants in a single
sideband system. This technique requires a much longer training
sequence to reach ~n estimation of~reasonable accuracy than
that proposed by the subject invention~ Moreover, the method
will not solve a complex variable matrix equation. Accordingly
the approach canno~ be used to ach~eve equalization in a double
sideband system as will the subject in~ention.
It is an object of the present invention to obviate or mitigate
the above said disadvantages.
According to the present invention there is provided
in a data modem receiver supplied with a received signal including
; a carrier-only signal, apparatus for detecting the carrier-only
signal comprising:
means for deriving a series of angles from the
received signal;
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means for forming a plurality of difference values
from a series of angles derived from the carrier-only signal
by said means for deriving; and
means for testing said difference values to determine
whether a plurality of said difference va:Lues are within a
selected first range and for producing a signal indicating
said carrier signal is present upon detec~ion of a select~ed
number of said difference values be;ng within said first range.
Also according to the present invention there is
provided a method for achieving initial start-up of a data
modem receiver including the steps of:
sending a training pattern including a carrier-only
signal;
deriving a series of angles from a received form of
said carrier-only signal;
~ orming a first set of difference values using said
angles;
testing a plurality of said dlfference values to
determine whether a first selected number of said difference
values are within a first selected range; and
producing a signal indicating said carrier-only
signal is present upon detection of said first selected number
of difference values within said first range.
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3 ~2254
The apparatus of the invention has the major advantage
of enabling precise equalization constant calculations from the
samples in a minim~l amount of time
despit~ wide variations in the distortion induced
by the medium over which the received impulse is transmitted.
Utilizing the invention, an equalizer has been constructed which
can achieve initial aqualization in a time on the order of 30
milliseconds at a data rate of 9500 bits per second. This is
nearly five times aster than equalization can be achieved by
presently commercially available systems~ In the preferred
embodiment of the invention, eguali~ation is pexformed in response
to a single received impulse, and an important feature of the
preferred apparatus is provision of a means to de~ermine the
optimum points at which to sample~the impulse response prior to
receiving it. While equalization is performed using in-phase
and quadrature phase impulse respOnse signals at baseband
frequencies in the preferxed embodiment, such signals may be
derived at passband or other ~ranslated frequencies.
BRIEF ~ESCRIPTION OF THE DRAWINGS
The preferred embodiment and best mode presently
contemplated fsr implementing the iUst summarized invention will
~ now be described in detail in conj~nction withthedrawings of which:j
: . . '
~ .
2 ~ ~ ~
1 ¦ Fig. lA illustrates the received signal utilized by
2 ¦ the equalizer of -the preferred embodimen~.
3 ¦ Fig. lB and lC illustrate ~wo phasP cOmpQnentS in
: 4 ¦ relative quadrature produced from the received signal on the same
5 ¦ time scale as Fig. lA.
6 ¦ Fig. 2 is a schematic diagram useful in illustrating
7 ¦ the structure and operation of ~he equalizer o~ the preferred
¦ 8 ¦ embodiment~
1 9 ¦ Fig. 3 is a schematic diagram illustrating the digital
~ 10 ¦ processo~ utilized in the preferred embodiment o ~he in~ention.
11 I
12 I . .
6 ~
17 I .
18 I .
~9 I
~20 I .
21
22
1 23
~; 2
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271 . I
28 .
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l 11 B2~$4
Fig. 4 is a flow diagram illustrating the overall
2 structure and operation utilized to properly time the sampling
3 of the receivedc1gnal in the preferred embodiment.
4 Fig. 5 is a detailed flow diagram illustrating the
5 method and apparatus utilized to detect the presence of the
6 received signal in the prcferred embodiment.
7 Fig. 6 is a detailed flow dlagram illustrating the
8 method and apparatus employed in the preferred embodiment
9 to properly set the points for sampling the received signal.
Fig. 7 is a detailed flow diagram illustrating the
11 method and apparatus employed in the preferred embodiment
12 to determine the equalizer tap constant settings from the samples
13 of the received signal.
14 Fig. 8 is a contin~ation of the ~low of Fig. 7.
Fig. 9 illustrates one technigue suitable for
16 generating phase quadrature signals for use in the subject
17 invention.
18 Fig. l0 illustrates an alternative technique for
19 generating phase quadrature signals for use in the subject
invention.
21 Fig. ll illustrates an alternative technique for
22 generating phase quadrature signals for use in the subject
23 invention.
24 ETAI~ED_DESCRIPTION OF THE PREFERRE~ E~BO~IMENT
The automatic adaptive equalizer of the invention
26 may be conveniently introduced in conjunction with the training
27 pattern wavefonm utilized to set u~ automatic aain C~n~ .,timina an~
28 equalization, as shown in Fig. l. The training pattern of Fig. l
29
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2 5 4
, is the analog demodulated pattern at the _eceiver after trans-
2 mission. Th~ system of the preferred embodiment is particularly
3 directed to the quadrature amplitude modulation (Q~M) technique.
4 The training pattern includes in succession a number
of bauds of carrier-only 11, a number of bauds of clock-only 13,
6 a quiet or squelch period 15~ a received impulse 17, and another
7 squelch period 19. The training pattern may also include an
8 optional fine tuning sequence before the transmission of
customer data 20.
In the preferred embodiment, eight bauds of carrier-
11 only 11 and seventeen bauds of clock-only 13 are sent. The
12 squelch periods 15, 19 are twenty-seven and twenty-one bauds long,
13 respectively, and the impulse period is one baud long. Each
14 baud period is 416.7 miliseconds. Of course, other baud periods
could be utilized. Also, the length of the periods 11, 17, 15
16 and 19 depend on the maximum distortion. Wher. thc lin~ distor-
17 tion is less, fe~r bauds are required for each one of them,
18 especially fox periods 17, 15 and 19, and the total time for
19 tuning will be shorter. When the line distortion is severe,
~0 more bauds are required for each period, and the total tuning
21 tLme will be longer.
22 During the carrier-only period 13 in Fig. l, the
23 initial incidence of carrier energy on the line is detected
24 (carrier detect), starting system operation. When carrier detect
occurs, a rough timing counter KSTMX is started, which ultima~ely
26 anticipates the occurrence of ~he impulse response 17. KSTMX
27 counts once per baud.
281 Auto~atic gain control is then perfor~ed on the carrier-
2g .
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32
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only signal 11. After a fixed number of bauds of carrier-only
Z 11 are detected, the system ~nows it is actually receiving a
3 training pattern and can then expect the clock-only signal 13.
4 During the clock-only pattern 13, the apparatus
examines the transmitted pattern to determine the optimllm
6 points to sample the forthcoming impulse response 17. The
7 apparatus then sets up for the impulse response sampling
8 procedure. The firs~ step is to use the sampling point prev-
9 iously calculated to jump or preset the sampling clock to the
optimum sampling position. I~ may thus be seen that the
11 preferred embodiment actually samples the response to a
12 transmitted impulse although other means for generating signals
13 representati~e of such samples could be employed.
14 During the squelch period 15, the rough timing counter
KST~X, which was set-up upon detection of carrier-only, continues
16 to count to subsequently indicate to the apparatus the point in
17 time at which ~o start to sample the in-phase and qlladrat-lre
18 phase impulse xesponses 17 (Fig. lB, lC~. The samples are then
19 taken, stored and correlated for forming a matrix. After the
matrix is formed a special iterati~e technique is utilized to
21 ¦ determine the precise initial equalizer tap settings, as dis-
22 ¦ cussed further below~
23 ¦ The apparatus employed to perform these operations
24 ¦ is illustrated conceptually in block form in Fig. 2. The
25 ¦ apparatus includes an analog to digital (A/D3 converter an
26 ¦ automatic gai~ control (AGC3 sec~ion 21, a digital processor
27 ¦ 23, and a trans~ersal equalizer 28. The equalizer 28 is shown
28 I conceptually for purposes of illustration and is preferably
29 implemented digitally, in which case it could also be ~hown as
31
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2 ~
par~ of the digital processor 23.
2 Digital demodulation of the QAM signal into in-phase
3 (X) and quadrature phase (Y~ base band components, is preferably
4 accomplished in the digital processor 23. The analog form
5 of the demodulated in-phase and quadxature phase baseband
6 components is illustrated in Figures lB and lC, respectively.
7 Demodulation again may ~e performed by well-known techniques
8 and may optionally be performed by dedicated apparatus outside
the digital processor 23. ~either the ~GC or demodulation
10 technique used form a part of the subject invention.
11 The X and Y phase components produced by demodulation
12 represent samples in digital form of the baseband signal, the
13 Y component sample being demodulated by a carrier 90 out of
14 phase from the carrier demodulating the X component sample. In
15 ¦order to calculate the proper samp].ing time during the clock-
16 ¦only period, two samples per baud are taken in the preferred
17 ¦embodiment. ~ter the optimum cloc~ phase is set, the sys~em
18 ¦takes one sample per baud.
19 1 These samples X, Y are sent to separate channels 25,
20 127 of the transversal equalizer 28. Each channel 25, 27 includes
21 equally spaced digital delay elements 29, 31 and digital multi-
22 pliers 30, 32, 33, 35 as known in the prior art. The multi-
23 pliers 32, 33 mu1tiply the delayed samples X~ by constants
24 CPi a~d cqi while the multipliers 30, 35 multiply the delayed
samples Ym by constants CPi and cqi. The "constants" just
26 referred to are also called "coefficients" by some persons in the
271 art. The outputs of each multipliers 30, 32, 33, 35 are summed
28 by respective summers 40, 42, 44, 46 and fed to an adder 36.
29 The output of one summer 46 is subtracted from that of the other
30 ¦42 in a summer
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1~ B2254
37 to give the output data signal EQX. The outputs of the other
2 two summers 40, 44 are summed by a summer 36 to give the output
3 data signal EQY.
4 As shown in more detail in FigO 3, the preferred
embodiment of ~he invention includes a programmed microprocessor
6 structure and an equalizer unit. The equalizer unit 34 includes
71 the functions of the e~ualizer 28 of Fig. 2 and performs steady
8 state adaptivs equalization, for example Z15 taught in U.S. Patent
¦ 4,035,625 issued on July 12, 1977 and assigned to the present
~ol assignee, In the preferred
11 structure of the present invention, the equalizer unit 34 also
1~ contains some circuitry for accomplishing the initial equalizer
13 setting, as will be further detailed below.
l4 The microprocessor structure of Fig. 3 is conventional,
and includes a program store 16, a program counter :L8, for
16 addressing the program store 16, a~command decoder 14 for
17 decoding instructions from the program store 16 to produce
18 control signals and an arithmetic unit 22 for perorming the
19 instructions in response to the control signals rom the decoder
14. The microprocessor structure also includes a data storage
21 memory 26 and an address decoder 24 for addressing the memory.
22 The program store 16 is a conventional read only memory ~ROM)
23 of sufficient capacity to store the instructions for performing
24 the equalizer operations to be described below and may be
cons~ructed from four AMD 9216 ROM chips. The program counter
26 18 is a conventional counter which can be loaded or jumped
27 as necessary in response to control signals from the command
281 decoder 20. The arithmetic unit 22 is also conventional in
29 I i
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I structure and of sufficient power to carry out necessary
2 operations as hereafter described. The data storage memory
3 26 includes storage for constants and 256 words of random
4 access memory and may be configured from three AM9lL12ADC
5 R~ chips and one Çeneral Instrument R03-5120 chip. The random
~ access storage is used to store incoming samples of the impulse
7 response 17 and subsequent data 20 while calculations are
8 underway.
9 The apparatus of Fig. 3 jus~ described performs rapid
10 initial equalization by calculating the initial equalizer tap
11 multiplier constants in ~ery rapid fashion. The manner of this
12 calculation and the function and structure of the apparatus
13 of Fig. 3 will now be explained in detail.
14 The multiplier constants to be calculated are labeled
15 c c c ... c i and cq1, cq2, cq3...cqi (
16 In complex form the e~ualizer tap constants may be expressed as:
17 Ci cpifjcqi ,i=1, 2, 3,..~n
18 To cal¢ulate the equalizer constants ci from the pair of demodu-
19 lated impulse responses as shown in Fig. lB and lC, the ~ollowing
20 definitions are adopted:
21
22 rTO = ~ (Xm ~ Ym) (1)
24 1 m m+1 Ym Ym+l~ + j ~ l(XmYmfl - Y X +1) (2)
25 I m-l m=l
27 ~ m-l ( m m~2 ~ Y~Ymf2) + i ~2(xmym+2 ~ YmX +2) (3)
28 rTn-l m= (Xm m+n-l m m+n-l)+im=l (XmYm+n 1 m m+n-1)(4
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1 The following elements are defined:
2hk - Xn q-k jYn-q-k k=1,2 .. n (5)
3 rT
4 rT.
r _ 1 i=1,2 .. n-l (6j
6 rT0
7 In the above e~uations ~ (6), Xm and Y~ are th~ m th
8 sample of ~he ~ phase and quadrature phase of theimpulse
response used for calculating the au ocorrelation and cross
10 correlation. Equations, ~2), (3~, (4) represent the auto-
11 correlation and cross-correlation of the sa~ples Xm and Ym.
12 In the above e~uations 1-6, M is the total number
13 of samples used for calculating th~ auto correlation and cross-
14 correlation and n is equal to the n~mber of taps, twenty for
15 M and sixteen for n in the preferred embodiment, ancl q equals
16 the subs~ript of the first sample actuall~ used to cal~ulate
17 hk. The variable ~ accounts for the fact that in the preferred
18 embodiment not all samples taken are used, in other words n is
19 less than M as later explained in detail. If n equals M, q=l.
~Q With these definitions, the eq~:k~s defining the
21 optimum tap constants cl, c2, ...cn for an e~ualizer of n taps
22 is written as follows in ma~rîx form:
23 ~ ~ ~
26 .
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29
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.~ ~
. ~1 r2 . ~ rn 1 ~ Cl - - hl-
2 ¦r 1 rl* - ~ rn-2 c~ h2
31 2 rl 1 r*~ ......... ....r* . .
4 r3 r2 rl 1 r*l-...... --.- rn ~ . . '
5~ 7
8 n~ r 1 1 Cn = hn
3o In equation (7)~ rl...ri and hl...hn are complex constants while
11 cl...cn are complex variables. The asterisk (*) indicates t~e
12 complex conjugate form.
13 According to the invention, a special solution of this
14 equation (7) permits a precise iterative calculation of the tap
~5 constants cl...ci within ~he time interval required by the
16 training scheme of Fig. 1 plus the time delay ~equired for
17¦ data to propa~a~e between the input and output of the equalizer.
1~1 According to this solution, the following definitions ar~ made: ¦
19~ e = 1 - ¦r ¦ 2 (8)
20¦ Where ¦rl¦ represents the magnitude of the complex quantity rl;
21l 5l(1) c -r
Where superscxipt "(1) n indicates the first iteration i=l; and
23
24 cl ~ hl (10)
Adapting these definitions, the exact iterative solution for
26 the tap constants is as follows:
27
~8 .
29
31
32
~s ~6~4
+l (hi+l m-l ~m ri-m+l) (Zi
2 ~ Si+l = -(ri-~l +m-l Sm j ri-m~l) (Zi) (12)
~1 cji~l = C(i) + c i.... ~.l 5i ~ < j < i ~13)
61 sj i~1 = S~ s i+l si~J)l 1 ~ j < i (14
7~1 ei+l = ei(l- Is('+l) ¦ 2) (15)
9 Zi~l -- (16)
101 .
11 The superscripts again indicate the value of the variable ~or
12 a particular i~eration. These equations 7 16 provide a simple
13 means for rapidly and exac~ly calculating the tap constants c
14 in the complex matrix equation (7). This iterati.ve tPchni~ue
enables the apparatus of the invention to calculate the constants¦
16 ci and set the equalizer to achieve initial equaliza~ion du~ing a'~
17 total training tim2 of approximate.'y 30 milliseconds from the
18¦ be~inning of carrier only to the first bit of customer data in .
19¦ : a 2400 ba~d machine. ~Variations of the matrix equation (7~ may be
20¦ written and solved by the technique illustrated above without
21l departing from the scope of this invention.
22~¦ The structure and operation of the apparatus of Fig. 3,
23 as ît relates bo the preferred embodiment ofthe i~vention, wîll ~cw
24 described in further detail in conjunction with Figs. 4-8.
After the sarrier is detected and the clock KSTMX is
26 started, the system operates according to the flow illustrated
27 in the flow chart of Fig. 4. The 10w of Fig. 4 illustr-,tes
28 . .
29
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. accomplishment of the automatic gain control function, filter,
2 demodulation, the detecting of the training pattern present (TPP)
3 and calculation of the optimum sampling point to be used in the
4 subsequent operations of Fig. 7. Two samples of the carrier-only
signal are processed each baud for the eight bauds of carrier-
6 only ll. A counter N is set up at -8 to direct operation.
7 As long as N is less than zero, the left branch 43
of the flow is followed and each sample is subjected to an auto-
matic gain con~rol operation 47~ a filter and demodulation opera-
~0 tion 49 and the test pattern present detection 51. The test
11 pattern detection checks six successive bauds of carrier-only
12 signal and thereafter sets a flag indicating that a test pattern
13 is in fact being reoeived. Each baud, the counter N is incre-
14 mented by one, as is the counter RSTMX.
When N equals zero, the clock-only signal l3 begins.
16 ~GC is frozen and the right hand branch 53 of t~e'flow of Fig. 4
17 is entered. In this branch 53, a filter and demodulation opera-
lB tion 55 is performed and a test 57 of ~he TPP flag is made.
lg ¦ Assuming TPP has been detected and the TPP flag set, the ast
20 ¦ learn clock operation 59 is performed. During this operation,
2~ ¦ denoted FLC~R, the apparatus calculates the optimum sampling
22 point for the forthcoming impulse based on the demodulated clock-
23 ¦ only information. After each two samples per baud have been
24 ¦ demodulated.and used in the FLCLK process, the counter KSTMX
~5
26
271 //
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1 ~ is incremented by one, as is the N counter. When FLCLX is done,
2 ¦ the flow proceeds to Fig. 7.
3 ¦ The manner in which the training pattern detection is
41 performed is illustrated in more detail in Fig. 5. Referring
51 to Fig. S, X and Y samples of the demodulated baseband signal
6 ¦ are supplied to respective inpu~ at the rate of two samples
7¦ per baud.
81 The samples presented to the X input are operated upon
gl as follows. Each sample is first squared by a multiplier 63
10¦ and the output of the multiplier 63 is stored for one sample time
11¦ in a delay element 65. The current output of the multiplier 63
12¦ is added to the ~egative value of the previous output of the
~31 multiplier 63 in an adder 67. The output of the adder 67 is
14 ¦ supplied as one input to a second adder 69. The X input is also
15¦ supplied to a second one sample time ~lay element 71. The
16¦ output of the second one-sample delay element 71 is supplied to
17¦ a secvnd mllltiplier 73, also supplied with the X input, such that
18 ¦ the current X input sample is multiplied by the immediately
19 ¦ precediny X sample. The output of the second multiplier 73 is
20 ¦ fed to one input of a third summer 75.
21 I The Y input is similarly operated on. A delay element
22 ¦ 77 delays the first sample of the Y input and a multiplier 79 .
23 multiplies the first sample of ~he Y input by the delayed sample
24 I for supply to the third summer 75. The Y input is also squared
25 ¦ and the square~Y input ~alue is supplied to a delay element 81.
26 ¦ The delayed squared sample is subtracted from a present squared
27 sample by a summer 83 whose output is supplied to the second
28 ¦ summer 69.
29~ The output of the third summer 75 is mul~iplied by two
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I~2~
1 at a multip]ier 85 to form an output denoted as ACK. The output
Z of the s~cond summer 69 is denoted BCK. The arc ta~gent of
3 ACK/BC~ is then taken to determine the sampling angle ~ .
4 The current value of ~ is stored by a delay element 87. The
stored value of ~ is used in the clock preset to be subsequently
6 discussed.
7 It is then determined whether 0~ is within bounds or
8 each of a number of counts NTPP. ~hen NTPP is greater than l0,
9 five bauds of samples have been examined~ Thus, if¦~ ~go¦is less
than 15 continuously for ~reater than l0 MTPP counts it is con-
11 irmed that carrier has been received for 5 bauds, and the TPP
12 flag is therefore set equal to l. Thi; c,~eration is illustrated
l3 in Fig. 5 by proceeding through blocks 9l, 92, 93, to bl~ck 94,
14 TPP equals l. Once1~ -go¦is greater than 15 ~lld TPP equals l,
the clock preset routine is entereZ.
16 In the event~ however, that~n-90¦is greater than 15on
17 any of the carrier-only sa~ples operated on~ the test block 95,
18 TPP=l, will not be satisfied, and NTPP will be reset to zero. In
19 such event, if KSTMX is greater th~n l9~ indicating nineteen
bau~s have occurre~ without detecting TPP, TPP not present is
21 indicated. Failure to detect TPP normally indicates lir.e dropout.
22 Onc~ the training pattern is detected/ it is necessary
23 to properly align the timing of the sampling of the xeceived
24 impulse response 17. The sampling poin~s are calculated such
that the equalizer can best minimize ~he output errorO The
26 structure and technique used in the preferred embodiment for
27 performin~ the presetting of the samplins clock (FLCLK) is
2~1 illustrated in detail in Fig. 6.
29
31 l~
32
2 5~
I ¦ Assuming no distortion or noise, the difference between
21 successi~e angles ~ should be 180. Therefore, if the
3 magnitude
4 ~ n n-ll l
is less than 12 for several successive sa~ples, the clock is
6 in good range. Assuming that ~ is in good range over several
7 sampling intervals of the clock-only pattern, the loop including
8 blocks 101, 102, 103, 104, 105, 106, and 107 in Fig. 6 is
9 operative. Ini~ially, three counters NCNT, NSAMP, and NAV are
set to zero. When ~he first sample is tested, the sampling
11 counter NSAMP is incremented by 1 as înd~cated by the block 101.
12 The angle ~ is then tested, and if it is within range, the
13 counter NCNT is incremented by 1. After four consecutive good
14 samples, the test, NC~T greater than or equal to four (Block 104),
is satisfied, and NAV = 0 is satisfied. In this event, the test
16 indicated by block 106 is performed to ascertain whether the
17 magnitude of ~ is less ~han 90. If so, a counter NR is set
18 equal to 1. ~he counter NAV, representing the numher to be
19 a~eraged, is set equal to 1 and TAGL (total angle) is defined
as e~ual to ~ at this moment. The nex~ time aroun~ the loop,
21 the test NAY = 0 is not true, and NR is incremented by one at
22 block 108. NR ~ 1 is then equal to two. ~R is then not odd,
23 and another sample is ta~en. After this sample, assuming ~
24 is still in bounds, NR is odd (equal to 3).. Therefor~ the num~
ber averaged NAV + 1 = 2 and TAGh is equal to the previous ~n
2~ value plus the new ~ value. Thus there are two angles to be
27 averaged. Assuming that~ continues to be within bounds, the
number of ~n samples averaged is incremented to 4 and then the
29 angle P~ is determined at block los by calculating the quotient
31
32 ~9~
~ ~ ~225~
1 of TAGL and NAV. P~ indicates the number of degrees from which
2 the sampling point being used diverges from the optimum sampling
3 point. Thus, it takes 10 angle differences within bounds to
4 reach the block P~ = TAGL/NAV.
In the event, how~ver, that distortion is occurring,
6 other provisions are made for calcula~ing
7 P~ . For example, if it occurs that ~ is ~reater
8 than 12, satisfying block 102, a test 110 jf made to determine is
9 the number of good samples counted ~CNT i5 greater than or equal
to 4, i.e~ whether four inbounds angle tests have occurxed. If
11 so, a test 111 is made of the NAV counter to d~termine whether
12 any samples TAGL have been stored for averaging. If any samples
13 have been stored, the average ~av = TAGL/NAVL is computed as
14 indicated by the four blocks 112, 113, 114, llS. These four
t5 blocks indicate that P~ is taken as e~ual to ~av i NR is even,
16 whereas ~ is taken as equal to ~
18 ~ ~GN(~aV)l [18~ ¦~avl]
19 ¦ if NR is odd. If, however, at the test 111, NAV is found to
20 ¦ be equal to zero, indicating no samples ~ have been accumulated,
21 ¦ P~ is taken to be the current sample ~n.
22 If the NCNT > 4 test llQ is not satisfied, a test 117
23 of the number of samples, indicated by counter NSAMP is made.
24 If ~hat number NSAMP is greater than 29 (~ 14 bauds), P~ is
again ta~en to be ~ n If NCNT > 4 is not satisfied and NSAMP
26 29 is not satisfied, NCNT is set to zero and another sample is
27 examined. This procedure assures that if the angle determination
Z8 is initally or occasionally out of bounds, subsequent angles can
29 be examined ~o average the clock according to ~he previously
discussed procedures.
31
3~ -20
~ :~ 8 ~
P~ then determines the phase shift of the impulse
21 sampling clock to be used in the matrix sampling operation
31 illustrated in Fig. 7.
4 ¦ In Fig. 7, the first time through, the new program (NP)
51 test 121 is positive and the left branch 123 of the flow is
6¦ followed. Here the equalizer random access memory (RAM) 26 is
71 reset. Also the optimum sampling point determined by FLCLK is
81 used to jump the sampling clock to the optimum sampling position
9¦ within each baud. The clock rate is reduced in half to 2400
10¦ Hz such ~hat one sample per baud of the impulse response is
11¦ taken from each o~ the X and Y channels. .
12¦ The second time through the flow of Fig~ 7, a second
131 branch 125 is followed. Detected samples are demodulated (block
141 127), and then a tes~ 129 is performed on KSTMX to see if it is
15~ greater than 45. I it is not, XSTMX is incremented (block i31~.
16¦ As soon as KSTMX is greater than 45, matrix ~ormation 133 from
17¦ the sampled impulse 17 begins.
~8¦ The branch followed when KSTMX < 45 includes a demodu- !
191 lated output energy test which assures that the system is
20 ¦ receiving the equalizer tes~ pat~ern and not customer data.
21 ¦ After KSTMX is greater than 38 the energy is determined as denote~
2~ I by blocks 134, 138. If he energy is below a set level Eref, the
~ I squelch period is assumed to have been detected and the system
24 ¦ knows a training pattern is present. ~f ~he energy is greater
25 ¦ than E f~ training pattern TPP not present is indicated. This
261 provides a double ~heck on the presence of a training pattern.
281
291 . Il
301 . I
311 . .
, I -21- j
I
~ 5 ~
Sampling of the impulse wave form 17 is illustrated by
2 the vertical lines in Fig. lB and lC. The number of samples is
3 counted by a counter K, started when KSTMX = 45. Each sample
4 produces an X component xi and a Y component Yi. As the samples
xi, Yi are successively taken, formation of the matrix equation
6 (7) according to the deinitional equations ~1), (2~, (3), (4)
7 begins. For example, during the ,first baud, xl and Yl are taken
~ and stored in the RAM 25 and may then be used to calculate
9 xl + Yl / the first itera'ion of rT0, equation (l). During the
second and successive samples, itexations of rT0 and ~he corre-
ll la~ing equations rTll rT2... are calculated.
12 As the second sample x2 t Y2 is ta~en, it is stored in
13 the RAM 26, and the square of its magnitude, X2 + Y2 is com-
14 pared to the square of the first sample magnitude xl2 + yl2 to
determine which is larger. The larger i5 retained and compared t~
16 the square of the magnitude of the next sample to determine the
17 largest sample and hence the peak 180 of the sampled impulse
18 ! response 17. The baud KP during which the peak 180 occurs is
! stored to be used in subsequent operations. All samples ~i~ Yi
20 ¦ are also stored.
21 Sampling is terminated upon one of two conditions as ',
22¦ indicated by a test 137 (Fig. 7). For the applicat~on of the
23 pxeferred embodiment, it is advantageous to use eight samples
24 before the peak and ele~en after the peak. If eleven samples
have occurred after the peak, K= KP + ll, and matrix ~ormaticn
26 is terminated. If g <8, KP is set equal to eight (blocks 13SJ
136) so that at least nineteen samples must be taken before for-
28 mation can be termina~ed upon K = KP ~ ll. O~herwise, once
29
31
32 -22- j
t,
,.
t~enty-four total s~mples have been taken, matrix formation is
2 termunated and a flag is set.
3 Once the matrix flag is set, the next time through
4 the flow, a bxanch 132 occurs to th~ test 141, K > 20 (Fig. 8).
If grea~er than 20 samples have been taken, the test 141 is
6 satisied, and ~he processor 23 proceeds to correct the effect
on the matrix of taking too many samples.
8 Thus, K > 20 indicates that, because of the rough
9 alignment of the counter KSTMX, too many samples before the
occurrence of the peak 18 have been taken. These samples wili
11 likely contrihute to inaccuracies and their efect is subtracted
12 by an operation l~3 denoted SU~ 1. Thîs subtraction is accom-
13 plished by taking the first samples xl, Yl from memory, calcu-
14 lating. their impact upon the values for the e~uations (1), (2),
(3) for rT0, rTl, rT2, etc. and subtracting that impact. After
16 the effect of the first sample xi, Yl is subtracted the sam~le
lq¦ coun~.er K is decremented by one (blocX 145) and.the R ~ 20 test
18 ¦ 141 is a~ain performed. If the test 14~ is satisfied, the
19 efect of the second.sample pair x2 t Y2 is calculated and sub-
20¦ tracted, etc. until K < 20. Once K < ~0, the values determined
21 by the remaining sampleS xi, Yi are utilized in the subsequent
22 matrix calculations.
23 Once K is reduced to 20, h br~nch 147 occurs to the
24 tap constant c~lculation process, equations (5) - ~6) and (8) -
(16), first passing through a test 149 to determine if the calcu~,
26 laton has already been done. At the beginning of the calcula-
28 tion process, a c~ountex N is set to zero. A tes~ 151 of the
value of N is then made.
29 . .
31 .
32 . ~3
~22~
The fi.rst step 153 i~ the calculation process, with N
2 equal to zero, is a noxmalization process. During this step
3 the ri's and hk's of equations (4) and (5) are calculated by
4 the microprocessor structure of Fig. 3.
The next time through branch 147, with N e~ual to 1
(block 155), the microprocessor develops t~e e~uali~tion con-
7 s~ants ci by calculating Successive iterat:ions of the equations
8 (11) (12) (13) (14) (i5) (16), previously discussed.
9 With N = 2, the microprocessor structure of Fig. 3
begins to interact with the equalizer unit 34 in the following
11 manner. The microprocessor calculates equations (11) and (12)
12 and then transfer the "r" matrix (equation 7) and other inter-
13 mediate calculation results to the equalizer unit 34. In this
14 manner, the microprocessor shifts part of the calculation respon-
sibili~y to the equalizer uni~ 34 in order to free ~he processor
16 to handle other operations on the inco~ing data. The equalizer
17 unit 34 contains hard wired logic whi~h performs or calculates
18 the subsequen~ iterations of equations ~11) through ~14). For
19 N = 2, the ~lizer only calculates equations (13) and (14). At
the end of each calculation of an iteration of equations
21 through ~14~ in the equalizer unit 34, (13 and 14 only for N = 2)~
2~1 the proces.~or calculates the quantity Zi~l equations (15) and ¦ ¦
(16), and returns that value to the equalizer 34 for performance ,
24 o~ the nex~ iteration of equations (11) through (14). This
allocation of calculation between microprocessor and equalizer
26 unit is merely due to a desire to efficiently utilize the appara- .
tus. As is apparent, the assignment of the calculations of
~8 .
29
.
31 .
32 . -24-
~ I
~ 2~4
equations (11) through (14) to circuitry associated schematically
2 with the equalizer unit 34 is one approach to calculating the
3 instant equalizer settings. Other approaches such as utilization
4 of a more power~ul microp~ocessor to do all calculations could
be implemente~ according to the subject invention.
6 When N is equal to 15, the maf rix has been solved for
7 the tap constants c~ and the iteration done flag is set. When
8 the final tap constants are calculated, the hk's are stored and
9 the final equalizer constants ci determined according to the
just described procedure are set.
11 The just discussed operation is sufficient to set 16
12 taps. I~ the line signal is of such a poor quality that addi-
13 tional taps are needed, a fine tuning procedure may be performed i
14 in which additional bauds of known two phase da~a are sent and
the error difference detected and used to adjust the additional
16 taps according to conventional prvcedures. Il
17 As is indicated in the above discussion, many modifica-¦
18 tions and adaptations of the preferred embodiment are possible
19 without departing from the scope and spixit of the inventionO
20¦ For example, as illustrated in FigO 9~ 10, and 11 the ',
21j in-phase and quadrature-phase signals used by the equalizer of the
221 invention may be derived other than at baseband and in systems
23 using various demodulation schemes.
24 ¦ Fig. 9 illustrates a simple quadrature demodulation
25 ¦ technique wherein baseband signals x~t) and y~t) constitute the
26 ¦ in-phase and quadrature~phase signals~ In Fig J 9 t the received
27 ¦ signal on an input line 201 is fed to first and second mixers
28l
29
31 I -25-
32
2 ~ ~ 4
1 203, 205 ~herein the line signal is mixed with respective signals
2 cos~ t and - sin~ t where w is the carrier frequency. The com-
3 ponents are then filtered by respective baseband filters 207, 209
4 to yield the baseband quadrature components x(t) and y(t);
In ~ig. 10, the received signal is fed to a first pass-
6 band filter 211 having an impulse response h(t) and ~o a second
7 passband filter 213 having an impulse response h~t~, which is
8 the Hilbert transform of the impulse response h(t~ of the first
9 filter 2Il~ The respective outputs h(t), h~) of the filters
211, 213 are at passband frequency and constitute in-phase and
11 qua~rature-phase signals which could be sampled by the egualizer
12 of the subject invention.
13 In Fig~ 11, an output h(t) of the ilter 211 is fed to
14 a first mixer 21S and ~o a fo~ mixer æl. The output h(t)
of the filter 213 is fed to a second mixer 217 and to a third
16 mixer 219. The four mixers 2i5, 217, 219, 221 receive respec
17¦ tive second inputs of cos~ct, sin~ct, cos~ct, cos~ct, where ~c
18 ¦ is the carrier frequency. The outputs of the first and second
19 mixers 215, 217 are then summed by a summer 218 to give the demo-,
201 dulated baseband signal x(t) . The output of the fourth mixer
21 221 is subtracted rom the output of the third mixer 219 at a
22j summer 220 to give the demodulated baseband signal y(t)~
23 Fig. 11, x(t) and y(t) are in-phase and quadrature-phase signals
24 which can also be sampled according to the invention to accomplis~
initial setting of the equalizer taps.
26 Therefore, it is to be understood that, within the
27 scope of the appended claims, the invention may be practiced othe
28 than as specifically described herein.
29
31
32 -26-
