Note: Descriptions are shown in the official language in which they were submitted.
~ RD~865
HIGH VOLTAGE SEMICONDUCTOR DEVICE HAVING
IMPROVEMENTS TO THE dv/dt CAPABILITY
AND PLASMA SPREADING
Related Patents
This application is related to V.A.K. Tample
United States Patent Number 4,261,000 issued April 7, 1981,
and to V.A.K. Temple United States Patent Number 4,261,001
issued April 7, 1981, both of which are assigned to the
instant assignee.
Background of the Invention
This invention relates to semiconductor switch-
ing devices, and more particularly, to high voltage
semiconductor switching devices having reduced suscepti-
bility to inadvertent device turn-on due to high voltage
transients.
Thyristors, triacs and transistors are
; semiconductor devices often used to turn~on and turn-off
high voltage sources. These devices include at least
first and second main current carrying electrodes and
a gate electrode. A main vol-tage is applied across
the first and second electrodes, such that a main
current flows therebetween upon application of a
control signal to the gate electrode. The device is said
to be in a turned-on state when conduction current flows
between the first and second electrodes. Because the
device has an internal junction capacitance, its forward-
blocking capability is sensistive to the rate at
which a forward voltage is applied to its main
terminals. A steeply rising voltage impressed across the
main terminals may cause a capacitive charging
current to flow through the device. The charging
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current (i=C,dv/dt) is a function of the inherent
junction capacitive value and the rate of rise of
the impressed voltage. If the rate of rise of impressed
voltage exceeds a critical value, the capacitive
charging current may be large enough to generate
a gate current at a sufficient level and for a sufficient
time to turn-on the device. The ability of the device
to withstand an impressed voltage transient across
its main terminals is commonly termed the dv/dt capability
specified in volts/microseconds. The dv/dt capability
becomes of particular importance when voltage transients
are impressed across the main terminals of the device.
Voltage transients occur in electrical systems when
some disturbance disrupts the normal operation of
the system or even in normal circuit operation when
other devices in the system switch on or off. Voltage
transients generally have a fast rate of rise that
may be greater than the dv/dt capability of the device.
If the rate of rise of the transient exceeds the dv/dt
capability of the thyristor, for example, it may cause
the device to be inadvertently turned-on.
There are a number of known methods for increasing
the dv/dt capability of the semiconductor device.
One such method is the use of "emitter shorts" in a
relatively large emitter area of a semiconductor device.
Disadvantages that may occur with the use of emitter
shorts are that the gate current required to activate
the semiconductor device is increased and the di/dt
rating of the device is also decreased.
Another known method of improving the dv/dt capabil-
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ity of the semiconductor device is the use of inter-
digitation. Interdigitation increases the initial
turn-on area of the emitters and correspondingly reduces
the turn-on sensitivity of the device to gate current.
The interdigitation approach raises problems related
to packaging as well as increasing gate current requirements.
A still further known method of increasing the
dv/dt capabiIity of the semiconductor device is the
use of a resistor connected between the gate and the
cathode of the semiconductor device, which provides
a shunt path to divert a portion of the transient
generated gate current away from the emitter of the
cathode. The use of a resistive shunt path for the
gate signal reduces the gate sensitivity of the semiconductor
device as well.
The present invention concerns a high voltage
semiconductor device in which the dv/dt capability
; of the device is increased by decreasing the amount
of the transient capacitive charging currents conducted
to the emitters of the device.
One object of the present invention is to provide
circuit means externally connected to the semiconductor
device to cause a re].atively large increase in the dv/dt
rating of the device but with a relatively small decrease
in gate sensitivity.
Another object of the present invention is to
provide a semiconductor device ir which means are incor-
porated for increasing the dv/dt rating of the device
with but minimal effect on the other parameters o~
the device.
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A still further object of the present invention
is to provide a semiconductor device in which the speed
of a plasma created upon initial turn-on of the device
is increased~
These and other objects of the invention will
become apparent to those skilled in the art upon consid-
eration of the following description of the invention.
Summary of the Invention
In accordance with one preferred embodiment of
the invention, a high voltage semiconductor device
comprises at least a first cathode including a first
metallization layer, a second cathode including a second
metallization layer, an anode, and a gate region adapted
to receive an applied signal. Each of the first and
second cathodes has an emitter layer affixed thereunder
and each cathode is separated from the anode by at
least a first and second layer of alternating conductivity-
type material. The second cathode and the anode are
; adapted to be coupled between opposite ends of a relatively
high voltage potential source having periodic relatively
high voltage transients. Periodic occurrences of the
voltage transients between the second cathode and the
anode generate capacitive charging currents within
the first and second layers which are manifested as
gate current ln the emitter layers of the first and
second cathodes. The gate current in the emitter layer
of the first cathode, if unreduced in amplitude, is
of a sufficient value to cause conduction between the
first cathode and the anode. The high voltage semiconductor
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device further comprises capacitive means coupled to
the gate region to provide a capacitive shunt path
for diverting a portion of transient generated capacitive
charging current flowing within the gate region away
from the emitter layer o~ the first cathode and that
part of the first layer lying thereunder, such that
the transient generated capacitive charging currents
which are manifested as the gate current are reduced,
thereby improving the dv/dt capability of the high
voltage semiconductor device.
The features of the invention believed to be novel
are set forth with particularity in the appended claims.
The invention, itself~ however, both as to its organization
and operation, together with further objects and advantages
thereof, may best be understood by reference to the
following description taken in conjunction with the
accompanying drawings.
Description of the Drawings
Figure 1 illustrates a partial cross-section of
one preferred embodiment of the present invention in
which an impedance is employed to provide a shunt path
for transient gate current; and
Figure 2 is a partial cross-sectional view of
a center-gated amplifying gate thyristor of the present
invention in which internally insulative layers are
employed to increase the dv/dt rating of the device.
Detailed Description of the Preferred Embodiment
Figure 1 shows a partial cross-section of a semicon-
ductor device 10 in a center-gated amplifying thyristor
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configuration exemplifying one embodiment of the present
invention. Device 10 has an anode base layer 16 of
an N-type semiconductor material and a P-type semiconductor
material forming a layer 18 which is situated beneath
and in contact with the layer 16. A cathode-base layer
14 of P-type semiconductor material is situated above
and-in contact with the layer 16. Layers 14 and 16
have a beveled surface 38 located at their outer peripheries
for improved avalanche breakdown voltage. Semiconductor
layer 14 furnishes a major portion of a top surface
19 of the semiconductor device 10. Semiconductor layer
J~
~& generally constitutes the substrate of the device
10 with layers 14 and 18 being formed by diffusion
and/or epitaxial growth. Device 10 includes a pilot
thyristor 13 and a main thyristor 28 each having an
additional high conductivity n~ layer shown respectively
as 15 and as 17. The n-~ layer 15 constitutes the emitter
of the pilot thyristor 13. Similarly, the n~ layer
17 constitutes the emitter of the main thyristor 28.
The emitter 15 is overlaid with a metallization layer
26, herein termed the pilot stage cathode electrode
or first cathode electrode. Similarly, the emitter
17 is overlaid with a metallization layer 30, herein
termed the main stage cathode electrode or second cathode
~5 electrode. Emitter 15 and layer 26 comprise the pilot
stage cathode while emitter 17 and layer 30 comprise
the main stage cathode.
Metallization layer 30 provides a contact for
connecting one end of a relatively high voltage source
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via terminal 34. Metallization layers 26 and 30, if
desired, have conventional emitter shorts 32 formed
in their top portions and extending into region 14.
A further metallization layer 24, herein termed the
gate of device lO, overlays cathode-base layer 14.
Gate 24 may be connected to an electrical gate signal
source via terminal 22. In one form of a photo-sensitive
amplifying gate thyristor 10 a light signal may impinge
upon part or all of gate region 47. For this purpose,
electrode 24 ls selected to be transparent to the incident
light radiation, or maintained with small area to allow
'~' 3~ sufficient light to impinge on surface-~ in gate region
47 in order to trigger the device.
A still further metallization layer 20 is positioned
under layer 18 and provides a means for connecting
the other end of the high voltage source to the device
10 via terminal 36. Metallization layer 20 is herein
termed the anode of device 10.
Semiconductor device 10, as shown in Figure 1,
includes a gate region 47 extending from a centerline
12 to a leading edge, or turn on line, 70 of pilot
thyristor 13, a pilot thyristor region 49 extending
from the termination of gate region 47 to the termination
of emitter 15 of pilot thyristor 13, and a main thyristor
region 51 beginning at a turn-on line 80 and spanning
the emitter 17 of the main thyristor 28. The leading
edge of the pilot thyristor on the side closest to
gate region 47, and thereby being leading relative
to the gate region.
As previously discussed, occurrences of voltage
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transients impressed across the cathode and anode of
a semiconductor device, such as device 10, may cause
capacitive charging currents to flow within device
10. The capacitive charging currents are shown in
Figure 1 as a plurality of arrows 41 emerging from
anode 20 and flowing upward through layers 18, 16,
' and 14 towards the top portion 19 of device 10. A
portion of the transient capacitive charging currents
may be manifested as a gate current of sufficient value
to exceed a critical value and render the main thyristor
28 conductive, thus inadvertently turning on device
10. Similarly, a portion of the transient generated
capacitive charging currents 41 may also intercept
and render conductive the pilot thyristor 13, thus
also inadvertently turning on device 10.
In the embodiment of Figure l, an impedance means
11 is provided to reduce the susceptibility of device
10 to inadvertent turn on by voltage transients. Reducing.
the susceptibility of inadvertent turn on correspondingly
increases the dv/dt capability of device 10.
Impedance means 11 is connected between gate 24
and second cathode electrode 30 to provide a shunt
path for a portion of the transient capacitive charging
currents. Thus impedance means 11 provides a shunt
or parallel path to conduct a portion of the transient
generated capacitive charging currents away from emitters
15 and 17, and thereby provides the shunt path for
most of the transient capacitive charging currents
flowing within gate region 47.
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Impedance means 11 is comprised of a capacitor
having a substantially non-dissipating energy characteristic
and a relatively low impedance to fast transients.
Use of a capacitive shunt increases the dv/dt capability
of the semiconductor device but increases the turn-
on delay time of device 10, and, in general, somewhat
reduces the di/dt rating of device 10. For reasons
explained infra, the value of capacitor for impedance
means 11 is selected with consideration given to the
increased dv/dt capability obtained and also to the
resulting increased turn-on delay and correspondingly
decreased di/dt rating of device 10.
It will be appreciated that use of capacitive
shunt 11 having a low impedance to rapid transient
currents diverts a portion of the capacitive charging
; currents 41 away from the emitters 15 and 17 and thereby
decreases the dv/dt derived gate current that is applied
to the pilot thyristor 13 and main thyristor 28. The
gate current as a function of time, herein termed IG(t),
is approximately represented by the following relationship:
IG(t) - CJ dv/dt (1-e G ) (l)
where
CJ = the junction capacitance of the gate region 47;
t - elapsed time during the voltage transient;
CJ dv/dt = the capacitive charging currents generated
by the voltage transients;
~G~ = (CJ ~ C11). RGK for the time duration t,
wherein
C11 = capacitive value of impedance means 11; and
R = resistance value between gate electrode
2~Kand second cathode electrode 30.
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The symbol ~G is herein termed the gate 24-to-
c.thode 30 time constant. It should be recognized
that the value of TG for device 10 having an inherent
capacitive CJ and resistance RGK may be chosen by appro~
priate selection of a capacitive value for C11.
After a time duration tramp when the voltage transient
generating the capacitive charging current ceases,
IG may be approximately represented by the following
relationship for times greater than tramp:
IG(t) = IG(tramp) exp (~(t~tramP)/ a (2)
where ta is the time constantmeasurin~ the decay of
IG~
Equation (1) may be integrated over the tramp
time duration to determine the charge delivered to
the gate during tramp and then the result of equation
(1) may be added to the integral of equation (2) for
time durations greater than tramp to determine the
total charge delivered to gate 24, having impedance
means 11 attached, by the dv/dt gate current. The
determined charge may then be compared to a charge
that would have been developed without the capacitance
of impedance means 11 connected between gate 24 and
second cathode electrode 30. The resulting comparison
would be representative of an improved dv/dt factor
F, which may be approximately represented by the follow-
ing relationship:
F =
l - e~(tramp/ G) (3)
As previously mentioned, while impedanee 11 improves
the dv/dt capability of device 10 it also increases
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C~
TABLE I
Anode Voltages Delay di/dt di/dt
and ll Approxima-te l'ime (A/~sec.) (A/~sec.)
Gate Currents (~d) F Values ~sec.) _yristor (2a) Thyristor (13)
01.00 6.8 200 llO
.021.29 8.4 200 110
VA = 400V.041.77 10.0 200 100
IG = 200ma.062.35 11.6 200 100
.082.93 13.2 200 100
.103.53 14.8 200 100
.206.50 20.3 ~00 100
.309.50 ~6.5 200 100
.4012.50 32.2 200 lO0
.5015.50 38.0 200 100
_
01.00 3.6 230
VA = 400V.052.06 6.2 225
IG = 400ma.103.53 8.0 225
.155.02 9.8 220
.206.50 11.3 220 110
.309~50 14.2 215 100
_ 40l2.50 l6.9 210 100
01.00 5.1 1100 550
VA = 800V.011.05 6.0 1150 500
IG = 200ma.021.29 6.8 1100 480
.041.77 8.3 1050 440
.052.06 9.0 1000 440
.06, 35 9.8 1000 440
.082.93 11.3 1000 420
.103.53 12.5 950 410
.20 6.5 18.3 900 400
.30 9.5 24.0 880 360
.4012.5 29~5 850 360
.6018.5 40.5 850 360
, .,
,~ --1 1 --
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the turn-on time of device 10 to the degree that impedance
means 11 takes away gate current from gate 24. In
most thyristor applications for relatively low speed
switching, such as <lkHz, a TG in the order of 20~
seconds will not substantially dégrade the performance
of device 10r If the switching speed needed for the
thyristor's use is ~1kHz, then~G should normally be
chosen to be no more than a few microseconds.
It should be recognized that impedance means 11
reduces the rise-time of the normal gate current signal
applied to gate 24 under normal Piring conditions.
Hence, the turn-on speed and the di/dt rating of device
10 may be affected under normal firing conditions.
To investigate the degree of reduction in turn-on di/dt
of an amplifying gate thyristor corresponding to improved
dv/dt factors F, experiments were per~orrned, the results
of which are shown in Table I. These results present
measured turn-on speeds in units of di/dt.
The values given in Table I were derived using
equation (3) for a tramp = 1llsec., and ~= RGKC11
where RGK ~ 30Q and C11 is as shown in Table I for
each corresponding value of F. The turn-on di/dt in
the column for thyristor (28) are those that occurred
during turn~on of main thyristor 28. Similarly, the
di/dt reading in the column for thyristor (13) are
those that occurred during turn-on of pilot thyristor
13. The first four readings of di/dt for pilot thyristor
13 associated with VA = 400V and IG = 400ma were not
determined.
From review of Table I, in particular for VA-800V
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and IG=200ma., it, is evident that the largest percent
reduction in the turn-on di/dt occurs for thyristor
13 changing from 550 to 360. However, the cor~responding
F value shows an increase from 1.00 to 18.5. Thus,
for a relatively low decrease in the turn-on di/dt
a corresponding relatively high improvement to the
dv/dt capability of the device is realized as a consequence
of utilizing capacitor ll, without any substantial
degradation in the other capabilities of device 10.
A second embodiment of the present invention that
uses built--in insulative layers to perform a function
similar to that of externally connected lmpedance means
11 is shown in Figure 2, which illustrates a partial
cross-section of a center-gated amplifying gate thyristor
40 having a pilot thyristor 21 and a main thyristor
33. The layers 14, 16 and 18, transient capacitive
charging currents 41, be~e~-Y~, anode 20, and gate
.~b '
24 have a similar structure and function as described
for device lO of Figure 1.
Pilot thyristor 21 includes an emitter 37 formed
of a high conductivity n+ layer upon which is overlaid
a metallization layer 44, herein termed the pilot stage
cathode electrode or first cathode electrode. Similarly,
main thyristor 33 fncludes an emitter 39 formed of
a high conductivity n+ layer upon which is overlaid
a metalli2ation layer 45, herein termed the main stage
cathode electrode or second cathode electrode.
An insulating layer 46, preferably comprising
an oxide of semiconductor layers 14 and 37, is formed
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within layer 14 and emitter 37, and is located to contact
and overlap turn-on line 70 of pilot thyristor 21 under
the leading edge 48 of first cathode electrode 44.
The mating of leading edge 48 with insulating layer
46 forms a layered arrangement 50. An insulating material
54 is formed within layer 14 and emitter 39 and located
to contact and overlap turn-on line 80 of main thyristor
33 under the leading edge 56 of second cathode electrode
45. The mating of leading edge 56 with insulating
layer 54 forms a layered arrangement 57.
With further regard to main thyristor 33, an insulating
layer 60, preferably comprising an oxide of semiconductor
layers 39 and 14, is formed within layar 14 and emitter
39, and is located in a complementary arrangement with
a local region 58 of second cathode electrode 45 under
which layer 39 has been etched away or otherwise removed.
An alternative to local region 58 and insulator 60
is an ~nsulating layer 62, preferably comprisin~ an
oxide of semiconductor layer 14 which is formed beneath
second cathode electrode 45 and located in a local
region 68 in which emitter 39 was intentionally not
diffused or epitaxially grown. lnsulating layers 46,
54, .60 and 62 have a thickness and area predetermined
to control the capacitance of regions 53, 57, 58 and
25 68, respectively, in the same manner that capacitance
C11 was chosen or varied in the embodiment shown in
Figure 1.
The layered arrangements 50 and 57 provide built-
in bypass capacitors for pilot thyristor 21 and main
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thyristor 33 respectively. These capacitors provide
means for shunting the capacitive charging currents
4i generated by voltage transients impressed across
the anode and second cathode, away from emitters 37
and 39 of pilot thyristor 21 and main thyristor 33
respectively. The shunt path for pilot thyristor 21
is provided by layered arrangement 50 diverting a portion
of transient capacitive charging cur.rents 41 to
first cathode electrode 44. Similarly, the shunt path
for main thyristor 33 is provided by layered arrangement
57 diverting a portion of transient capacitive charging
currents 41 to second cathode electrode 45.
~ Device 40, shown in Figure 2, having built-in
bypass capacitors 50 and 57 within pilot thyristor
21 and main thyristor 33, respectively, accomplishes
the same result as device 10 having impedance means
11, as shown in Figure l. Built-in capacitive values
~or layered arrangements 50 and 57 of device 40 in
Figure 2 provide approximately the same dv/dt improvement
factor F, listed in Table I for corresponding capacitance
values C11, with the same degree of increase in turn-
on time and reduction in di/dt rating, as for device
10.
The combination of local region 58 and insulating
layer 60 provide a capacitive type "emitter short"
in an etched defined type of emitter, as shown in Figure
2. Similarly, the combination of insulating layer
62 positioned under second cathode electrode 45 in
an area 68 in which the highly conductive material
of emitter 39 has been removed provides a capacitive
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type "emitter short" in a diffusion defined type of
emitter. These capacitive type emitter shorts positioned
in main thyristor 33 reduce susceptibility to inadvertent
turn-on of amplifying gate thyristor 40 in a manner similar
to that occurring as a result of conventional emitter shorts
as previously discussed. However, the capacitive emitter
shorts of main thyristor 33 do not inhibit spreading of
a plasma created upon initial turn-on of a thyristor, as
compared to what occurs as a result of conventional emitter
shorts. The capacitive emitter shorts of main thyristor
33 increase plasma spreading speed and thus are likely
to increase the di/dt capability oP device 40 while maintaining
a high dv/dt capability.
It should be recognized that the density and
area of local region 60 or 62 should be adjusted so that
the dv/dt current flowing into each ~esults in no more
than a one-half band gap of voltage across the built-in
inJ ec~
capacitor. This will assure little ~4~e~t-K~ from the
adjacent n+ emitter P-base junctions. Note that some of
the emitter shorts could be conventional ones. For example,
conventional shorts could be alternated with capacitive
shorts.
Although arnplifying gate thyristors have been
described herein, it should be recognized that the described
embodiments bf this invention are also applicable to other
semiconductor devices, such as thyristors and high voltage
transistors. For a thyristor not having a pilot thyristor
stage for amplifying the gate current, the described embodiments
need only be utilized for the main thyristor stage. Similarly,
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for a high voltage transistor having two layers of alternating
conductivity-type rnaterial similar to layers 14 and 16,
the described embodiments need only be utilized to divert
the capacitive charging current away from the emitter layers
of the transistor whereby they are not amplified by the
gain of the transistor.
It ~will now be appreciated that the described
embodiments herein concern high voltage semiconductor devices
allowing for relatively large improvement to the dv/dt
rating of the devices and relatively low degradation to
the other parameters of the devices. Still further, the
described embodiment utilizing capacitive emitter shorts
in the main thyristor emitter layer improves the di/dt
capability of the device while maintaining the relatively
high dv/dt capability of the device.
While the invention has been particularly shown
and described with reference to several preferred ~mbodiments
thereo~, it will be understood by those skilled in the
art that various changes in form and detail may be made
therein without departing from the true spirit and scope
of the invention as defined by the appended claims.
