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Patent 1164548 Summary

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Claims and Abstract availability

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(12) Patent: (11) CA 1164548
(21) Application Number: 368254
(54) English Title: REPEATER FOR A DIGITAL TRANSMISSION SYSTEM
(54) French Title: REPETEUR POUR SYSTEME DE TRANSMISSION NUMERIQUE
Status: Expired
Bibliographic Data
(52) Canadian Patent Classification (CPC):
  • 340/100
  • 333/27
(51) International Patent Classification (IPC):
  • H04L 25/20 (2006.01)
  • H04L 25/03 (2006.01)
(72) Inventors :
  • JESSOP, ANTHONY (United Kingdom)
  • CATCHPOLE, RICHARD J. (United Kingdom)
  • FARLEY, BRIAN S. (United Kingdom)
  • DYKE, PETER J. (United Kingdom)
(73) Owners :
  • STC PLC (United Kingdom)
(71) Applicants :
(74) Agent: SMART & BIGGAR
(74) Associate agent:
(45) Issued: 1984-03-27
(22) Filed Date: 1981-01-09
Availability of licence: N/A
(25) Language of filing: English

Patent Cooperation Treaty (PCT): No

(30) Application Priority Data:
Application No. Country/Territory Date
8001632 United Kingdom 1980-01-17

Abstracts

English Abstract



A. Jessop et al 7-4-1-1
(Revision)

Abstract of the Disclosure

A repeater for PCM ox digital transmission systems
includes, in addition to the usual primary feedback control
loop, a secondary feedback control loop having a low-pass
filter and a peak detector to derive a control signal for a
controllable impedance in the equalizer circuit. This control
loop optimizes the repeater performance fox different cable
types and characteristics with regard to the low frequency
energy content of the eye diagram.

ACH/mlw/jn
November 17, 1980


Claims

Note: Claims are shown in the official language in which they were submitted.


A. Jessop et al 7-4-1-1

THE EMBODIMENTS OF THE INVENTION IN WHICH AN EXCLUSIVE PROPERTY
OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:
1. A repeater for a digital transmission line system comprising:
an automatic line build out circuit having a
primary equalization feedback control loop coupled
between an output of said line build out circuit and a
first controllable impedance means connected in said
line build out circuit, said primary feedback control
loop being responsive to equalized signals at said
output of said line build out circuit; and
an equalizer circuit having its output coupled to
an input of said line build out circuit, said equalizer
circuit having at least one secondary feedback control
loop coupled to said output of said line build out
circuit, said secondary loop being responsive to said
equalized signals including a filter coupled to said
output of said line build out circuit and a first peak
detector coupled to the output of said filter to produce
a control signal to control a second controllable
impedance means connected in said equalizer circuit.
2. A-repeater according to claim 1, wherein
said filter is a low pass filter.
3. A repeater according to claims 1 or 2, wherein
said primary loop includes a second peak detector
having its input coupled to said output of said line
build out circuit and its output coupled to said first
controllable impedance means to control said line
build out circuit.



A. Jessup et al 7-4-1-1

4. A method of equalization for a digital transmission line
repeater comprising the steps of
filtering equalized signals within a control
loop; and
detecting peak values of said filtered equalized
signals to provide a control signal for controlling
equalization in said repeater.
5. A method according to claim 4, wherein
said step of filtering includes the step of low
pass filtering said equalized signals.
6. A feedback control loop for an equalization network in a
repeater of a digital transmission line system comprising:
a filter coupled to the output of said network
responsive to equalized signals at the output of said
network; and
a peak detector coupled to the output of said
filter responsive to a continuous low frequency voltage
output of said filter to produce a control signal for
controlling a controllable impedance included in said
network.
7. A control loop according to claim 6, wherein
said filter is a low pass filter.



Description

Note: Descriptions are shown in the official language in which they were submitted.


5~L~


1
A. Jessop-R J Catchpole- !.;;.:
P.J. Dyke~B.5. Farley 7-~-1-1
~Revision)
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A REPEATER FOR A DIGITAL TRAIISMISSIO~ SYSTEM
, .
Back~round of the Invention
This invention relates to repeaters for PCM (pulse
code modulation) or digital transmission svstems, and more -~
particularly to arrangements for compensating therein for -~
transmission line characteristics.
Conventional automatic line build out (ALBO) networ~s
provide variable eqùalization within a primary equalization
:
feedback control loop to correct for mainly frequency
dependent losses due to line length variations. However,
changes in cable type, e.g., paper insulated, plastics
insulated, etc., in cable characteristics and signal level
variations all e~fect the performance o~ repe~ters. The ~.
. . .
use of high efficiency line codes, such as that known as
4B3T and disclosed in U.S. Patent 3,611,141, issued
October 5, 1971, requires accurate equaIization of line
losses, especially at lower frequencies where this code :
contains more energy than codes, such as that known as
HDB3 (~igh Density B;polar 3~, whether Gr not the signals
are scrambled.
A known equalizer design for heavily multiplexed PCM
systems, e.g., 48 channels at 2.37M bit/sec, for example, is
shown in Fig. 1. This design incorporates a primary equali-
zation control loop to keep the height of the so-called "eye 1f"
diagram" constant, with the ALBO network carefully designed
to give correct equalization for a range of different line

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lengths. The equalized signal is taken from a decision point X and applied
to an ALB0 peak detector 10, which detects the peak or "height" of the eye
diagram. This peak value is amplified and fed to a diode network 11. The
output of diode network 11 is used to control the ~LB0 network equalization.
When the repeaters are manufactured a manually adjustable variable resistor
is included in network 12 to enable the repeater, once installed, to be
adjusted for the lo~ frequency content of the eye diagram
An object of the present invention is to provide an improved
arrangement in a repeater for a PCM or digital transmission system to
compensate for transmission line characteristics.
According to a first aspect of the present invention, there is
proyided a feedback control loop for an equalization network in a repeater
; of a digital transmission line~system comprising: a filter coupled to
the output of said network responsive to equalized signals at the output
of said network, and a peak detector coupled to the output of said filter
responsive to a continuous low frequency voltage output of said filter to
produce a control slgnal for controlling a controllable impedance included
in said network.
According to a second aspect of the present invention, there is
provided a repeater for a digital transmission line system comprising: an
automatic line build out circuit having a primary equalization feedback
,
control loop coupled between an output of said line build out circuit and
a irst controllable impedance means connec~ed in said line build out
circuit, said primary feedback control loop being responsive to equalized
signals at said output of said line build out circuit; and an equalizer
circuit having its output coupled to an input of said line build out cir-
cuit, said equalizer circuit having at least one secondary feedback control
loop coupled to said output of said line build out circuit, sald secondary
loop being resporlsive to said equalized signals including a filter coupled
to said output of said line build out circuit and a first peak detector
coupled to the output of said filter to produce a control signal to control
~J a second controllable impedance means connected in said equalizer circuit.

s~

In a preferred embodiment the secondary loop filter is a low pass
filter.
According to a third aspect of the invention, there is provided
a method of equalization for a digital transmission line rep~ater compri~
sing the steps of filtering equalized signals within a control loop; and
detecting peak values of said filtered equali~ed signals to provide a
control signal for controlling equali~ation in said repeater.
The above-mentioned and other features and objects of this
invention will become more apparent by reference to the following descrip-
tion taken in conjunction with the accompanying drawing~ in which:




~J
-2a-



A. Jessop et al 7-4
-3-
~ic~. 1 is a bloc}; diagram of the prior art equali-
zation arrangement described hereinabove under
the heading "~ack~round o~ the Invention"; and
Fig. 2 is a block diagram of a repeater equalization
arrangement in accordance with the principles of
the present invention.
escription of the Preferred Embodiment
The repeater of Fig~ 2 is basically the repeater of Fig. 1
with the addition of the secondary control loop. The equalized
si~nals rom decision point X are fed to a low-pass filter 20
which is followed by a peak detector 21. The output of peak
; detector 21 is amplified and ~ed as a control signal to a
variable impedance 22 in equalizer 13. The low pass filter 20
ensures that the secondary loop only responds to the low
frequency content of the eye diagram or control of equalizer
13. This automatic control of equalizer 13 optimizes the
equaliæation for thebest eye diagram, regardless of the cable
type or characteristic of the input cable.
While we have described above the principles of our
invention in connection with specific apparatus, it is to be
`~ clearly understood th~t this description is made only by way of
ex~ample and not as a limitation to the scope of our inventicn
as set Cor~h in the objects thereof and in the accompanying
claims.

ACH/mlW/jn
November 17, 1980




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Representative Drawing

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Administrative Status

For a clearer understanding of the status of the application/patent presented on this page, the site Disclaimer , as well as the definitions for Patent , Administrative Status , Maintenance Fee  and Payment History  should be consulted.

Administrative Status

Title Date
Forecasted Issue Date 1984-03-27
(22) Filed 1981-01-09
(45) Issued 1984-03-27
Expired 2001-03-27

Abandonment History

There is no abandonment history.

Payment History

Fee Type Anniversary Year Due Date Amount Paid Paid Date
Application Fee $0.00 1981-01-09
Registration of a document - section 124 $0.00 1999-06-18
Owners on Record

Note: Records showing the ownership history in alphabetical order.

Current Owners on Record
STC PLC
Past Owners on Record
INTERNATIONAL STANDARD ELECTRIC CORPORATION
Past Owners that do not appear in the "Owners on Record" listing will appear in other documentation within the application.
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Document
Description 
Date
(yyyy-mm-dd) 
Number of pages   Size of Image (KB) 
Drawings 1994-03-15 1 26
Claims 1994-03-15 2 76
Abstract 1994-03-15 1 31
Cover Page 1994-03-15 1 22
Description 1994-03-15 4 179