Note: Descriptions are shown in the official language in which they were submitted.
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LOW rAI~A~ITAN OE SELF-ALIGNED SEMICONDUCTOR
ELEC~'P~O~E STRUCTURE AND METHOD OF FABRICATION
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This invention relates to high frequency semiconduc-
tor devices and, more paxticularly, to an electrode
structure with low parasi~i.c capacitance and a method for
fabricatin~ low capacitance electrodes in a semiconductor .
device while avoiding the requirement or precision mask
~li.g'IlI~ nt .
Semiconductor dev.ices designed ~or high frequency
ope.r~cion require electrodes having extremely small dim~
sions and must: be fabricated under extremely tight dirrlen-
sional control to minimize stray capacitance and serlesresi.stance~ Devices designed for operation at or above
one s~gahertz utiliæe electrode widths of one or two
micxons and electrode separations of a few micxons.
PhotolithographiG alignment and mask to mask registration,
lS therefore, requires a precision of a few ten-ths of a
micron. Such re~uiLements make processing of high fre-
quency semiconductor devices costly and difficult.
On~. example of a device requiring precislon a]ign-
. ment and mask to mask registration is the static induc-
tion transi.stor J ~ field effect device which exhibits
excellent high power and high frequency capabiliries
~rhe s~at.ic induction t:ransistor (SIT) typically u-til.izes
a vertica]. geomecry~ Source and drain contacts a.e
\ placed on o~posite sides of a thin, high-resistivi.ty
2S layer of one conductivity type. Gate regions of the
cpposite conductivity type are diffused into the high
res.istivity layer on opposite sides of the source. Gate
and source widths are typically 1.5 microns while the
gate to source spacing is typically 5 microns. ~ sliyht
mas~ mis~lignrl~ent can resu't in short-c:ircuit.ed semi.~
conduc.to~ devic~es or ca.n degrade device perforrl~all(e.
Furt~ermore, the pacasit.ic ca~acitance associatecl wi.th
metal~.ic contact cve:rlap degrades device perforrnarlce.
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It is, therefore, d~isirahle to provi.de an electrodestructure in which the parasitic capacitance associated
with metallic contact windvw Gverlaæ is reduced and to
provide a method for fabricating low capacitance elec-
S trodes in semiconductor devices while avoiding ~hexequixemerlt for precisi.on mask alignment and mask to
mask registration.
According to one aspect o~ the invention, there is
provided a method for forming self-aligned irst and
second electrodes in a semiconductor device while
avoiding the requirement for precision mask alignment and
mask registration r said method comprising the steps of:
growing a first oxide la er on a silicon semiconductor
wafer in which said first and second electxodes are -to
be formed; opening first and second windows in said first
oxide layer; depositing a protective silicon nitride
layer in said first window; doping said semiconductor
wafe.r through said second window thereby forming said
second electrodei yrowing a silicon layer of the same
conductivity type as said second electrode over said
wafer, said silicon layer growing as a low resistivity
monocrystalline region over said second electrode and as
a polycrystalline region over the remainder of said wafer;
exposing said wafer to a first etching solution which
removes said polycrystalline region but which has little
effect on said monocrystalline region; growing a second
oxide layer on said wafer in a low temperature, high- ,
pressure process; exposing said wafer to a second etching
solution which removes said silicon nitride layer from said
first window without affecting said oxide ].ayers; doping
said semiconductor wafer .hrough said first window thereby
forming said first electrode; openin~ ~ contact window
throu~h said second oxide layer to an enlarged portion of
said monocrystalline region; and depositing and patterning
metal over said con'cact window and said Eirst electrode for
makin~ electrical contact to said first. and second
electrodes.
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The silicon layex is typically grown ln an e~itaxi.al
reactor by chemical vapor deposition. One example of a
semiconductor device to wh.ich the ~ethod of the present
invention is applicable is the static induction transistor.
According to another aspect of the invention, there
is provided a field effect semiconductor device havincJ
low parasi-tic capacitance, said device comprising: a high
resistivity layer of semiconductor matexial of one
conductivity type; a low resistivity source electrode
formed on a first surface of said high resis~ivity layer;
a low resistivity drain electrode formed on a second
surface of said high resistivity layer; low .resistivity
gate electrodes of the opposite conductivity type ~or~ed
on the first surface of said high resistivity layer on
1~ opposite sides of said source electrode; and very low
resistivity monocrystalline silicon gate contacts disposed
on said gate electrodes without overlap thereof, sa.id gate
contacts having the same conductivity type as said gate
electrodes and including enlarged portions to wh:ich .
electrical contact is made by a gate metalli~ation,
whereby the parasitic capacitance associated with
metallic gate contact overlap is eliminated.
Some embodiments of the invention will now be
described, by way of example~ with reference to the
accompanying drawings, in which:
FIG. 1 is a cross-sectional vlew of a semiconductor
wafer after opening of gate and source windows in a first
oxide la~er~
FIG. 2 is a cross-sectional view of the semiconductor
wafer of Fig. 1 after deposition of a silicon nitride
layer in the source window;
FIG. 3 is a cross-sectional view of the semiconduc.:or
wafer shown in Fig. 2 after doping of the yate
electrodes;
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FIG. ~ is a cross-sectional view of the semiconduc- -
tor waler shown in Fig. 3 after growth of a silicon layer
over the wafer;
FIG. 5 ls a cross-sectional view of the semiconduc-
tor wafeL shown in Fig. 4 after etching of the polycrys-
talline portion of the silicon layer;
FIG. 6 is a cross-sectional view of the semiconduc-
tor wafer shown in Fig. 5 after growth of a second oxide
layer;
FIG. 7 is a cross sectional view of the semiconduc~
tor warer shown in Fig. 6 after etching of the silicon
nitrid~ la~er and doping of the source electrode;
~IG. 8 is a top view of the semiconductor wa~er
shown in Fig. 7 after deposition and patterning of the
1~ source and gate metallizations;
FI~ 9 is a cross-sectional view of the semlconduc-
tor wafer shown in Fig. 8;
FIG. 1~ is a cross-sectional view of the semic~nduc-
- tor wafer shown in Fig. 7 illustrating an alternative
method of r,taking electrical contact to the source elec-
trode; and
FTG. 1].~ i5 a top view of the semiconductor wafer
shown in Fig. 10 illustrating the source and gate
metallizations.
For a better understanding of the present invention
together with other and further objects, advantages a~d
capabilities thereof reference is made to the folloT,7ing
disclosure and appended claims in connection with the
above descxibed drawings.
A method for forming self-aligrled ~irst and second
electrodes in a semiconductor device while avoidirlcJ the
requirement for precision mask aligmnent and mas~ to mask
regist~ation is descri~ed by way of exarlple in connectiorl
~, 3s with a vertical geometry static induction transistor (SIT).
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The SIT i~cludes source and drain eiectrodes on opposite
sides of a thi.n, hlgh-resistivity layer o one conductiv-
ity type and gate elect~odes of the opposite conduc-tivity
type in the high resistivit~ layer on opposite sides of
the source. For operation in the one gigahertz ~recluency
range, it is necessary that the widths and spacing of the
gate and source electrodes be on the order o~ a few
microns.
Referring now to Fig. l,there is ~hown a partial
cross-sectiona.L view of ~ semiconductor wafer 10. A hic3h
resistivit~ epitaxial layer 12 is growr, on a highly doped
substrate 14 of one conductivity type. In a typical de-
vice the substrate 14 provldes mechanical support ancl is
about 2~0 microns in thickness while the ep;.taxial layer
12 is about 7 to 10 microns i.n thickness and has a resis-
tivity of at least 30 ohms centirneters. Next, a silicon
dioxide layer 16 is grown on the upper surface of the
epitaxial layer 12. The oxide layer 16 can be formed by
known methods such as exposing the semiconductox wafex 10
to an oxygen and steam ambient at about 1100C. Gate
windows 18 and a source window 20 are fo.rmed in the oxide
la~er 16 in th~ next step. J.n a typical method of form-
ing windows 18 and 20, a photoresist material is applied
to the upper suxface of the oxicl2 layer 16, expose~d
through a patterned mask, and developed. The exposed
portions of the oxide layer 16 are etched by a suitable
solution such as buffered HF, or NH4:HF, to form the win-
dows 18 and 20. Since the gat~ wi.ndows 18 and the source
window 20 are formed at the same tim~ no alignment is
required durinJ this step.
Referri.ng now to Fig. 2,the semiconductor wafer 10
is shown after depositlon o a silicon nitride layer 22
i.n the source window 20 accorcling to the n~xt step of the
process. A typical method of forrllincJ the silicor! nitride
layer 22 is by chemical vapor depc;sltion from ammonia at
a~out 800C. While a raa~,~ is rec~uirc-~cl for patterninc3 the
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si:licon nitride, precisiorl alignment of the mask is not
required. The dimension of the m~sk ap~rture is made
larger than the dimension of the source window 20 so that
the silicon nitride layer 22 overlaps the source window
20. Overlap o~ the silicon nitride layer 22 is not a
problem as long as it does not extend into the gate win-
dows 18. The silicon nitride layer 22 protects the high
resistivity epitaxial layer 12 beneath the source window
~0 during the succeeding steps of the process.
In the next step of the process the epitaxial layer
12 is doped through the yate windows 1~ to form gate
electrodes 24, as shown in Fig. 3. The ga~e ele~trodes
24 can he formed by standard methods ofiion implantation
and drive-in diffusion or by prediffusion and drive-in
diffusion. In the example of the static induction tran-
sistor, the gate electrodes 24 have low resistivity and
are of the opposite conductivity type from the epitaxial
layer 12. This step requires no alignment.
The semiconductor wafer 10 is now introduced int~
70 an epitaxial reactor for growth of a silicon layex 26
over its top surface as shown in Fig. 4. The silicon
layer 26 is grown by standard chemlcal vapor depositicn
techniques from a SiH4-H2 gas system at a temper~ture
between about 950C and 1000C. In the growth of the
2~ silicon layer 26, monocrystalline, or epitaxial, regions
28 are formed in the gate windows 18 a.s a continuation of
the crystal structure of the gate electrodes 24. A poly-
crystalline region 30 is formed over the remainder of
the semiconductor wafex 10, including the oxide layer 16
and the silicon nitride layer 22. The monocrystalline
regions 28 grow at a faster rate and become thicker than
the polycrystalline region 30. Since the monocrystalline
regions 28 act as the contacts to the gate electrodes 2~1,
these regiolls are formed w:ith the same conductivity t~pe
~ as the gate electrodes 24 and have low resistivlty. In
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the present example, the mollocrystalline regions 28 are
grown to about 15,0~0 angstroms in thickness.
It is possible, by controlling the epitaxial growth
conditisns, to reduce the rate of yrowth of the undesired
S polycrystalline region 30. When the Si4-H2 gas system is
used, growih temperatures of about 1200C minimize yrowth
o~ the polycr~stalline region 30 on SiO~. However, un-
acceptable impurity redistribution can occur in the semi-
conductor wafer 10 at 1200C. Therefore, lower tempera-
tures are preferred. As described hereinafter, the poly-
~rys~alline region 30 can be removed by etching techniques.
The silicon layer 26 can alternatively be grown using
a SiCL4-IICl-E2 gas system. The use of silicon chlorides
with HCl was described by R. K. Smeltzer, in "Epitaxial
Deposition of Silicon in Deep Grooves", J. Electrochem.
Soc.: Solid ~State Science and Technology, 112, No. 12,
p. 1666 (1~75). When a silicon chloride gas s~stem is
used, the growth of the polycrystalline region 30 over
silicon dioxide can be reduced by controlling the concen-
2Q tration of ~Cl in the system.
The silicon layer 26 is exposed in the next step toan etching solution whi~h etches the polycrystalline
region 3~ at a faster rate than the monocrystalline
regiorls 28. ~uring this etching step the polycrystalline
region 3~ is removed while the monocrystalline region 28
remains, as shown in Fig. 5. One etching solution which
can be used to remove the polycrystalline reyion 30 is
buEfered HF, or NH4F:HF, in a ratio between 1:5 and 1:10.
The buffered HF filters through the relatively porous
polycrystalline region 30 and attacks the surface of the
silicon dioxide layer 16, causing the polycrystalline
region 30 to lift off, or peel off, the surface. No such
effect occurs in the monocrystalline regions 28. An
alternative mixture, which operates by selective etchin~
rather than lift-off~ is potassium hydroxide and n-~ro~
panol. In se]ective etc~ling, the polycrystalline regior.
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30 is etched at a higher rate than the rnonocrystallineregions 23. Another selective etching mixture is
ethylenediamine, cate~hol a~d water. One suitable ex-
~nple of this mixture is 46.4 mole % ethylenediame, 4.2
mole ~ catechol, and 49.4 mole ~ water and an etchiny
temperature of about gOC is used.
After the polycrystalline region 30 of the silicon
layer 26 has been removed, a second oxide layer 32 is
grown over the surface of the semiconductor waer lO as
shown in Fig. 6. In reali.ty, the oxide layer 32 is a
continuation of the growth of the oxide layer 16.
However, the oxide layer 32 is separately identified in
FigO 6 for purposes of clarity. The o~:ide layer 32 does
not grow over the silicon nitride layer 22 but lifts the
edges o F the silicon nitride layer 22 by a small arnount
as is known in the art. To avoid impurity rediscribution
in the semiconductor wafer 10 r a low temperature, high-
pressure oxidation process is utilized. Typically, a
temperature of about 950C and a pressure of about
10 atmospheres are used ~or growth of the oxide layer 32.
The silicon nitride laye~ 22 is thon stripped off
the wafer 10 to provide access to the sol1rce window 20,
as shown in Fig. 7. The silicon n tride layer 22 can be
removed by known methods such as exposure to phosphoric
acid at about 80C or plasma etching. In this step, the
oxide layers 16 and 32 are left intact. Next, a thin
source electrode 34 is formed by ion im~lanation or dif-
fusion of impurities. In the static induction transistor,
the source electrode 34 has low resistivity and is of the
same conductivity type as the epitaxial layer 12.
A partial top view of the semiconductor wafer 10 is
shown in Fig. 8. The monocrystalline regions 28 which
cover the gate electrocles 24 are in the form of elongated
strips and are buried under the oxide layer 32. The rnono-
crystalline regions 28 include enlarged portions 36 atone end thereof. In the next ste~ of the process o~ the
-~ present invention, gate contact winclows 38 ace opened ln
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the o~ide layers over the enlarged portions 36 uti.l,izing
the process descrihed herelnabove in conne-ction ~i,th the
openlng of windows 18 and ~0. The use of enlarged por-
tions 36 obviates the recluir~ment for precislon mask
alignment in this step.
In a metallization step, metallie gate and source
eontaets are deposited and patterned. ~ gate co~tact 40
ineludes fingers 42, which extend over the gate eontact
windows 38 for making electrieal contaet to the mono-
er~stalline regions 28, and a relatively large reg,ionfor external lead attaehment. A souree eontaet ~ in-
eludes a finger 45, as shown in Fiys. 8 and 9, in the
souree window 20, for making eleetrieal eontaet to the
souree eleetrode 34, and a relatively large reyion for
external lead attachment~ The metallic eontaets are
typieally made by sputtering of aluminl,~ ineluding 2%
silieon. An appropriate mask produees the metallic con-
taet patterns. While the metallization mask requires ............ ..
reasonably preeise alignment to ensure proper plaeement
2n of the source eontaet 42, a small misalignment of thesource contact 42 does not seri.ously dec~rade the per-
formanee of the statie induetion transistor. Mask align-
ment is also less eritical with respect to the gate con-
:~ ~aet 40 since the deviee dimensions are larger in t.he
xegion o~ the gate contact windows 38 than in the elonga-
ted stri.p portions of the monocrystalline regions 28.
It is to be understoocl that Figs. 1~9 illustrate
only a portion of the semiconductor ~afer 10. A complete
static induction transistor typically includes multiple
source electrodes in an array of parallel strips~
Parallel gate electrodes are located between each pair of
source eleet.odes. The source electrodes and gate elee-
trodes, respectivel.y, are connected in parallel to for~n
a deviee with the desired power h~ndling capabi.lity.
The completed SIT w:ith low eapae.-i-tanee selr-alicJned
gate electrodes is illustrated in Figs. 8 and 9. An
.,- ohmie eont~ct 48 is attached to the bottom surface o~ the ,:
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su~strate 14 and constltutes -the drain contact for the
*evice. ~y way of specific examplé, a high ~requency
SIT can be fabricated with the substrate 14 having a
resistivity of about .Ol ohm centimeter, the high resis-
tivity layer 12 having a resistivity of at least 30 ohmcentimeters, the ga~e e].ectrodes 24 ha~ing an impurity
surfa~e concentration of lOl8cm 3, the monocrystalline
regions Zg having a .resistivity of less than O.l ohm
centimeters, and the source electrode having a resis-
tivity of less than O.l ohm centimeter. Gate and sourceelectrodes are typically l.5 to 2.5 microns in width
and are spaced apart by 4 t:o 5 microns. Gate and source
electrode depths are typically 2.5 to 3 microns and 0.3
microns, respectively. Further details regarding the
construction and operation of static induction transis-
tors are disclosed by Nishizawa et al in U.S. Patent
~os. 3,828,230 and 4,lg9,77l; by Nishizawa et al in
"Field Effect Transistor Versus Analog Transistor (Static
Induction Transistor)," IEEE Transactions on Electron
Devices, Vo].. ED-22, No. 4, April 1975; and Nishizawa
et al in "Hiyh Frequency High Power Static Induction
Transistor," IEEE Transactions on Electron Devices,
Vol. ED-25, No. 3, March l978.
In an alternative ap~roach, the source contact is
formed as a monQcrystalline silicon region over the source
electrode, as shown in Figs. lO and ll. The device is
fabricated in the manner descrihed hereinabove up -to and
including the step of stripping the silicon nitride layer
22. Then a second silicon layer, having the same conduc-
tivity type as the epitaxial layer 12 but having very lowres;.stivity, is grown over the semiconductor ~ra~er lO, as
described hereinabove in connection with the silicon
layer 26. The second .silicon layer includes a monocrys-
talline region 50 over the source elec-trode 34 and a poly-
c.rystalline region (not shown) over the remainder of the
. semiconductor wafer lO. The second sil.icon layer .is then
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exposed to an etching solution which remo~s the poly-
crystalline region but does not attack the monocrystalline
region 50. Suitable etching solutions are described here-
inabove. After etching of the second silicon layer, a
protective oxide layer 52 is yrown over the semiconductor
wafer 10. During the oxidation step, the source electrode
34 is formed by outdiffusion from the highly doped region
50.
The monocrystalline region 50 which covers the source
electrode 34 includes an enlaryed portion 54 at one end
thereof as illustrated in Fig. 11. Gate contact windows
38 and source contact windows 56 are opened in the oxide
layers over the enlarged portions 36 and 54, respectively,
utilizing the process describe~ hereinabove in connection
with the opening of windows 18 and 20. secause of the
relatively large dimension~ of the enlarged portions 36
and 54, precision mask allgnment is not required.
A metallic gate contact 40 includes fingers 42,
which make electrical contact to the monocrystalline re-
gions 28, and a larger reglon for lead attachment, as
described hereinabove. ~ metallic source contact 58 in-
cludes a fingex 60, which extends over the source contact
window 56 for making electrical contact to the monocrys-
talline region 50, and a larger region for lead attachment.
The contacts 40 and 58 are made by sputtering of aluminum
including 2~ silicon. An appropriate mas}r produces the
metallic contact patterns. Since the metallic contacts
are aligned only with the erllarged portions 36 and 54,
precision alignment of the metalliæat~on mask is not
re~uired. ~ -
The completed SIT with low capacitance self-aligned
gate and source electrodes, as ill~strated in E'igs. 10
and 11, can have the parameters OL the device shown in
Figs. 8 and 9 and described hereinabove. I~he mono-
crystalline regior 50 can have a resistivity of les~
than 0.1 ohm centimeter.
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Thus, there is provided by the present invention ~.nelectrode structure in which the parasitiG capacitance
associated with metallic contact window overlap is
reduced. The reduction in contac~ window overlap by
metallic contacts results in a significant reduction in
parasitic capacitance and an improvement in high frequency
device performance. Furthermore, there is provided a
method for fabricating closely spaced electrodes in a
high frequency semiconductor device while avoiding the
requirement for precision mask alignment and mask to mask
registration.
While there has been shown and described what is at
present considered the preferred embodiments of the
invention, it will be obvious to those skilled in the
lS ~rt ~hat various changes and modifications may be made
therein without departing from t.he scope of the invention
as defined by the appended claims.
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