Note: Descriptions are shown in the official language in which they were submitted.
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FIELD OF TIIE INVENTION
The present invention relates to power supply regulators
and more particularly to a DC regulator.
BRIEF DESCRIPTION OF ~HE PRIOR ART
Frequently, a DC output voltage requires regulation
due to the fact that it is subject to overvoltage and
undervoltage transients of relatively high value. Circuits
have been developed to convert an unregulated DC input
~ voltage to a regulated DC output voltage while providing
input-to-output isolation. These circuits are well known
to those in the art and include push-pull converters, boost-
buck regulators, and bridge inverters. The prior art circuits
suffer from several disadvantages. In general, large voltage
excursions of the input create large voltage and current
lS stress leve;s in the semiconductor~s used in the regulator
circuits. Further, large currents are experienced by ilter
capacitors used in such regulator circuits. Historically,
this problem has been handled in two ways. The flrst involves
the use of costly semiconductors or, in some cases, parallel
connected semiconductors have been used. In an alternative
solution, input power is preconditioned, thereby increasing
cost and complexity of the circuit while decreasing the
efficiency thereof.
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I j BRIEF DESCRIPTION OF THE PRESENT IN~IENTION
The present twin transformer inverter alleviates
many of the problems previously encountered. A control
unit provides a pulse width modulated square wave having
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a duty cycle ~hich is a ~unc~ion of output voltage. The
square wave is transforrner coupled to power switching tran-
sistors which operate 180 degrees out of phase with each
~ other. By filtering the outpu~ of the power switches,
a regulated DC output voltage is derived.
As will be explained hereinafter, by interconnec-ting
transformers in a twin configuration,~output ripple current
~i is significantly reduced. Further~ there is a marked
reduction in voltage and current stress on semiconductor
devices in the circuit, as compared with those in conventional
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; regulators. Previous regulation techniques produced ripple
currents that were equal to the output load current and
', caused the output filter to be excessiveIy large. The
i present circuit reduces the ripple current to 1~3 of the
15, output load current and, consequently, one-third of the
filtering is all that is required. Further, the use of
twin connected transformers provides for a simple and
effective paralleling of the switching transistors and
I output rectifiers, thereby reducing the electrical stress
20on each.
,I The above-mentioned objects and advantages of the
present invention will be more clearly understood when
l considered in conjunction with the accompanying drawings,
in which:
I BRIEF DESCRIPTION OF THE FIGURES
¦ FIG. ] is a basic block diagr~m of the present invention.
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FIG. 2 is an electrical schematic diayram of the
present invention illustrating a pulse width modulation
control unit in block form~
` FIG, 3 is a logic circuit illus-trating the pulse
width modulation control unit in detail.
FIG. 4 is a composite timing diagram showing signal
flow at various points of the inventive inverter.
DETAILED DESCRIPTION OF THE IN~ENTION
Referring to the figures in detail, and FIG. 1 in
particular, a basic block diagram of the present inverter is
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:illustrated. A pulse width modulation control unit 16 provides
a pulse width modulated (PWM) square wave having a duty
cycle which is a funct1on of output voltage derived at
terminal 12 A transformer 18 couples the PWM square wave
to power switches 20 whlch operate upon the unregulated
DC input voltage indicated at lOo The output of the power
switches i9 fed to a filter 22 which accomplishes final DC
voltag~ regulation. A feedback connection between the output
voltage and the PWM control unit 16 occurs along lead 14.
` FIG. 2 illustrates the system in greater detail.
The PWM control unit 16 briefly mentioned in connection
i with FIG. l is seen to include an input 24 connected t.o
I a B+ source. A current sense line 26 furnishes an additional
Ii input to the control unit and senses current at the output
of the inverter, as will be explained hereinafter. Similarly,
j lead 27 provides a further input to the control unit 16
and serves to sense voltage at the output of the inverter.
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A common return for the control unit 16 and the inVerter
output occurs along retuxn lead 28~
The primary winding of transformer 18 is connected
to the control unit output and includes upper and lower
terminals 30 and 34, respectively, as well as a center tap
32. The secondary winding of the transformer includes upper
and lower terminals 36 and 48, respec~ively, along with
a center tap 42 which is connected to a return potential
of the input voltage, along connecting lead 43. The PWM
square waves from the control unit 16 are transformer coupled
through transformer 18 to a common emitter power switch
configuration including transistors 40 and-46. The emitters
45 and 44, of transistors 40 and 46, respectively, are con-
nected to the center tap 42 of transformer 18 which is
connected to the return potential of the input voltage.
The base 38 of transistor 40 is connected to the upper
secondary winding terminal 36 while the base 50 of tran-
sistor 46 is connected to the lower terminal 48 of the
~ seconda~ry winding of transformer 18 thereby completing the
input to the power switching transistors. The output of
the power switching transistors is coupled to the primary
windings of twin connected transformers 56 and 57. Specifically,
the collector 52 of transistor 40 is connected to the upper
jj terminal of transformer primary winding 54 while the lower
terminal 59 of the primary winding 54 is connected to the
,` positive potential of the input voltage, along connecting
lead 60. The input voltage is stabilized by capacitor 64
appearing across the input. It will be noted that the lower
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terminal of primary winding 54 (transformer 56) is directly
connected to the upper -terminal of primary winding 61 (trans-
former 57) so that the previously mentioned positive potential
is likewise provided the upper terminal of primary winding 61.
The collector of transistor 46 is connected to the lower
terminal of primary winding 61, via connecting lead 58.
In operation of the circuit, the PWM square waves from
transformer 18 are fed to the power switching transistors
40 and 46 whlch operate as saturated switches 180 degrees
out of phase with each other. While transistor 40 is con-
ducting, current is built up in transformer 56 and when
transistor 40 is turned of, transistor 46 turns on and
operates 180 degrees out of phase with transistor 40. The
upper terminal of the secondary winding 66 (transformer 56)
is connected to the anode of a diode 68 while the lower
terminal of the secondary winding 72 (transformer 57) is
connected to the anode of diode 74. The cathodes of the
; diodes 68 and 74 are connected in parallel to lead 76.
With transistor 40 conducting, polarity is such that diode
68 is reversed biased. When transistor 40 turns off, diode
68 becomes forward biased and load current is supplied until
transistor 40 turns on again. Operation of diode 74 similarly
utilizes the switching of transistor 46 and coupling -throu~h
; transformer 57. However, diode 74 operates 180 degrees
out of phase with diode 68.
The cathode of diode 68 is connected~ via lead 76,
as the positive potential point 77 for the output voltage.
The junction point 70 between the lower terminal of secondary
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winding 66 (transformer 56) and the upper terminal of sccondary
winding 72 (transformer 57) is connected as a common terminal
28 for the output voltage. In order to sense current flowing
through the output section of the inverter, a resistor 80
is connected between the common terminal 28 and the junction
point 70 of the secondary windings of transformers 56 and
57. The previously mentioned current sense line 26 performs
its current sensing function by monitoring a small voltage
across the resistor 80 thereby providing overcurrent protec-
tion. Capacitors 82 and 84 are connected across the output
voltage terminals to filter the output voltage thus providing
a well regulated supply.
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PWM CONTROL UN _
Referring now to FIG, 3, the PWM control unit 16
is seen to ;nclude an operational amplifier 86 which serves
as an error voltage amplifier. A first input to the amplifier
is provided along lead 88 which is connected to the B-~ supply
at 24, via resistor 90. The negative potential of the output
voltage, along lead 28, is connected in parallel with the
input 88 of amplifier 86, via Zener diode 94. The second
input 96 to amplifier 86 carries the positive potential
of the output voltage along lead 77. The output 98 of
amplifier 86 produces an error signal between the reference
B+ voltage and the output voltage. A second operational
amplifier 100, serving as a current error amplifier has
a first input connected along lead 104 to the common terminal
28 of the output voltage while a second input, appearing
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along lcad 26, carries the output current flowing through
~ resistor 80 (FIG~ 2) so that amplifier 100 is a current
; sensing device for achieving overcurrent protection. The
output of amplifier 100 is connected, via lead 102, to the
output of the amplifier 86 at a node 106 which, in turn,
is connected as a first input 108 to comparator 110. The
comparator is a high gain operational amplifier. In order
to understand the nature of a second input 115 to comparator
110, reference is made to oscillator 112 which generates
clock signals at the output thereof which are fed to integrator
114 which integrates the trigger pulse signals to form a
triangular wave as shown at the output of integrator 114.
The superposition of the DC level input to comparator 110
and the triangular signal input to the comparator is
illustrated along lead 126 at the output of comparator 110.
A pulse width modulated signal occurs and as shown along
lead 126, it has zero crossovers at the point of intersection
between the triangular and DC signals. The PWM signal on
` lead 126 is fed in parallel to NAND gates 120 and 124.
A second input 118 to NAND gate 120 is derived as an output
from flip-flop 117 while a complem~ntary output 122 from
. the flip-flop 117 drives a second input of N~ND gate 12~. !
The purpose of flip-flop 117 is to enable gates 120 and
' 124 in synchronism with the clock input pulses to flip-flop
117 as they occur along oscillator output lead 116. The
gates 120 and 124 are enabled 180 degrees out of phase with
~i each other. This difference of phase conduction is conveyed
1, at respective output terminals 128 and 129 to the upper
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and lower primary winding terminals 30 and 34. A reference
voltage, namely B+, is connected to ~he center tap 3Z of
the primary winding of transformer 56 via a semiconductor
current source 130. The PWM pulses appearing at the primary
winding of transformer 56 are coupled to the subsequent
inverter circuitry as previously explained in connection
with FIG. 2.
FIG. 4 is a composite timing diagram showing signal
waveforms at various points in the circuitry of the inverter,
as indicated on the Figure.
; It should be understood that the invention is not
limited to the exact details of construction shown and
described herein for obvious modifications will occur to
persons skilled in the art.
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