Note: Descriptions are shown in the official language in which they were submitted.
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SUPPRESSED C~O~K EXTRACTION BY A PHASE LOCKED L~OP
- BACKGROUND OF THæ INVENTION
This invention relates to a method of clock
extraction throu~h a special arrangement o~ a phase locked
loop.
For most baseband digital communications, data is
usually transmitted in a form of suppressed carrier method to
achieve maximum usage of the cha~nel's bandwidth. Bip~lar
or binary (unipolar) are popular methods. Some data
recording formats (such as ~, MFr~I~ r~FM and etc.) and NRZ can
also be considered as modified suppressed clock modulations.
Phase locked loop is usually applied to regenerate the clock
signal. For a narrow loop bandwi~dth design~ i~ usually requiras
expensive voltage controlled c~ystal oscillator aue to stability
proble~randd provides limited low frequency trac~ing ablility.
For a ~æ~ bandwidth design, phase and frequency of the clock
generated will be degraded (drifted) if there is a long term
of zero data input without transition.
The application of comparing a window signal and
a feedback signal has been men-tioned in U.S. Pat. No. 4,218,771.
However, the stated reference cannot carry ou-t -the suppressed
clock extraction as in my in~ention~s objective. ~urtn~rmore,
if both delayed and advanced feedback signals are within -the
~window's limits, there is no error compensation signal generated
to the voltage controlled phase shift even if there is phase
error existing. Another reference cited with CAN. ~at. No.
1,051,528 relates to a data recovery system mainly for .~ ~q
recording format. ~he stated invention may not stand for phase
deviation as required by general baseband communication. A
,. ....
n 1l e n ~/v~ '~
feedback phase shi~t logic is no-t rny ~vn~t~D~ intention.
~urt~ermore, its phase tracking range is limited and with
undefined regions which requires a leader signal of all unes
to train and long time of acquisition.
SU~ ARY OF TXE I~ENTION
In this invention, a broad bandwidth phase locked
loop can be applied to compare phases when there is a
transition signal in the incoming data. When -the input
signal~s data is zero during a particular clock time slot,
the comparison of phases is disabled. At this time, the
frequency/phase detector~output is off and the following 10W
pass ~ilter i~ kept idle. Thus the low pass filter la~ches
the las~ filtered DC signal to control the ~oltage controlled
oscillator. I~ the leakage o~ the ~ilter is low and the
oscillator's dri~ting is small, the loop's oscillator will
conti~ue to generate same ~requency as before and its phase
position will be kept.
a~
When there is~transition edge of incoming signal
available again, frequency/phase detector reacts again
immediately to generate a compensation s,ignal o~ any phase/
frequency error. An expensive voltage controlled c~ys~al
oscillator is not required because the phase error will be
compensatad by the broad pass band low pass filter during
transition comparison period. As a whole~ this invention
provides an equivalen~ low noise band phase locked loop
during zero da~a input while tracks the low ~requency jitter
by the broad loop bandwid-th phase locked loop during ones
da~a period.
BRIE~ DESCRIPTION OF ~HE DRAWINGS
A better un~erstanding o~ the inv-ention will be
obtained by re~erence to ~he description below, in conjunction
with the following drawings, in which:
Figure la is a block diagram of' a basic form of'
the in~ention,
Figure lb is a wa~eform diagram o~ t~e pre~erred
embodiment of the invention, and
Figure 2 is the schematic o~ a pre~erred ambodir.l~nt.
DE~AILE~ DESCRIPTION OF THE I~ENTIOM
Turning now to Figure la, a logical block diagram
shows basic apparatus essential to an understandi.ng of the
manner in which the in~ntion is implemented in more detailed
apparatus to be explained later.
An input source of suppressed clock modulated
signal with frequency and phase deviations which is intended
to have data clock signal regenerated is applied to inputs of'
delay device 1 and window generator 2. The output of delay
device 1 is connected to one input of f'requency/phase detector
4. The output of the windo~ generator 2 prPvides a control
signal enabling an edge signal of f'eedback clock through at
the feedback clock sampling latch 3. This feedback clock is
coming from voltage controllad oscillator 6. Output of
feedback clock ~ampling latch 3 is connected to ano~her input
--3--
of the frequency/phase detector 4 and -to an input of window
generator 2 so as to reset it. Output o~ the frequ6ncy /phase
detector 4 is filtered 'by a low pass filter 5. Filter's
output is connected to input of voltage controll~d oscillator
6.
When the delayed input signal receeds the qampling
latch 3's output, there i5 a positive pulse output from the
frequency/phase detector ~ with the duration representing the
p~ase di~ference. When the sampling latch~s output preceeds
the delayed input, there is a negative pulse ouput from
frequenc~/phase detector 4. Where there is no phase differe-
nce or no phase comparison, ou~put o~ frequency/phase detector
4 is off. Detail action can be observed in Figure lb.
'F~rthermorè, detector 4 also provides a means to detect
~requency dif~erence between two inputs for a case of start-up
or a sudden change of input!s ~requency.
The detector's output is smoothed by the low pass
filter 5 before reaching the voltage controlled oscillator 6.
~he filter may be implemented in passive or active form.
Turning now to ~igure 2, a detailed logic diagram
of the preferred form of the invention is shown.
The clock suppressed modulated input signal is
applied to input terminal of hal~ clock period delay device 10
and clock C termianl of window generator flip flop 11. If
the input signal's pulse duration is assumed to be about ~0
percentt the next opposite-edge of the signal can be used as
the hal~ clock period'delayed signal. m that case, half
clock period delay device 10 can be replaced by an in~erter.
`~~` The Q output of flip flop 11 is connected to ~Q D terminal
of flip flop 12. The Q ou~put of flip flop 11 is connected
to reset R terminal of flip flop 12. ~he Q output of flip
flop 12 is connected to reset R terminal of flip flop 11 and
an input o~ fr~quenc~/phase detector 13. The output terminal
of delay device 10 is connec~ed to another input of frequency/
phase detector 13~ The output termi~al o~ frequency/phase
detector 13 is connected to an input of a low pass filter 14.
The output terminal of the low pass filter 14 is connected to
an input terminal of the voltage controlled oscillator 15.
Resistor 16 is used to control the maximum frequency generated
by voltage controlled oscillator 15. rl~aximum frequency shoula
be less than two times the average of the recovered data clock
rate preventing locking to a higher harmonic frequency.
Resistor 18 is used to control the minimum ~requency generated
by voltage con~rolled oscillator 15. Minimum ~requency should
be more than half t~e average of t~e recovered data clock rate
providing a start-up fast acquisition and preventing locking
to lower harmonic frequenc~. ~he output terminal of voltage
controlled oscillator 15 is connected to clock C terminal of
sampling latch flip flop 12~ In a successful prototype, the
frequency/phase detector 13 was CD4046B which included the
charge-pump tri-state device and voltage controlled oscillator
inside. Of course, other equivalent device or discrete logic
can also be used. Flip flops ll and 12 are CD4013B.
In operation, the positive edge of input signal
causes window generator flip flop 11 output high. The feed-
back signal from voltage controlled oscillator 1~ sampling
-r~
J
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~`~`' this ~ P signal to cause the sampling latch 12 output high.
Thus this high transition is frequency/phase compared with the
hal~ clock delayed positive edge of input signal by frequency/
phase detector 13. At the sametime, sampling latch 12 Q
output is fed to reset the window generator flip flop 11 and
then the sampling latch 12 itself. ThUS there is a narrow
pulse generated at latch 12 Q output for frequency/phase
comparison. The reset of flip flop 11 using a narrow pulse
is to provide the capability of tracking of an instant ~180
degrees phase step input. During transitions comparison
period, the frequency/phase error signal is generated from the
oub,put of detector 15 in order to charge or discharge the low
pass ~ilter 14. ~he filtered signal is applied to input of
voltage controlled oscillator 15 to cause its frequency output
compensated. During zero data period, there is no transition
applied to detector 15 and thus its output is off. And the
low pass filter 14 will latch the last f;ltered DC output.
The output of voltage controlled oscillator 15 as the recovered
data clock is also fed back to clock ~ input of sampling latch
12.
A suppressed clock extraction circuit applying a
phase lco~d loop has been described. Various modifications
may appear to those skilled in the art possible without
departing from the spirit of the invention.
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