Note: Descriptions are shown in the official language in which they were submitted.
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This is a division o-E Patent Application No.
359,921, filed September 9, 1980.
The invention relates to the field of satellite
communications and relates to data rearrangement and
allocation among a plurali-ty of users in a time
multiplexed environment.
Prior art pulse code modulation IPCM) time
division multiple~ed (TDM) communications typically
involve sampling a plurality of channels in a sequence
of time and producing a digital word related to the
value of the individual channel so sampled. After
each of the channels has b~en sampled, the process
is repeated a number of times to produce a PCM frame.
Although this is a standard technique of providing
PCM/TDM data, the bit stre~m so organized is difficult
to handle for certain applications insofar as the
digital samples for the various channels are inter-
leaved. Furthermore, an interruption at a particular
point of time in the transmission of the data stream
will cause a temporary loss of information in sub-
stantially all of the communication channels.
The ground stations of satellite communications
systems generally involve a plurality of users at-
tached to the ground station transmitter through
common equipment. In prior art systems the plurality
of users of "interface modules" were multiplexed and
demultiplexed to and from the common equipment
generally by employing well-known multiplexers and
demultiplexers. The bus structures involved in the
multiplexing~demultiplexing operations ~ere configured
in a variety of ways such as the radial, party-line
(bus), or daisy chain configurations. These prior
s
art techniques are generally large in size and in-
flexible in nature. That is, -the channel allocation
for each burst of data for each of the interface
modules must be preset by the multiplexer/demultiplexer
and changes in channel and/or burs-t allocation for
any one of the interfaced modules requires a substan-
tial reorganization of the multiplex/demultiplex
operation.
The present invention provides an apparatus for
selectively multiplexing a plurality of data sources
with equipment common to each of the data sources,
which comprises a first memory means in each of the
data sources for receiving and storing input data at
a data rate, the first memory in response to an output
enable signal and a plural bit read address signal,
providing to the common equipment data specified by
the read address signal, the read address signal
having first and second portions; counter means in
the common equipment, the counter having a first
section providing the first portion of said plural
bit read address signal and a second section; second
memory means in each said.data source, the second
memory means receiving a plural bit.output from the
second counter section as.an address input and pro-
viding a corresponding second memory output the out-
pu~- of the second memory comprising the second por-
tion~of the read address signal.
The invention will be more readily understood
from the following description of an embodiment
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thereof given, by way of example, with reference
to the accompanying drawings, in which:
Figure 1 is a schematic illustration of a single
ground station having a plurality of PCM channel
5 banks and terr~strial inuerface modules in communica-
tion with common time division multiple access equip-
ment.
Figure 2 illustrates the interrelationship
between the common equipment and each of the terres-
trial interface modules Eor the transmit portion
of the ground station.
Figure 3 is an illustration of the interrela-
tionship between the common equipment and each of
the terrestrial interface modules for the receive
portion of the ground station equipment.
Figure 4 illustrates the PCM data ~hroughout
an entire TDMA frame.
Figure 5 illustrates the same PCM data re-
organized so as to pack an entire channel of data
into a contiguous block of time.
Figure 6 illustrates the format of an entire
frame of TDMA data transnitted from the ground station
to a satellite link.
Figure 1 is a schematic illustration of the
relevant portion of a TDMA circuit. A plurality
of analog channels which may be comprised of simple
telephone lines for example are input to an associated
1 out of n PCM channel banks lOa through lOn. Each
PCM channel bank converts the parallel analog input
signals to pulse code mo~ulated (PCM) time division
multiplexed (TDM) serial bit streams which are ap-
plied to an associated 1 out of n terrestrial inter-
face modules (TIM) 15a through 15n. Under the selec-
tive control of common TDMA ~time division multiply
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access) equipment 25, the data from the appropriate
TlM is delivered to bus 20 at the proper time where
it is then delivered to the common TDMA equipment
25. The common TDMA equipment 25 processes the
data so provided and delivers it to a modulator.
The processing involved in the common TDMA equip-
ment and subsequent modulation does not represent
a part of the subject invention.
Data returning to the common TDMA equipment
25 from the demodulator is applied to the appro-
priate TIM module through bus 20 at the proper time.
The appropriate TIM module is selected by the com-
mon equipment 25 by providing an address to all
of the TIM modules simultaneously; the particular
address so provided will cause the data to be written
into only one of the TIM modules 15a through 15n.
The data words provided to the TIM modules 15a
through 15n are subsequently delivered to PCM
channel banks lOa through lOn where they are de-
multiplexed and provided as a plurality of parallel
analog signals from each of the channel banks.
An embodiment of the invention is described
in greater detail with reference to Figures 2 -
5. Figure 2 illustrates the transmit portion of
one of the TIMs of Figure l and the associated com-
mon TDMA equipment with which it communicates
through the bus structure 20. The PCM encoded
data is delivered to PCM frame synchronization
means 30 which detects the position of each PCM
frame and delivers a frame synchronization signal
to counter 35 which is clocked at a
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rate equal to the PCM data word rate~ The various synchronizat-
ion signals referred to throughout this specification may be
provided in any well-known manner. The PCM encoded data is then
delivered to serial to parallel converter 40 where the serial PCM
data is converted to a parallel format. The parallel ~CM data is
delivered along an 8 bit data bus to one of two tri-state
compression buffers 45 or 50 under the selective control of write
enable pulses delivered to one of the compression buffers from
flip-flop means 52. The flip-flop means 52 iS synchronized with
the TDMA frame in a well-known manner and provides a "ping-pong"
action between compression buffers 45 and 50. The PCM data is
written into one of the buffers 45 or 50 at a location determined
by counter 35 which provides an address along the write address
bus.
Contemporaneously with the write operation in one of
compression buffers 45 and 50, a read operation is performed on
the other compression buffers 45 and 50 under the control of
flip-flop means 52, mapping RAM 55 and AND gates 54 and 56. The
mapping RAM 55 provides the output enable signal OE whenever
data is to be read into one of compression buffers 45 and 50.
The signal OE is further combined with the write enable signals
WE 45 and WE 50 in AND gates 54 and 56 so that data is output
from the compression buffer which does not have a write enable
signal applied to it at that particular point in time. The data
from the other of compression buffers 45 and 50 is read from an
address provided on the read address bus as shown in the figure.
The read address is provided from both the counter circuit 57 in
the common TDMA equipment which counts at a clock rate equal to
the ~DMA data word rate and form mapping RAM 55. The common
TDMA equipment provides address bits Ao~ Al, A5, A6 and A7 while
mapping RAM 55 provides bits A2 through A4.
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The data is rearranged upon reading from compression
buffers ~5 or 50 in a manner explained with reference to
Figures S a~d 6. Figure ~ illustrates the data bit stream
of 8 bit parallel PCM data provided from serial to parallel
converter 40 to one of col1pression buffers 45 or 50. ~ach
of the PCM channel banks :LOa through lOn, Figure 1, pro-
vides 24 channels of PCM data to the TIM. Each of the
channels in one PCM frame comprise a single 8 bit sample
~rom the individual channel. The time division multiplexed
nature of the PCM frame i3 illustrated in Figure 4 where
it is seen that an 8 bit ~lata sample from channel 1 is
imlQediately followed by an 8 bit data sample from channel 2
and so on through channel 24. The PCM frame repeats itself
upon reaching channel 24 wherein the next 8 bit sample will
be from channel 1; In th:Ls manner, a single TDMA frame
comprised of 6 sequential PCM frames (total of 750 ms) is
established. It should be noted that the number of PCM
frames contained in a TDMA frame is a matter of choice
and can be varied to accollmodate the user's needs.
Figure 4 also illustrates the address allocated to
each of the PCM data samp:!es from each of the channels.
Since there are 24 channe:!s in a single PCM frame, the
particular channel in a PCM frame can be identified with a
minimum of 5 bits (2 = 3:'), namely, Ao through A4. The
particular PCM frame that the channel is contained in can
be identified by a minimum of 3 bits (23 = 8), namely, A5
through A7. In other words, bits Ao through A4 indicate to
which of channels 1 through 24 the 8 bit sample belongs,
while bits A5 through A7 :indicate to which of the PCM
frame numbers 1-6 the 8 b:it sample belongs. The bits Ao
through A7 are provided to write address inputs of com-
pression buffers 45 and 50 by means of counter 35 synchro-
nized to each of the PCM 8 bit samples as discussed with
reference ~o Figure 2. The address bus fro,-n counter 35 is
tied to the write input l:Lnes of buffers 45 and 50 so as
to make bit Ao the least significant while A7 is the most
significant bit.
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The data is read out of the other of compression
buffers 45 or 50 under the control of the read address bus
which ls provided with a portion of the address by mapping
RAM 55 and a second porti~n of the address from the common
TDMA equipment. The blts Ao through A7 are provided to
the compression buffers 45 or 50 in an order dif'erent than
that provided for the write address. Specifically, with
reference to Figure 5, it is seen that the address is com-
prised of address bit A5 as the least significant bit in
the address followed by A6, A7 and Ao through A4, A4 being
the most significant bit. Leading the data out of memory
in this manner effects a reorganization of the data so as
to pack all the bits associated with a single channel into
a single contiguous block of time for an entire TDMA frame.
This structure allows the data mapping, described below, to
be independent of the number of PCM frames in a TDMA frame
length.
A comparison of Figures 4 and 5 illustrates how this
reorganization is achieved. Reiterating, bits Ao through
A4 indicate from which of the 24 channels the 8 bit data
sample belongs while ~its A5 through A7 indicate in which
of the PCM frames within a single TDMA frame the sample
belongs. The 8 bit data samples are read out of memory
under the control of counter 57 having address bits A5
through A7, Ao and A2 as outputs, and mapping RAM 55 having
A2 ~ A4 as outputs, A5 being the least significant bit and
A4 being the most significant bit in the address. Inasmuch
as bits A5 through A are cycled through before bits Ao
through A4, 8 bit samples from a single channel (defined by
Ao through A4) will be sequentially read from compression
buffers 45 or 50 from consecutive PC.~ frames 1 through 6
as defined by A5 through A7. As the first channel sample
is read out of memory from the slx PCM frames, counter 57
which delivers the bits A5 through A7 will reset and bits
Ao through A4 ~ill increment so that the next channel will
be read out from each of the six PCM frames within the TDMA
frame. Bits Ao - A4 will similarly reset upon counting 24
channels.
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The reorganized data shown in Figure 5 illustrates
that an entire PCM channel (channel "8" for example) is
now "packed" within a single block of time. As each of
the channels is so packed, the data is rearranged in con-
S secutive channels as shown and grouped into blocks offour channels defined by the bits A2 through A4, three
bits defining one of six blocks of data. The particular
channel within any one of the blocks is defined by bits
Ao and Al.
Referring to Figure 1, rearranged data is delivered
to the remaining TDMA system, via the common TDMA equip-
ment, where it is transmitted to a communications satel-
lite. Data returning to the common TDMA equipment 25 from
a communications satellite is delivered from the common
TDMA equipment 25 to the various TIMs 15a through 15n
along bus structure 20. The received portion of the
various TIM's common equipment and the associated bus
structure are illustrated in Figure 3. Address bits A5 -
A7, Ao and Al are delivered from the counter 66 in the
T~MA common equipment directly to the write address bus,
while bits A2 ~ A4 are delivered to the address bus from
mapping RAM 65. The data from the common TDMA equipment
is applied to the 8 bit data bus as shown in Figure 3.
Data is written into one of expansion buffers 70, 75 under
the control of write enable pulses WE 70 and WE 75 pro-
duced by AND gates 74 ancl 76. The flip-flop 72 is operated
synchronously with the TDMA frame in a well-known manner
to produce output enable pulses OE 70 and OE 75 and pro-
vides the "ping-pong" operation of expansion buffers 7n
and 75 similar to the "ping-pong" operation of compression
buffers 45 and 50. The write address bus is hard wired to
buffers 70 and 75 so tha~: bit A5 constitutes the least
significant bit of the address while bit A~ is the ~ost
significant bit. In this, manner, the data is written into
the expansion buffer 70 and 75 in the same manner as it
was read out of compression buffers 45 and 50.
Contemporaneously wLth the above-mentioned write
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operation into one of expansion bu,ffers 70 and 75, a read
operation is effected in the other of the expansion buffers.
The read address delivered to the expansion buffers is
produced by counter 85 synchroni~ed in a well-known manner
with the unique word contained in the preamble of the burst
illustrated in Figure S and clocked at the PCM data word
rate. Bits Ao through A7 in the read address are hard
wired to the expansion buffers 70 and 75 so that bit Ao
is the least significant bit and bit A7 is the most signif-
icant bit. In this manner the data is rearranged from theformat illustrated in Fi~ure 5 to the terrestrial side
format illustrated in Fi&ure 4. The data so read out of
the other of expansion buffers 70 and 75 is delivered to
parallel to serial converter 80 to provide a serial bit
stream of PCM data to one of the associated PCM channel
banks lOa through lOn.
The address mapping function of mapping RAMs 55, 65
and 67 will now be discucsed. In Figure l, it is seen
that a multiplexing and cemultiplexing operation must be
effected between the plurality of TIMs 15a-15n and the
common TDMA equipment 25. Prior art techniques employ
standard multiplexer/demultiplexer systems which are large
in size and inflexible ir, nature. That is, the channel
allocation for each burst of data for each TIM must be
preset by the multiplexer and changes in channel and/or
burst allocation for any one of the TIMs requires a sub-
stantial reorganiæation of the multiplex/demulciplex
operation.
The TIM bus structure of the present invention em-
ploys the mapping RAMs 5S, 65 and 67 so that channel and
burst allocation for the TIMs can be changed in real time,
and the flexibility of the channel and burst allocation is
greatly enilanced over the prior art systems.
With reference to Figure 2, the mapping operation of
the transmit portion of the TIM bus scructure will be
descrlbed. As noted above, the counter 57 counts at the
TDMA data rate, and is
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synchronized with each burst by means of the unique word
synchronlzation signal, 'rhe counter 57 is comprised of
three portions: a first ,livide-by-6 portion having a 3 bit
output and connected to a second divide-by-4 porticn having
a 2 bit output. The divi,ie-by-4 portion of counter 57 is
further connected to a divide-by-192 portion having an 8
bit output. The divide-by-6 portion of counter 57 com-
prises the least significant bits in the counter A5, A6
and A7, which correspond to the identification of the PCM
frame number of the PC:~ word currently being read fro~
one of compression buffers 45 or 50 (see Figure 5). The
next two bits Ao and Al, the outputs from divide-by-4
portion of counter 57, indicate in which of the four
channels within the six blocks of the PCM data word
currently being processed belongs. The 8 bit output of
the next portion of counter 57 indicates which block of
data is currently being read from one of compression
buffers 45 or 50. With reference to Figure 5, it is noted
that each TIM typically contains 24 channels of data, the
channels being divided up into six blocks of four channels
each. Inasmuch as the example used in accordance with the
present invention employs up to 32 TIMs, there are 192
(6 x 32) blocks which must be identified within any one
burst of data. The divide-by-192 portion of counter 57 so
defines the particular block of data within the entire
burst which is presently being read out of one of compres-
sion buffers 45 or 50.
The ~ bit block identification number is delivered to
mapping RAM 55 which is contained in each of the TIMs 15a
through 15n. Each of the mapping RAMs in the TIMs are
individually programmed so as to recognize the particular
block of data defined by the 8 bit identification number,
and to provide the output enable signal OE whenever the
mapping RAM determines that its associate TIM should pro-
vide that particular block of data. This represents asimple decoding of the block number by each TIM and pro-
vides the TIM with the information as to when it should
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transmit data to the common equipment. For example, TIM
No. 10 can be assigned to transmit data on blocks 5, 150
and 151 by having the mapping RAM 55 in TIM No. 10 simply
recognize blocks 5, 150 and 151 from the 8 bit input from
counter 57 and deliver the output enable signal in response
thereto.
Insofar as mapping RAM 55 for each of the TIMs "knows"
which of the 192 blocks is currently being processed, in
addition to providing the output enable signal, it can be
further programmed to provide bits A2 to A~ to the read
address since these bits define which of the si~ blocks of
data is being processed by the individual TIM. In the
example shown in Figure 5l a count of "150" from divide-by-
192 portion of counter 57 would produce a "block 1" indi-
cation from bits ~2 - A4. As counter 57 increments to
indicate that block 151 i3 being processed, mapping RAM 55
would indicate "block 2" on bits A2 ~ A4.
It can now be seen that the mapping RAM arrangement
allows the allocation of any one of the 192 blocks of data
to any particular TIM in any particular order. Each of the
four channels of data contained in any one of the blocks so
processed by the TIM contains the entire channel informa-
tion for an entire PCM frame. The subsequent addition or
changes to the number of PCM channels, therefore, has
little effect on the entire PCM/TDM system. Any changes
needed to compensate for changes in system requirements can
be accomplished by simply reprogramming the mapping RAMs
55 which are in communication with a central processing
unit as shown. Th:is reprogramming of the mapping RA~s
can also effect a simple change in channel allocation as
desired.
The receive portion of the TIM bus s~ructure will be
discussed with reference to Figures 3 and 6. Figure 6
illustrates the general format of an entire frame of TDMA
data. The TDMA frame consists of a series of bursts, each
burst provided by a uniq~le ground station.
Each of the ground stations in communication with the
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transponding satellite can select the particular stations
from which it receives data. The TIMs on the receive side
of the terrestrial station can further choose which of the
channels (in blocks of 4) it wishes to receive from any one
of the station bursts within the TDMA frame. The common
TDMA equipment as shown in Figure 3 consists of a 4 bit
burst counter 68 which is clocked by the burst synchron-
ization signal which is provided in a well-known manner.
In this way the counter 68 keeps track of which particular
burst is currently being received by the common equipment
and delivers this information in 4 bits to mapping RAM 67.
Counter 66 is similar to the counter 57 of Figure 2 and
keeps track of which'PCM'frame number, channel number and
block number is currently being received by the common
equipment. The mapping R.AM 67 is programmed first to
recognize the particular burst from which is desired to
receive information. It should be noted that with the
arrangement of mapping RA.Ms shown in Figure 3, any one of
the TIMs in the associate.d terrestrial station can receive
information from any combination of the plurality of
bursts illustrated in Fig,ure 6 by programming the mapping
RAM to provide the appropriate output when the chosen burst
is being received. Mappi.ng RAM 67 further keeps track of
which of the 192 blocks c,f information is currently being
~5 received within the parti.cular burst as indicated.by
divide-by-192 portion of counter 66. Whenever mapping RAM
67 determines that the ps.rticular block of information in
the particular burst presently being received by the common
equipment corresponds to a block of data which is to be
received by one of the T]:Ms, it produces a l bit output
which is applied to AND gate 77. The output of divide-by-
4 portion of counter 66 i.s also applied to the second input
of AND gate 77. The 1 bi.t output from mapping RAM 67 (low
in this case~ allows the AND gate 77 to pass the clocked
count from counter 66 to counter 76. This arrangement
effects an initialization of the block count in counter 76
so that block No. 1 from burst I will not be confused with
block No. 1 from burst I + 1. In other words, the counter
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76 will sequentially reorganl2e the blocks of data which
are to be received by the common equipment over t~e entire
TDMA frame as shown in Figure 6. The counter 76 counts
to a maximum of 192 blocks for reception and delivers the
8 bit block count to each of the receive portions of TIMs
15a through 15n. The mapping RAM 65 of each of the TIMs
"recognizes" the particular reorganized block of data
presently being delivered on the 8 bi~ data input line
from the common equipment and produces a write enable
pulse whenever that particular block of data is assigned
to the associated TIM.
The mapping RAMs 55, 65 and 67 are programmed to
provide the above-mentioned input/output functions in a
manner well-known to those skilled in ~he art. Table I is
provided to illustrate one of the many schemes of program-
ming RAMS 55 or 65. The memories are provided with a 4 bit
output corresponding to bits A2 through A4 and the enable
output. These outputs are located in loc;ations of
memory defined by the 8 bit address. In the example
shown in Table I, the mapping RAMS 55 or 65, respectively,
read or write in response to blocks 6, 32 and 33. When
these blocks are indicated on the 8 bit input lines to
RAMs 55 or 65, each RAM will output the appropriate enable
signal to effect an output or write operation and will
further provide bits A2 through A4. The example shown in
Table I assigns block 6 (out of 192 blocks) as block 6,
block 32 as block 2 (bits A5 through A7, Ao and Al have
changed since block 6), and block 33 as block 3. The
particular assignment of blocks in the mapping process is
a matter of choice and merely requires that the users keep
track of the particular assignments. The programming of
mapping RAM 67 is simplified insofar as it need on]y
produce a 1 bit output corresponding to the proper block
and burst for reception.
Mapping RA~Is 55, 65 and 67 are connected to a CPU
whereby a reorganization of the data selected by any one
or all of the TIMs can be effected. A simple reprogram-
ming of mapping RAMs 67 can change the burst or bursts
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TABLE I - R.~M 55 OR 65
OUTPUT BITS
8 BIT Address (Block No.) A2A3A4 Enable/Disable
00000000 (O) XXX D
lO OOOOOllO (6) 110 E
OOOOOlll (7) XXX D
OO100000 (32) OlO E
OOlOOOOl (33) Oll E
OOlOOOlO (34) XXX D
2n
from which information is received at the TIMs so that
the TIMs can receive information from any terrestrial
station contributing a burst to the TDMA frame. The
particular block of ~ata within any one of the selected
bursts can also be select:ed by any one of the TI~Is through
a simple reprogramming oi. mapping RAM 65 by the CPU in a
manner similar to that oi the transmit mapping RAM 55,
Figure 2.
Thus, there is provi.ded a technique for perform-
ing a data reorganization so as to "pack" an entire
PCM channel within a single block of time. A plurality
of mapping RAMs are also provided to effect a compact
and flexible bus structure for interfacing a plurality
of TIMs with common TDMA equipmentO
