Note: Descriptions are shown in the official language in which they were submitted.
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The present inven~ion relates to a differential amplifier made of N-
type MOS (metal oxide semiconductor) field effect transistors and having the
differential to single-ended conversion capabllity.
A differential amplifier finds its use in operational (O~ amplifiers,
which may be fabricated on a single chip of silicon substra~e using the MOS-
integration circuit (IC) technique. This TC technique ena~les t~e integration
density for the single chip to be enhanced three to five ~imes as high as that
achieved by the bipolar-transistor IC technique.
Field effect transistors (FET's) manufactured by the MOS-IC technique
are generally classified into N-type MOS FET's (NMOS PET's), P-type MOS FET's
(PMOS FET's), and complementary MOS FET's (CMOS FET's). An NMOS FET is featured
by its operational speed, which is nearly three times as high as a PMOS FET.
It has an advantage of permitting a higher degree of circuit integration than a
CMOS FET.
An example of the above-mentioned OP-atnplifier made of NMOS FET's is
proposed in a paper entitled "Some Design Aspects on M.O.S. L.S~I. Operational
Amplifiers" by Bernd Hoefflinger et al., published in the Solid-state and
Electron Devices, Vol. 3, No. 2, pp. 33 - ~O~ March 1979 (Reference 1). However,
those operational amplifiers proposed therein are operable only within a narrow
frequency band for reasons to be described later.
An object of the present invention is, therefore, to provide a dif-
ferential amplifier operable over a significantly broader frequency band.
According to the present invention, there is provided a differential
amplifier comprising: a differential amplifier portion having a first NMOS FET
having a gate electrode connected to a first input terminal, a drain electrode
providing a first OUtp~lt of said differential amplifier portion and a source
electrode, a second NMOS FET having a gate electrode connected to a second input
~L15 0~3
terminal, a draiJI electrode connected to an output terminal for providing a
second output oF the different;al amplifier portion and a source electrode con-
nected to the source electrode of the first NMOS FET, first load means connected
to the drain electrode of the first NMOS FET, second load means connected to the
drain electrode of the second NMOS FET; and a differential to single-ended con-
verter portion including a third NMOS FET having drain and gate ~lectrodes for
receiving the first output and a source electrode which is grounded, a fourth
NMOS FET having a drain electrode for receiving the second output, a gate elec-
trode connected to the gate electrode of the third NMOS FET and a source elec-
trode which is grounded, whereby the first and second outputs are converted into
one output to be taken out from the output terminal.
This invention will now be described in detail in conjunction with the
accompanying drawings in which:
Figure 1 is a circuit diagram of an embodiment of the invention;
Figure 2 shows a graph illustrating the frequency-gain characteristics
achieved with the embodiment of the invention and the differential amplifier
proposed in Reference l; and
Figure 3 shows an example of one application of the present invention.
In the drawings, an FET with a thick line between the source and drain
thereof depicts a depletion-type NMOS FET, whereas an FET with a thin line
therebetween represents an enhancement-type NMOS FET.
Referring now to Figure 1, one embodiment of the invention comprises
a differential amplifier portion having a first FET 3 having the gate electrode
connected to a first input terminal 8, and the drain electrode for providing a
first output of the amplifier, a second FET 4 having the gate electrode connect-
ed to a second input terminal 9, the drain electrode connected to an output ter-
mînal 10 for providing a second output of the amplifier. The source electrode
- 2 -~
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of FET 4 is connected to the source electrode of the FET 3. A first load com-
prising an FET 1 has its source electrode connected to the drain electrode of the
FET 3, and a second load comprising an FET 2 has its source electrode connected
to the drain electrode of the second FET 4. The present embodiment also has a
differential to single-ended converter portion including a third FET 5 having
the drain and gate electrodes for receiving the above-mentioned first output and
the source electrode grounded~ a fourth FET 6 having the drain electrode for
receiving the above-mentioned second output, the gate electrode connected to the
gate electrode of the third FET 5 and the source electrode grounded. The dif-
ferential to single-ended converter is adapted to convert the first and second
outputs from the differential amplifier portion into one output appearing at the
terminal 10. The grounded source electrodes of the FET's 5 and 6 contribute to
provide the larger conductance gm for each of the FET's 5 and 6. ~n FET 7 serv-
ing as a current source has the gate electrode connected to a direct current
(DC) bias voltage source, and the source electrode connected to a voltage source
Vss. The drain electrodes of the ~ET's 1 and 2 are commonly connected to a vol-
tage source VDD. Since each of the pET's 1, 2, 3, 4 and 7 has the same s~ructure
as each of the FET's Tl to T5 described in Figure 5 of Reference 1 mentioned
above, further description will be omitted.
With such a structure, voltages Vinl and Vln2 given to the input
terminals 8 and 9 are differentially amplified in the FET's 3 and 4 and taken
out from the drain electrodes of the PET~s 3 and 4 as differential outputs Vl
and V2, respectivel~. The outputs Vl and V2 are converted into a single output
VOUt through the FET's 5 and 6 functioning as the above-mentioned single-ended
converter and taken out from the terminal 10.
Next, referring to Pigure 2, the reason why the embodiment shown in
Figure 1 can operate over a significantly broader frequency band, will be de-
scribed below. It is assumed now that the inp~t voltages at the input terminals
-- 3 --
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1 and 2 are Vi 1 and Vin2, the voltage appearlng at the dra.in electrode of the
FET 3 is Vl, the output voltage of the terminal 10 is V0, the currents flowing
-from the source VDD to the draln electrodes of the FET's 1 and 2 are Il and I2,
the drain currents from the FET's 5 and 6 are I5 and I6, the transconductances
o~ the FET's 1 to 6 are gml to gm6, and the backgate conductances of the FET's
1 to 6 are gmbl to g b6. Under the assumption mentioned above, if the input
voltage Vinl is equal to ths input voltage Vin2 in operation, the relationship
of Vl = V t~ Il, = I2, and I5 = I6 hold. Further, if the length and the width
of the gate electrodes of all the PET~s 1 to 6 are identical, the following
relation holds between the respective conductances gml to gm6 and gmbl to gmb6
of the FET's 1 to 6:
gml gm2' gm3 gm4' gm5 gm6'
gmbl gmb2~ gmb3 gmb4' gmb5 gmb6'
The gain A of the amplifier shown in Figure 1, in consideration of
those conditions mentioned above, is generally expressed by equat~on
A = ~ 2 m3 (1 ~ m5 3
20lgl"l (1 gm5 ~ ~lgml ...... (1)
where
~VT
~VSBl
VTl: a threshold voltage of the FET 1
VsBl: a voltage between a substrate ~not shown) and
the source electrode the FETl formed on the
substrate.
Next, if the load capacitance to be produced to the output terminal
10 is assumed to be CLo~ then the frequency characteristic of the gain A may be
obtained by equation (2):
-- 4 --
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(~lgml j L0) gm5 ~lgml ... (2)
In the equation (2), if gmS>> gml~ the gain A can be written by
equation (4a):
gm3
~lgml j L0 ,...,. (4a)
The cut-off frequency fco at this time is depicted by equation (4b):
fco 2~ C~0 ........................................... (4b)
The gain Al of the differential amplifier portion (consisting of
the FET's Tl to T~) shown in Figure 5 of Reference 1 is obtained as in equation
(5) when each of the FET's Tl to T4 is structurally identical with each of the
FET's 1 to 4 used in the invention.
gm3
~1 gml = jw CLl ................................. (5)
wherein CLl denotes the load capacitance of the OUtpllt of the portion ~FET's
Tl to T4).
The frequency characteristic of the gain A2 in the differential to
single-ended converter portion ~FET's T6 to Tg) (shown in Figure 5 of Reference
1) is then given as follows:
A2 2 g 6 ~ 6) + jw CL2 [ 1 g 6 (1 ~6)~ ( )
wherein CL2 is the load capacitance of the output of the differential to single-
ended converter portion (FET's T6 to Tg); and
_ aVT6
~6 avsB6
VT6: a threshold vol*age of the FET T6
VsB6: a voltage between a substrate (not shown)and
-- 5 --
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the source electrode of the FET T6 formed
on the su~strate.
The cut-off frequencies fCl and fc2 of the differential amplifier
shown in Figure 5 of Reference lcan be expressed by equations ~7) and ~8):
cl 2~ CLI ...................................... ~7)
f = gm6 ~ ~6) ................................... ~8)
For details of each derivation of the above-mentioned equations for
the gains A, Al, and A2, and the cut-off frequencies fco~ fCl~ and fC2, refer-
ence is made to "Design Consideration in Single-Channel MOS Analog Integrated
Circuits - A Tutorial", by Yannis P. Tsividis published in the IEEE Journal of
Solid-State Circuits, Vol. SC-13, pp. 383 - 3917 June, 1978 ~Reference 2).
Now turning to Figure 2, the frequency-gain characteristic achieved
with the invention (see equation (4 ea)) clearly shows that the present ampli-
fier can operate within a considerably broader frequency band. This is easily
confirmed from the fact that the present amplifier has a larger zero-crossing
frequency fOl ~at which the gain is O dB) than a corresponding one fo2 of Ref-
erence 1.
The differential amplifier of the present invention, designed on the
basis of the structure of Figure 1 to have a maximum gain of 30 dB, has a cut-
off frequency fco (equation (4b~) of 30 KHz and a zero-crossing frequency fOl
~equation (4a)) of 1 MHz. On the other hand, the differential amplifier accord-
ing to Reference 1 has a cut-off frequency f 1 (equa~ion (7)) of 30 KHz, a cut-
off frequency fc2 (equation (8)) of 200 KHz, and a zero-crossing frequency fo2
(equation (6)) of 500 KHz, when designed to achieve the same gain.
Referring to Figure 3 which shows an application of the invention,
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an OP-amplifier comprises the difEerential amplifier 100 shown in Figure 1, a
second stage 200 for amplifying the output of the amplifier 100, and an output
stage 300 for performing the class A push-pull operation. The second stage 200
includes an FET 10 to form a negative feedback amplifier; an FET 9 serving as
the load resistance of the FET 10; a capacitor for frequency compensation of the
negative feedback amplifier; and an FET 8 serving as a resistance element for
preventing the reduction of frequency band width. The output stage 300, on the
other hand, has FET's 17 and 18 to function as a class A push-pull amplifier,
and a Mirror circuit composed of FET's 13 and 16 for giving a signal of a phase
opposite to the input signal appearing at the FET 17 to the FET 18. An FET 12
functions as a resistance element, whereas an FET 15 is used to lower the output
impedance of the FET 18 by feeding back the output of the FET 18 to the input
thereof.
Since the operation of the OP-amplifier of Figure 3 is similar to that
of the OP-amplifier shown in Figure 5 of Reference 1 except that the OP-amplifi-
er of Figure 3 can operate within a comparatively broader frequency band, a
detailed description will be omitted.
