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Patent 1181668 Summary

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(12) Patent: (11) CA 1181668
(21) Application Number: 448584
(54) English Title: METHOD OF PREFERENTIALLY ETCHING OPTICALLY FLAT MIRROR FACETS IN INGAASP/INP HETEROSTRUCTURES
(54) French Title: METHODE D'ATTAQUE SELECTIVE POUR L'OBTENTION DE FACETTES DE MIROIR OPTIQUEMENT PLATES DANS DES HETEROSTRUCTURES INGAASP/INP
Status: Expired
Bibliographic Data
(52) Canadian Patent Classification (CPC):
  • 149/6
(51) International Patent Classification (IPC):
  • H01L 21/308 (2006.01)
(72) Inventors :
  • COLDREN, LARRY A. (United States of America)
  • FURUYA, KAZUHITO (United States of America)
(73) Owners :
  • WESTERN ELECTRIC COMPANY, INCORPORATED (Not Available)
(71) Applicants :
(74) Agent: KIRBY EADES GALE BAKER
(74) Associate agent:
(45) Issued: 1985-01-29
(22) Filed Date: 1982-06-23
Availability of licence: N/A
(25) Language of filing: English

Patent Cooperation Treaty (PCT): No

(30) Application Priority Data:
Application No. Country/Territory Date
276,942 United States of America 1981-06-24

Abstracts

English Abstract




METHOD OF PREFERENTIALLY ETCHING OPTICALLY FLAT
MIRROR FACETS IN InGaAsP/InP HETEROSTRUCTURES

Abstract of the Disclosure
Highly reproducible, optically flat mirror facets
are created by etching a predetermined area of the
InGaAsP/InP heterostructure system to expose a
crystallographic surface throughout the entire
heterostructure system. Contact of the exposed surface
with HCl causes a preferred crystallographic plane to be
exposed as an optically flat mirror facet.





Claims

Note: Claims are shown in the official language in which they were submitted.



Claims:
1. A method for etching a multilayer semiconductor
heterostructure body having alternating layers of InGaAsP
and InP,
CHARACTERIZED BY
etching a given surface of the semiconductor body
with a material selective chemical etchant to expose a
portion of a crystallographic surface of an InGaAsP layer
and an abutting InP layer,
etching the exposed InP layer with HCl to expose a
preferred crystallographic plane thereof and an abutting
InGaAsP layer, the preferred plane being substantially
coplanar with the exposed portion of the InGaAsP crystal-
lographic surface, and
iterating the aforesaid processing steps to provide
an optically flat mirror facet across four of said alter-
nating layers.
2. The method as defined in claim 1 wherein the
chemical etchant is AB etchant.
3. The method as defined in claim 1 wherein the
chemical etchant is H2S04:H202:H202 = (10:1:1).
4. The method as defined in claim 1 wherein the
chemical etchant is a solution of KOH:K3Fe(CN)6:H2O.

-13-





Description

Note: Descriptions are shown in the official language in which they were submitted.



-- 1 --

METHOV OF PREFERENTIALLY ETCHING OPTICALLY FLAT
MIR~OR E'ACE~S IN InGaAsP/InP HETEROST~UCTllRES

Technical Field
_ . . ... ...............
This invention relates to a method of chemical
etching an optically flat facet Oll a preferred
crystallographic plane of a multilayer InGaAsP/InP device.
Backqround of the Invention
,
In general, an optoelectronic device such as a
laser is fabricated along a preferred crystallographic
direction. Mirror facets for uch a device are formed on a
plane perpendicular to the preferred directlon and
sidewalls of the device are formed on planes parallel to
that direction. Also, it is desirable for at least the
mirror facets to exhibit the characteristic of optical
flatness.
Optically flat mirror facets are created by
manual cleaving or by etching. Thou~h manual cleaving does
produce high quality mirror facets, this technique has a
low yield.
Etchin~ methods encompass both wet and dry
chemical etching. Wet chemical etching techni~ues
generally cause mask undercutting thereby no~ producing the
desired flatnessO Examples of wet chemical etching
techniques are given in the following references: K Iga
et al., "GaInAsP/InP DH Lasers witll a Chemically Etched
Facet," IEEE Journal of Quantum Electronics, QE-16, p. 1044
(1980), (a solution of HCl: CH3COOH: H202 = (1:2:1));
P. D. Wright et al., "InGaAsP Double Heterostructure Lasers
(A = 1.3~m) with Etched Reflectors," Applied Physics
Letters, Vol. 36, p. 518 (1980), (a solution of Br: CH30H);
and S. Arai et al., "New 1.6 ~m Wavelength GaInAsP/InP
Buried Heterostructure Lasers," Electronics Letters,
Vol. 16, p. 349 (1980), (a sequential process of Br: C~130H
followed by 4~1Cl-H20).

;~L~16~
-- 2 --

Dry chemical etching techniques include reactive-
ion etching, reactive-ion beam etching and plasma etching.
For separate descriptions of each of the above, see R. E.
Howard et al., "Reactive-Ion Etching of III-V Compounds,"
Topical Meetin~ on Inte~rated and Guided Wave Optics Di~est
~ . _
(IEEE: New York 1980) WA-2; M.A. Bosch et al., "Reactive-
Ion Beam Etching of InP with C12," Applied ~y~
Letters, Vol. 38, p. 264 tl980); and R. H. Burton et al.,
"Plasma Separation of InGaAsP/InP Light-Emitting Diodes,"
Applied Physics Letters, Vol. 37, p. 411 (1~80~.
Reactive ion etching avoids some of the problems of
the wet chemical etching methods and is useful in making
grooves in a heterostructure system. This type of etching
is effectively a single step process which results in
facets which are approximately planar but "overcut". That
is, the facets which form the groove slope toward each
other from the top of the groove to the bottom. Although
these facets are reproducible, they lack the optically
flat mirror quality necessary for certain applications.
Similarly, the other dry etching techniques create facets
satisfactory for use as waveguide sidewalls and die separ-
ations but lack the optically flat mirror quality necessary
~or optoelectronic and integrated optics devices.
Summarx~ the Invention
According to the invention there is provided a
method for etching a multilayer semiconductor heterostruc-
ture body having al~ernating layers of InGa~sP and InP,
characteri2ed by etching a given surface of the semicon-
ductor body with a material selective chemical etchant
to expose a portion of a crystallographic surface of an
InGaAsP layer and an abutting InP layer, etching the
exposed InP layer with HCl to expose a preferred crystal-
lographic plane thereof and an abutting InGaAsP layer, the
preferred plane being substantially coplanar with the
exposed portion of the InGaAsP crystallographic surface,

- 2a - -

and iterating the aforesaid processing steps to provide an
optically flat mirror facet across four of said alternat-
ing layers.
Other aspects of this invention are claimed in our
copending Canadian patent application Serial No~ 405,781
filed on June 23, 1982 o~ which the present application
is a division, and in other divisions thereof.
Brief Description of the Drawin~s
FIG. 1 shows a portion of a multilayer semiconductor
heterostructure body having a stripe-mask thereon;

6~


FIGS~ 2 and 3 show structural changes of the
semiconductor body in FIG. 1 after successive steps in a
first exemplary etching metl~od embodying the invention;
FIG~. 4~ 5, 6 and 7 show structural changes of
the semiconductor ~ody in FIG. 1 after each of four
sequential steps in a second exemplary etching method
embodying the invention;
~ IGS. 8, 9, 10 and 11 illustrate structural
changes of the semiconductQr body in FIG. 1 after each of
four se~uential steps in a third exemplary etching method
embodying the invention;
FIG. 12 shows a portion of a multilayer
semiconductor heterostructure body ~aving a stripe-mask
thereon in a direction different from that in FIG. l; and
FIGS. 13, 14 and 15 show structural changes of
the semiconductor body of FIG. 12 after each of three
successive steps in a fourth exemplary etching method
embodying the invention~
Detailed Description
-
Optoelectronic and integrated optics devices are
grown in certain desirable crystallographic directions.
For III-V semiconductor heteros~ructure lasers and the like
composed of InGaAsP/InP on a (100) substrate, the desirable
direction for the laser axis is <011>. Hence, it is
necessary to create optically flat, mirror quality facets
on the (011) crystallograpnic plane, because this plane is
~erpendicular (vertical~ to the <011> direction and the
(100) plane of the heterostructure heterostructure
substrate.
EIG. 1 shows a multilayer InGaAsP/InP
heterostructure body having mask 1 on the (100)
crystallographic plane. Also included in FIG. 1, as well
as all remaining fiyures, is a set of basis lattice vectors
indicating tlle three-dimensional orientation oE the
semiconductor body.
Tne semiconductor heterostructure of FIG. 1
comprises mask layer 1, p+-type caL~ layer 2, p-type upper


-- 4 --

cladding cladding layer 3, n-type or undoped active
layer 4, n-ty~e lower cladding layer 5, and n-type
substrate 6. The conductivity type for each layer can be
reversed so that each p-layer becomes an n-layer and eac~
n-layer becomes a p-layer. For the example described
herein, cap layer 2 is a~proximately 3000~5000 angstroms
thick, cladding layers 3 and 5 are a~proximately 1.5-2~m
thick, active layer ~ is approximately 1000-3000 angstroms
thick, and substrate 6 is approximately 75-100 ~m thick.
Semiconductor materials for the heterostructure
are chosen from the group of III-V compQunds. In
uarticular, a binary III-V compound, InP, is employed for
cladding layers 3 and 5 and or substrate ~. A quaternary
III-V compound, Inl_yGayAsxPl x~ is utilized for cap
layer 2 and active layer 4, wherein the alloy composition
ratios x and y are chosen to produce a particular
wavelength or energy bandgap and lattice constant for the
heterostructure. For a description of techniques for
choosing x and y, see R. Moon et al, "Bandgap and Lattice
Constant of GaInAsP as a Function of Alloy Composition", J
Electron. Materials, Vol. 3, p~ 635 (1974). In the
description which follows, exemplary composition ratios,
x = 0.52 and y = 0.22, are selected to produce a wavelength
of 1.3 ~m (On95eV). It is important to note that the
inventive method is equally applicable when these ratios
are varied to pronuce wavelengths in the range of 1~1 ~m to
1.7 ~m. For concentration ratios producing wavelengths
above 1.5 ~m, it is necessary to grow a quaternary
antimeltback layer between layers 3 and 4 during liquid
~hase epitaxial growtl~ of the heterostructure. The
presence of such an antimeltback layer requires the
inventive metllod to be modified only slightly, in terms of
etching exposure times, to provide acceptable results.
A mask layer is deposited on the (100) plane of
the semiconductor body by any suitable deposition process
such as chemical vapor deposition or the like. ~n
exemplary mask layer is chemically composed of silicon-




nitride. Mask 1 is formed by photolitllography and dryetching of the silicon nitride to have edges which are
substantially smooth. ~triped regions in mask 1 leave
surface areas such as surface 10 completely exposed, as
opposed to being cov~red by mask 1. The stripe in mask 1
is aligned with the <011> direction of the semiconductor
heterostructure body. Although this type of stripe mask
produces a groove in the semiconductor body, other masks
such as the one shown in EIG. 12 can be utilized to produce
a single wall, i.e., for effectively slicing away an
unmasked portion of the semiconductor body.
FIG. 2 illustrates tile structural changes in the
semiconductor body of FIG. 1 after processing that body
with a wet chemical etcharlt. A wet chemical etchant
suitable for creating the structural change shown in FIG. 2
in a single step is HCl:~N03 = (1:~), where 1< a<5 and,
preferably, ~ is equal to 3. The etching process is
anisotropic and is substantially self-stopping when the
(011) plane is reached in each of the various layers of the
semiconductor body. This plane is perpendicular to the
(100) plane. The proportion of HCl and HN03 is critical to
ensuring that no step discontinuities appear at the
interface of the heterojunction and surface 20 exposed by
the HCl:H~03 etchant. By experimentation, it has been
found that, for less HN03 than an amount dictated by an
optimum proportion, ~uaternary layer 4 is etched more
slowly than binary layer 3. ThiS gives surface 20 the
appearance of being steyped outward toward the etched
groove such that layers 4 and 5 protrude into the groove
be~ond the ex~osed edge of layer 3. If the amount of HNO3
exceeds the optimurn proportion, the opposite result appears
because quaternary layer 4 etches more quickly than
layer 3. So, surface 2~ appears to be stepped inward from
the etched groove and layer 3 protrudes into the groove
beyond the exposed edges of layers g and 5. Optimization
of the value of ~ ~ermits the etchant to react with both
the binary layers (layers 3, 5, and 6) and quaternary



layers (layers 2 and 4) at approximately the same rate~
Hence, surface 20, which is e~posed by this optimized
etchant, is substantially planar through at least layers 2,
3, and g.
In practice, optimization is performed by using a
small sample of the semiconductor body to be etched. The
sample is then subjected to the etchant while the value of
~ is adjusted until the optimum value is found. Certain
factors influence the selection of a value for ~ such as
the alloy composition ratios x and y, the thickness of each
semiconductor layer in the heterostructure, the age and
strength or diluteness of the etchant component chemicals
and the temperature of the etchant.
Assuming that the value of ~ is optimized for the
wet chemical etchant, HCl: ~NO3, the exposed
crystallographic surface 20 is substantially perpendicular
to ~he (100) plane.
In one example from experimental practice, the
semiconductor heterostructure body defined above is
immersed and agitated in a chemical bath of ~Cl:3HNO3 for
approximately 30 seconds at 22 degrees Centigrade. After
this immersion, the etching process is halted by rinsing
the ~C1:3HNO3 from the semiconductor body with deionized
water and surface 20 is exposed. However, surface 20 has a
roughened appearance exhibiting irregular characteristics
such as high spots and striations generally along the <100>
direction~ and a polishing step is necessary to relnove
these irregularities from exposed crystallographic
surface 20.
FIG. 3 illustrates the structural change~ which
appear after the semiconductor body of FIG. 2 is polished
with a chemical etchant. In this instance, polishing
entails contacting exposed surface 20 ~FIG. 2) witl- HCl for
a time ~ufficient to expose a preferred crystallographic
plane of the semiconductor body. HCl is both material
selective and orientationally preferential (anisotropic) as
an etchant. As before, the selniconductor body of FIG. 2 is

6~


imln~rsed in a bath of HCl and ayitated. The polishing
process is halted by rinsing the etched semiconductor body
in deionized water. In one example, concentrated HCl is
utilized in the batt~ at 22 deyrees Centi~rade with an
immersion or etching time oE approxiamtely 3 seconds. For
more dilute concentrations of HCl, the etching time must be
adjusted and increased accordingly.
For the example shown in FIG. 3, the
crystallographic plane preferentially exposed by the HCl
etchant is (011) plane, denoted as surface 21, which is
per~endicular to the (100) plane. Surface 21 is an
optically flat mirror facet. Although HCl preferentially
exposes the (011) crystallographic plane of only the XnP
layers, i.e., layers 3 and 5, and does not etch the
quaternary layers, layers 2 and ~, the a.nount of etching
(polishing~ is so small as not to impair the substantially
coplanar relationship of the groove walls. If desired, the
value of can be selected to cause a slight undercutting
of the layers 2 and 4 during the first etching step,
whereupon the polishing of the layers 3 and 5 moves tlle
side walls thereof into coplanar relationship with the side
walls of layers 2 and 4. Generally, however, such fine
adjustment is not necessary.
At the lower portion of a trough or groove in
layers 5 and 6 created by the etching process,
crystallographic plane ~111) denoted as surface 22) is also
ex~osed as a polished facet. Surface 22 is generically
referred to as a (lll)B crystallographic plane which
includes planes (111, (111), (111), and (111). The suffix
'~' means that the particular plane includes only
phosphorous atoms which are chemically reactive and,
therefore, capable of bein~ removed by a chemical etchant.
Similarly, a (lll)A crystallographic plane, which will be
discussed below, includes planes (111), (111), (111), and
(111). The suffix 'A' means that the particular plane
includes only indium atoms which appear to be substantially
inert and resist reinoval by chemical etching.



FIGS. 4, 5, 6, and 7 sho~ structural changes
which appear after the semiconductor heterostructure body
of E`IG. 1 is subjected to the etchants in a sequential
etching process. The method shown in EIG~. 4 through 7 is
called seguential etchiny because each layer of the
multilayer structure directly under exposed surface 10
(FIG. 1) is etched away in sequence~ That is, the portion
of cap layer 2 directly under surface 10 is etched away
with a wet or dry chemical etchant to expose surface 12 on
cladding layer 3. Preferably, each etchant used is
material selective, i.e., an etchant which attacks either
laylers 2 and 4 or layers 3 an~ 5, but not both. An
advantage of this is that it provides greater control of
the process. Eor example, variations in the performance of
one etchin~ step has little or no affect uyon the
performance of the next step.
Several wet chemical etchants have been shown to
be effective for selectively etching quaternary layers such
as layers 2 and 4. Examples of several selective etchants
include: a solution of H2SO4:H2O2:H2O = (10:1:1) as
described in R. J. Nelson et al., "High-Output Power in
InGaAsP/InP (A = 1~3 ~m) Strip-Buried Heterostructure
Lasers," Applied Physics Letters, Vol. 36, p. 353 ~1980);
or AB etchant, wherein the A solution is (40.0ml.
H2O ~ 0.3~.Ag NO3 ~ 40.0ml. HF) and the B solution is
(40.0g. Cro3 ~ 40.0ml. H2O) and A:B=(l:l~ as described in
G. ~. Olsen et al., "Universal Stain/Etchant for Interfaces
in III-V Compounds," Journal of Applied Physics, Vol. 45,
No. 11, p. 5112 (1974); or a solution of KOH:K3Fe(CN)5:H2O.
Etching time for the quaternary layers varies according to
thickness of the quaternary layer, temperature, and alloy
colDpoSition ratios, x and y, for the quaternary layers.
For a 3000 arlystroms thickness of layer 2 (A = 1.3~in) and a
temperature of 22 degrees Centigrade, the following
approximate etching times produce the results shown in
FIGS. 4 and 6: AB etchant for approximately 15 seconds, and
KO~:K3Fe~CNj6 M2O etch for approximately 8 seconds. This



etching step is halted by rinsing the etched semiconductor
body in deionized water.
FIG. 5 shows the structural change of the
semiconductor body in ~IG. 4 after etching in an InP
selective etch. ~or this etching step, HCl is a suitable
etchant to cut away the portion of layer 3 under surface 12
(EIG. 4), thereby exposing surface 13 on quaternary
layer 4. This etchant stops reacting automatically at
surface 13. For an InP layer thickness of apuroximately
0 105 ~ m, an exemplary etching time period for concentrated
HCl is approximately 45 seconds to produce the results
shown both in FIGo 5 and FIGo 7~ After this etching step
as shown in FI~ 5, it is important to note that the
etched, exposed walls of layer 3 exhibit crystallographic
smoothness.
FIG. 6 illustrates the structural change apparent
in the semiconductor l)eterostructure body, after the body
shown in E~IG. 5 is contacted with a wet or dry chemical
etchant to selectively etch ~uaternary layer 4 directly
under surface 13 for a time period sufficient to expose
surface 14 on layer 5. Also, crystallographic surface 20
is exposed at a preselected (e.g., perpendicular) slope to
the surface containing mask 1 and surface 10 (EIG. 1). The
etching procedure and the etchants employed at this step
have been described above in relation to FIG. 4.
FIG. 7 shows the completion of all structural
changes caused by the sequential etching process. Again,
~r. InP selective etchant t HCl, is contacted with exposed
surfaces of the semiconductor body create an optically flat
mirror facet at surface 21. In particular, surface 14 and
crystallographic surface 20 are brought into contact, via
immersion and agitation as described above, with a solution
of HCl for a time period suficient to expose a preferred
crystallographic ~lane as the optically flat mirror facet.
~or this example, the e~ching time period in a bath of
concentrated HCl required to produce exposure of the (011)
crystallogra~hic plane at surface 21 is approximately 20

-- 10 -




seconds. As stated above, surface 22 is also exposed
through the InP material com~rising layer 5 and
substrate 6. Surface 22 is a (lll)B crystallographic
l~lane.
Although, as aforedescribed, either wet or dry
etching can be used ~or the layers 2 and g, dry etching is
~enerally better because it avoids any undercutting
problems associated with wet etching.
FIGS. ~, 9, 10, and 11 show another process for
et~hing the semiconductor heterostructure of FIG. 1.
In EIG. 8, the semiconductor body is shown to
have a groove directly under surface 10 (FIG. 1), i.e., the
unmasked stripe region ~etween adjacent sections of mask 1.
This groove is created by either the wet or dry chemical
etchants described in relation to FIG. 2. FIG. 8 shows the
result using a dry etching process, the walls of the
grooves thus slightly converging towards one another as is
characteristic of generally known dry etching procedures.
Also, no undercutting of the mask 1 occurs.
~`IG. 9 illustrates the st.uctural changes to
layers 3 and 5 and to substrate 6 after the semiconductor
body of FIG. 8 is immersed in an InP selective polishing
etchant such as HCl. The etched surfaces of layers 3 and 5
and substrate 6 are depicted as being crystallographically
~5 smooth. Immersion and agitation in this step are required
for only a short time yeriod, for example, 3 seconds. This
immersion is followed by a rinse in deionized water to halt
the etching process.
The results shown in FIG. 9 are exaggerated for
clarity of presentation. Layers 4 and 5 protrude only
slightly into the groove because of the inclination of the
sidewalls of the groove. If it is necessary to remove this
slight prorusion, the remaining steps shown in FIGS. 10
and 11 are available to create a perfectly flat surface.
FIG. 10 shows structural changes to quaternary
layers 2 and g after ~rocessin~ the semiconductor body of
FIG. 9 with a quaternary material selective etch such as



the wet or dry chemical etchants described above in
relation to ~IG. 4. For the wet chemical e~ci~ants
described above, the etching times to complete this step at
room temyerat~r~ are shorter, by a factor of approximately
one-quarter to one-third, than the etching times given in
relation to the step shown in ~IG. 4. It is critical that
the etching be controlled to align the exposed surfaces of
layers 2 and 4 on substantially the same plane.
A final polishing step for the semiconductor body
of ~IG. 10 is shown in FIG. 11. After this step,
crystallographic plane (oll) is preerentially exposed by
HCl at surface 21~ Surface 21 is an optically flat mirror
facet because of the alignment of layers 3, 4, and 5. For
concentrated HCl, this polishing etch step is necessary for
only a short time period such as 3 seconds.
It is also possible to omit the first HCl etching
step tthe result being shown in FIG. 9) and proceed
directly to the layers 2 and 4 etching step (FIG. 10). The
final polishing step (~IG. 11) corrects any roughness left
by omission of the FIG. 9 step. Also, the step illustrated
in ~IG. 10, of slightly etching back the layer 4 prior to
the final polishing step~ can be done in the aforedescribed
process illustrated by FIGS. 1-3. That is, such layer 4
etching step can be performed to remove any led~e of layer
4 protruding into the groove after the first etching step,
as well as for slightly recessing the layer 4 edge to
insure its coplanar relationship with layers 3 and 5 after
the final polishing step.
The semiconductor body shown in FIG. 12 is at an
orientation disylaced 9o degrees from that shown in FIG. 1.
Mirror facets are created on crystallographic plane ~011)
in this orientation and are useful in producing ring lasers
and sidewalls parallel to the laser axis for
heterostructure lasers. T~le (100~ surface of layer 2 has
mask 1 partially disposed thereon with stripes in the <Oli>
direction. Layer 7 is quaternary layer similar in
com~osition and thickness to layers 2 and 4.


~ 12 -

A~ter the semiconductor body of FIG. 12 has
reacted with a chemical etchant such as a Br:CH3O~I solution
(1%, for 30 seconds) Or HCl:HNO3 = (1:~) (as described
earlier), for 30 seconds, crystallographic surface 30
appears as shown in FIG. 13. surface 30 is an oblique
surface cutting through each layer o the semiconductor
heterostructure near a (lll)A crystallographic plane which
is inert as mentioned above in relation to FIG. 3.
FIG. 14 shows the structural changes which result
in quaternary layers 4 and 7 after the semiconductor
heterostructure of FIG. 13 is contacted by a selective
quaternary etchant such as one described above in relation
to FIG. 4. It is important that the thickness and
composition of layers 4 and 7 be chosen appropriately so
that the selective quaternary etchant causes surfaces 31 to
be substantially coplanar. For the exemplary semiconductor
body and layer thicknesses described above, etching time
periods approximately seven or eight times longer than
those defined for the quaternary layer selective wet
2Q chemical etchants descri~ed in relation to FIG. 4 above.
The results of a final polish etching step on the
sem7 conductor heterostructure body of FIG. 14 are shown in
FIG. 15. The polish etchant is HCl which is material
selective (InP) and orientationally preferential
(crystallographic plane (011)). Because of the hollow
cavities left by the removal of quaternary layers 4 and 7,
the HCl is able to etch layers 3 and 5 from underneath
through the (lll)B plane and exposing, thereby,
crystallographic plane (011) at surface 32 on layers 3 and
S. By yroper experimentation with layer and composition
thickness and etching times, it is possible to have
surfaces 31 and 32 of layers 3 and 5, and 2, 4, and 7 ,
respectively, coplanar in crystallographic plane (011) as
an optically flat mirror facet. For concentrated HCl, the
etching time period is determined to be approximately 20
seconds.

Representative Drawing

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Administrative Status

For a clearer understanding of the status of the application/patent presented on this page, the site Disclaimer , as well as the definitions for Patent , Administrative Status , Maintenance Fee  and Payment History  should be consulted.

Administrative Status

Title Date
Forecasted Issue Date 1985-01-29
(22) Filed 1982-06-23
(45) Issued 1985-01-29
Correction of Expired 2002-01-30
Expired 2002-06-23

Abandonment History

There is no abandonment history.

Payment History

Fee Type Anniversary Year Due Date Amount Paid Paid Date
Application Fee $0.00 1984-02-29
Owners on Record

Note: Records showing the ownership history in alphabetical order.

Current Owners on Record
WESTERN ELECTRIC COMPANY, INCORPORATED
Past Owners on Record
None
Past Owners that do not appear in the "Owners on Record" listing will appear in other documentation within the application.
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Document
Description 
Date
(yyyy-mm-dd) 
Number of pages   Size of Image (KB) 
Drawings 1993-09-10 7 159
Claims 1993-09-10 1 27
Abstract 1993-09-10 1 13
Cover Page 1993-09-10 1 20
Description 1993-09-10 13 576