Note: Descriptions are shown in the official language in which they were submitted.
3~37
PROGRAMMABLE AUTOMATIC CONTROLLER
Back~ d of the Invention
This invention relates to a programmable automatic con-
troller for operating a glassware forming machine having a
plurality of functional sections which operate in a timed rela-
tionship with one another.
In the past, there has been a great need for a programmable
controller for operating such complex machines. The glass form-
ing machine is typically comprised of a plurality of individual
sections which are integrated into a single plural section
machine fed by a single source of molten glass. The sections
are operated in synchronism in such relative phase relationship
as to permit the several sections to acquire gobs in ordered
sequence from a single gob feeding means. Thus, as one of the
sections is taking a gob from the feeding means, another section
is delivering a finished article to an output conveyor and the
other intermediate sections are enyaged i n various forming steps
intermediate the taking of a gob and the production of a fin-
ished ware.
Further, it has been customary in the past to provide two
molds in each section of an individual section machine whereby a
gob is received in a first mold called the blank or parison mold
for the initial ~rocess of forming a parison, followed by a
~ransfer of the parison to a second mold called the blow mold
for a final blowing of the article. By this means9 each section
of the machine is operating simultaneously upon two workpieces.
In order to control the operation of the various functional com-
ponents of each section of a glass forming machine, a means must
be provided for actuating each of the section elements in a
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preselected cyclic time format so that the operation of one ele
ment does not interfere with, but rather complements, the opera-
tion of the other components in the section. In addition, means
must be provided for interrelating the timing of the individual
sections with respect to a machine standard.
The several functional elements of the glass forming sta-
tions of the indivi~ual section machine are typically controlled
by pneumatic pressure which is controlled by either a mechanical
synchronizing means in the form of rotary drums or by an elec-
tronic timing circuit. An example of the prior art controllerutilizing mechanical synchronizing means is disclosed in Ingle,
U.S. Patent No. 1,911,119. The Ingle glass forming machine is
cumbersome and more importantly3 is difficult to adjust so that
the timing of the operation of the various components of the
machine can be varied. An example of the prior art controller
utilizing electronic timing circuits is U.S. Patent No.
3,762,907 issued to Richard M. Quinn, et al., and U.S. Patent
No. 3,969,703 issued to Kwiatkowski, et al., both of which are
assigned to the common assignee herewith. Some prior art con-
trollers do not include an easy, simplified means for adjustingthe time of operation of the various elements in a machine cycle
while the machine is operating and accordingly lacks the flexi-
bility desired in an automatic controller.
In addition, the prior art controllers either provided no
means or mechanical switch means for adjusting the time rela-
tionship of a section with respect to the machine time. Gener-
ally, the section delay means comprised components separate and
distinct from the components comprising the means for adjusting
the function actuation times. If remote controls were desired
for varying either the function actuation times or the section
delay time, further separate and distinct components were
required for processing the remote commands. Thus, the number
of components of the prior art controllers was greatly increased
as a result of parallel systems of components performing rela-
tively similar tasks.
A further drawback of the prior art is that the components
of the prior art controllers ~re so numerous and of such size
and of such sensitivity that it was not practical to locate the
controller adjacent to the glassware forming machine being con-
trolled. Glassware forming machines produce large quantities ofheat which tend to disrupt the operation of the components in
some of the prior art controllers. Therefore, it was necessary
to remotely position the controllers, thus requiring an extremely
large quantity of cable, means for shielding the cable from the
electrical noise of the environment and means for isolating the
controller from the cables. This involved a great deal of
expense.
It is therefore an object of this invention to provide a
flexible programmable automatic controller for operating a
glassware forming machine.
It is another object of this invention to provide an auto-
matic controller having a simplified and efficient means for
adjusting the time of the operational functions of a glassware
forming machine with a high degree of accuracy while the machine
is running.
It is yet another object of this invention to provide an
automatic programmable controller that can be placed adjacent to
the glassware forming machine it is controlling.
A further object of this invention is to provide an auto-
matic programmable controller having means for adjusting thetiming of a section with respect to the machine time.
A still further object of this invention is to provide an
automatic programmable controller with means for remotely con-
trolling the means for adjusting the timing of a section with
respect to the machine time.
Another objective of this invention is to provide a single
means for controlling the remote and local variation of section
timing and function actuation in order to minimize the number of
components comprising the controller.
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Accordingly, the inven-tion provides a prograr~nable
au-tomatic controller for controlliny at leas-t one section of
a glassware forming machine, the at least one section including
a plurality of movable components which operate in each of a
plurality of machine cycles in timed relationship with
respect to one another, the machine including machine cycle
position indicating means for cyclically moving in synchronism
with the cyclic operation o:E the maa.hine, the controller
producing substantially no heat and being so compact as to
minimiæe cooling requirements and comprising small containing
means located adjacent to at least one section and including:
first timing means for generating a digital signal in
synchronism with the movement of the cycle position indicating
means, ~the digital signal providing an instantaneous
indication of the time elapsed in each cycle of operation of
the machine; storage means for storing the relative times in
a cycle of machine operation when each of the plurality of
components is to be actuated, the storage means being a
random-access memory for storing the relative times in a
cycle of machine operation when each of the plurality of
components of the section is to be actuated and having one
location ~or storing the time the at least one section is
delayed from the machine cycle; means coupled to the storage
means for selectively varying the actuating times of selected
components stored in the storage means to thereby change the
rela-tive times in each machine cycle when the selected
components are to be actuated;
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3~7
means for reading out the contents o~ the storage means;
first comparator means responsive to the first timing means
and the readou-t means for comparing the first digital signal
corresponding to the time elapsed in each cycle with the time
the section is delayed from the machine cycle, the first
comparator means providing a first actuating signal when a
favorable comparison results; second timing means responsive
to the first actuating signa:L and the machine cycle position
indicating means for generating a second digital signal in
synchronism with the movement of the cvcle position indicati~
means, the second digital signal providing an instantaneous
indication of the time elapsed in each cycle o~ the section;
second comparator means responsive to the readout means for
comparing the second digital signal corresponding to the time
elapsed in each section cycle with at least one relative
component actuating time stored in the storage means~ the
second compara-tor means providing a second actu~ting signal
when a favorable comparison results; and addressing means
receiviny the second actuating signal from the second
comparator means for providing a component operating command
to the component whose component actuating time compared
with the cycle time elapsed.
It is often desirable, in controlling the operation
of a glassware forming machine, to vary the time at which a
particular machine element is to be actuated. Accordingly~
in one aspect of the invention thumbwheel switches are
provided which can be appropriately set during a machine
operation to enter a new component actua-ting time into the RAM.
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In addition to apoaratus for controlllng the time in a cycle
duriny which the various components are actuated, apparatus
is provided for stopping or starting a section at any time
duriny a machine cycle. Function actuation time variation
and section starting and stopping can also be controlled
from a location remote from the controllex.
The invention also con-templates a means for
controlling the timed relationship of the various machine
sections wherein each of the sections operates in a
predetermined, interdependent
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timed relationship with respect to one another. One location in
the RAM stores the time by which a section is delayed from the
machine cycle time. A second counter also totals the machine
cycle time. ~hen the output of the second counter matches the
stored section delay time, the First counter is reset, so that,
in effect, the first counter totals section cycle time.
Thus, for example, six machine sections may each receive
input material from a single source. Accordingly, the con-
troller of the present invention includes means for sequentially
coupling the input material to each of the sections in a prese-
lected order and to stagger the section cycles of each of the
sections in accordance with the order in which the input
material is fed thereto.
As a result of the unif;ed control system, the present
invention is comprised of significantly fewer components than
prior art electronic controllers, enabling the controller to oe
positioned adjacent to the machine being controlled. Thus, the
costs of installation and operation are greatly reduced.
Brief Description of the Drawings
Other objects, features and advanta~es of the present inven-
tion will become more fully apparent from the following detailed
description, the appended claims and the accompanying drawings,
in which:
FIGURE 1 is a block diagram of the programmable automatic
controller system of the present invention;
FIGURE 2 is a functional block diagram of the section memory
unit and operator control sections of the programmable awtomatic
controller for an individual section;
FIGURFS 3a, 3b, 3c, 3d, 3e and 3f are detailed circuit dia-
grams of the section memory unit together with the controlstherefor;
FIGURE 4 is a schematic diagram illustrating the manner in
which FIGURES 3a~ 3b, 3c, 3d, 3e and 3f should be oriented; and
FIGURES 5a and 5b are detailed circuit diagrams of the func-
tion enable and start-stop circuitry.
3 ~
Detailed Description of the Preferred Embodiment
Refer now to FIGURE l where a block diagram of the program-
mable automatic controller system of the present invention is
shown. A pulse generator 100 provides a train of cycle clock
pulses and a reset pulse at the completion of the machine cycle.
The generator operates on a machine cycle base wherein 360 cloc~
pulse intervals are provided per cycle. In the preferred
embodiment, the pulse generator includes a suitable conventional
pulse generating means mounted on the drive shaft of the glass-
ware forming machine and generates two pulse trains. The firstpulse train provides a cycle clock pulse for every degree of
machine rotation and the second pulse train provides one pulse
per machine revolution. Thus, assuming that the machine to be
controlled operates through a predetermined cycle, one pulse is
generated at the beginning of the machine cycle and another
pulse is generated every 1/360th of a machine cycle.
The output of pulse generator 100 is coupled to each of a
plurality of individual machine section memory units 102. Each
section memory unit includes storage, comparing and addressing
circuits which, when arranged, as described hereinbelow, deter-
mine which elements of the section being controlled are to be
actuated at any given time. In addition, each section memory
unit includes means for processing the output of thumbwheel
switches for changing the relative time in a machine cycle when
selected section components are to be actuated.
Operator controls 104 includes start-stop push buttons for
starting up or shutting down the machine be1ng controlled.
In addition, operator controls 10~ include a degree display
for instantaneously displaying the cycle t;me elapsed for a par-
ticular section being operated. Finally, the operator controlsinclude thumbwheel switches for controlling the changing of the
relative actuation times, and a function select control for des-
ignating which operational element is having its timing changed
by the thumbwheel switches. The design of the controller is
3~ such that it may be positioned near the machine being controlled
so that the operation of the machine can be monitored while the
various control functions in the operator controls are being
changed.
The output of each of the section memory units 102 is
coupled to an associated valve block machine interface 106 which
provides the mechanical drive means for the machine being con-
trolled. If, for example, the glassware forming machine being
controlled is operated on a pneumatic basis, the valve block
interface might include a number of valves which are controlled
by solenoid actuators, the solenoid actuators being in turn con-
trolled by the output of section memory units 102. A detaileddescription of the valve block machine interface will not be
presented herein, because actuators in valves for operating
machine elements are known in the art and because of the appli-
cability of the control system of the present invention to dif
ferent glassware forming machines each having a different valve
bloc~ machine interface structure.
A tape recorder 108 is provided, which stores operational
commands generated by a decimal keyboard. Thus, if the sections
being controlled are to be operated in a number of different
modes, each particular program mode may be stored on tape until
it is utilized. The output of the tape is coupled to a central
console 110 which provides dual operator controls so that the
variables of all section under the control of central console
110 may be altered from a c~ntral location. The central console
controls override the individual operator controls 104. In
addition, as each of the individual sections are operated under
the control of their associated section memory units 102, the
section memory unit may provide an output to the central control
verifying the order in wh;ch the respective components of the
machine are actuated. This information may be stored in the
tape recorder for future use.
Refer now to FIGURE 2 with respect to which a more detailed
description will be given of the section memory unit 102 and the
operator controls 104. The reset output of clock 100 resets
section synchronization controller 200. Cycle clock pulses then
increment a counter within section synchronization controller
200. One of the addresses in RAM 202 stores the time relation-
ship of the particular section to the machine generally. For
example, if a particular section is to be delayed 60 degrees
behind the machine cycle, one address of RAM 202 would contain
the equivalent of ~0. When this particular address is accessed
by RAM address select 204, this time is compared in section syn-
chronization controller 200 with the machine cycle time as
stored in a counter. When a favorable match occurs, section
synchronization controller 200 resets counter 206.
1n Pulse generator 100 also clocks counter 206, so that the
stored count is indicative of the section cycle time. For every
clock pulse from pulse generator 100, RAM address select 20~
accesses every memory location in RAM 202 storing an actuation
time. The accessed times are compared with the output of
counter 206 ;n function time comparator 208. If a favorable
match is found, the comparator produces an enable signal to
which function enable circuit 210 is responsive. ThP enable
signal permits the address of the matching time to be translated
into a signal to which valve block machine interface 106 is
responsive to activate or deactivate a section function.
The actuation time of any machine section component may be
altered quite easily. The particular function to be altered is
selected by use of a rotary switch and the new actuation time is
entered on thumbwheel switches. Upon depression of an enter
button, the selected function is compared with the function cur-
rently being addressed by the RAM address select 204. When a
favorable comparison occurs, data enter control 212 permits data
on the thumbwheel swikches to be entered into the addressed RAM
202 location. Data may also be entered from central console
110. An override command from central console 110 to data enter
control 212 permits the entry of data from the central console
as opposed to the thumbwheel switches located on the controller
ad~ cent to the section being controlled. In addition, the
actuation ti~e of the function currently selected by the func-
tion select rotary switch is displayed on actuation time display
214.
9 ~
Function enable circuit 210 is also responsive to start-stop
controls 216. Upon depression of the start switch~ function
enable circuit 210 prohibits an output to valve block machine
interface 106 until the -function that should properly be actu-
ated first is enab1ed. Provision is also made for an emergencystop and a delayed stop. The emergency stop immediately pro-
hibits further movement of the glassware makillg section after
opening the two molds therein. The delayed stop prohibits any
further molten glass from being fed into the machine section;
but permits the section to run through three machine cycles
before the section comes to rest in order to clear the section
of all glass.
As an alternative to the operation as described above, the
function times could be stored in RAMS 202 consecutively. If a
match is found by comparator 208, QAM address select 204 would
immediately increment the address, and the contents of the new
address would be compared by comparator 208. If the new con-
tents also match, RAM address select 204 would again increment
the address accessed and the contents of the new address would
be compared. This process would continue until no match exists.
The functions corresponding to the matched times would all be
activated essentially simultaneous1y. RAM address select 204
would hold at the first address having contents that do not
match until the output of counter 206 does match the contents of
the addressed location.
Referring now to FIGURES 3a through 3f, internal clock 400
(FIGURE 3d) can be any conventional oscillator with an output
frequency of approximately 500 kilohertz. Decade counter 402,
responsive to clock 400, has ten output terminals which are nor-
mally low, with each of the outputs consecutively going highwith each clock pulse for one clock pulse, so that the output
signals of counter 402 are a series of phase-shifted pulses each
with a frequency of ltlO of the output of clock 400 and a pul5e
width of the width of the output of pulses of clock 400. Seven
outputs of counter 402 are used and are represented as SO
through S6. The S0 through 53 signals are inverted by inverters
such as inverter 404.
Thus, tne output of counter 402 are signals having the same
frequency but phase-shifted to provide timing pulses for the
various components of the circuit. Counter 402 can be any
counter having a similar output, but is preferably the MC14017B
chip manufactured by Motorola.
Binary counter 406 is responsive to the S5 signal through
NQR gate 408. Counter 406 may be any binary counter havin~ at
least nine bits, but in the preferred embodiment, counter 406 is
an MC14040B chip manufactured by Motorola.
The tWQ lowest order outputs provide the two lowest order
inputs for BCD to decimal decoder 410. The binary nu~ber repre-
sented on the input lines causes one of the ten output lines to
go high during the period of that count. The highest order
input is grounded, and the next highest order input acts as an
inh;bit as described below. The two lowest order inputs are
capable of counting from zero to three, which cause the output
lines represented by 00 through 03 to consecutively go high. In
the preferred embodiment decoder 410 is the MC14028~ chip manu-
factured by Motorola.
Thus, the timing relationship is such that as each 00 signal
is high, the S0 through S6 signals each go high once. Flip-flop
412 causes the third order input to go high during the period
between the beginning of the S4 pulse and the beginning of the
S6 pulse in each cycle of 50 through S6. During that period, 00
through 03 remain low. All of the flip flops in this circuit
may be any flip-flop capable of functioning as described. How-
ever, in the preferred embodiment all of the flip-flops are the
MC14013B chip manufactured by Motorola.
The machine reset signal from pulse generator 100, as it
enters the controller, passes through optical isolator 414
(FIGURE 3e) and buffer 416 to clock flip-flop 418. This in turn
causes the data input of flip-flop 420 to go high. The next
time the 51 signal is high while the 00 signal is high, flip-
flop 420 is clocked by the output of AND gate 421 causing degree
counters 422 (FIGURE 3f) to be reset and flip-flop 418 to be
reset. As the machine clock signal enters the controller, it
passes through optical isolator 424 and buffer 4Z6 causing the
data input of flip-flop 428 to go high. The next t1me the 00/S0
signal produced by AND gate 431 (FIGURE 3d) goes high, the clock
pulse is advanced to the output of flip-flop 428, which in turn
clocks degree counters 422. The falling edge of the Q output oF
flip-flop 423 causes flip-flop 420 to be reset. The frequency
of the 00/S0 signal is such that every clock pulse entering the
controller will be advanced to the output of flip-flop 428 to
clock degree counters 422. The output of count~rs 422 repre-
sents the time that has passed in each machine cycle as deter-
mined by the reset signal followed by the clock pulses.
RAM address counter 406 (FIGURE 3d), in addition to creating
the 00 through 03 output signals, also addresses RAMS 430
(FIGURE 3c). In the preferred embodiment the RAMS are the
CD4061 ADRAMS manufactured by RCA. Any other suitable RAMS may
be employed. The time of each function is stored in 12 bits
located at the same four incremental addresses of each of the
three RAMS. After an address has been incremented by RAM
address counter 406, the contents of the newly addressed loca-
tion of RAMS 430 are clocked into serial to parallel shift reg-
isters 432. The shift registers can be any four bit output
serial to parallel shift register, but in the preferred embodi~
ment they are the MC14015B chip manufactured by Motorola.
The time stored in the highest address location of RAMS 430
represents the time by which the particular section is delayed
behind the machine cycle as determined by the reset and clock
signals. After this highest time has been clocked into shift
registers 432, flip-flop 436 (EIGURE 3d) sets, causing BCD
latches 434 (FIGURE 3f) to enter this time. When S1 is high at
the same time 00 is high, comparators 438 compare the output of
latches 434 with the output of counters 422. If a favorable
match occurs, the output of comparators 438 reset counters 440
(FIGURE 3e) which represents the time elapsed in the particular
section cycle.
12
As mentioned above, each address of RAMS 430 is addressed
during each clock pulse. The data on the output lines of shift
registers 432 (FIGURE 3c) represent a coherent time every fourth
data access. On every fourth data access, the output of shift
registers 432 is compared with the output of counters 440 in
comparators 442 (FIGURE 3e). All compara-tors used in the cir-
cuit can be any four bit comparators capable of performing the
described functions; however, in the preferred embodimellt the
MC14585 comparator manufactured by Motorola is used. A favor-
able comparison by comparators 442 indicates that the function
whose time has been compared to the output of counters 440
should be enabled. The address favorably compared and the out-
put of comparators 442 is supplied to the component enable cir-
cuit of FIGURE 5.
As mentioned above, the alteration of an actuation time for
a particular function is easily accomplished. First, one
selects the function whose actuation time is to be changed on
function select switches 450 (FIGURE 3d). Then the actuation
time to which a change is desired is set on thumbwheel switches
446 (FIGURE 3a) which produce a BCD output which is the input
for parallel to serial shift registers 448. Shift registers 448
can be any parallel to serial shift registers having at least
four input bits; however, the MC14021 chip produced by Motorola
is used in the preferred embodiment. The 00/SO signal from AND
gate 431 presets the shi~t registers 448 to the number selected
by the thumbwheel switches 446, and the S1 signal advances that
data through the shift register. At the appropriate time, as
controlled by select gate 452 (FIGURE 3d) and circuitry
described below, the output of each shift register respectively
is fed into one of RAMS 430, with the output of each shift being
stored in an incrPmentai location. Select gate 452 can be any
select gate that is capable of switching either one of two sets
of three inputs to an output, but in the preferred embodiment is
the CD4019 select gate manufactured by RCA.
To enter data, the enter switch 454 (FIGURE 3c) is
depressed, causing optical isolator 456 to present a high signal
13
to the data input of flip-flop 45~3. On the next 01 pulse, flip-
flop 458 is clocked causing enter push button flip-flop 460 to
be clocked so as to put a high voltage on the data input of
flIp-flop 462.
The clocking of enter push button flip-flop 460 causes its Q
output to become low, so that the diode of optical isolator 461
conducts. The resultant current flow through the photo-
transistor of isolator 461 causes Data Enter light emitting
diode 463 to light.
Data may be entered into the RAMS 430 either when the sec-
tion is running or when the section is stopped. If the section
is stopped, switch 464 is closed, causing the output of optical
isolator 466 to go highg which in turn causes one input of AND
gate 468 to be high. Since the output of flip-flop 462 is also
high, flip-flop 470 becomes set, which causes the one input of
AND gate 472 to become high.
As RAM address counter 406 (FIGURE 3d) causes each location
of RAMS 430 to be accessed, the divide by four line of the out-
put of counter 406 clocks BCD counters 474. The divide by four
1 i ne of counter 406 i s taken so that one pul se at the clock
input of counters 474 represents the incrementation to the next
function t;me stored within RAMS 430. The output of counters
474 is compared with the output of function select switches 450
in comparators 476. A favorable match in comparators 476 indi-
cates that the function selected on function select switch 450
matches the function whose time has just been accessed from RAMS
430. This causes the second input, and therefore the output, of
AND gate 475 to become high so that one input of AND gate 475
becomes highO At the appropriate time, i.e., the next 53 pulse,
the output oF AND gate 475 becomes high, enabling the write
inputs of RAMS 430. This enable signal also clocks decade
counter 477 (FIGURE 3c) which counts from zero to four, repre-
senting one complete actuation time transfer. The signal repre-
senting the count of four resets flip-flop 460. In the pre-
ferred embodiment counter 477 is the MC14017B decade counter
manu-Factured by Motorola.
14
If the section is running, switch 46~ is open causing the
set input of flip-flop 470 to be low. However, when a favorable
match is found by comparators 476, and the same function has
been enabled by comparators 422, the output of AND gate 478
becomes h;gh clocking flip-flop 470. Thus, the output of AN0
gate 472 becomes high, which enables data to be transferred into
RAMS 430, upon the next S3 signal.
Thus, if the machîne is not running, data is entered momen-
tarily after the depression of enter switch 454 upon the next
accessing of the locations of RAMS 430 that represent the func-
tion whose time is to be changed. If the section is running,
new data cannot be entered into RAMS 430 until the function
whose actuation time is to be changed has been actuated after
enter switch 454 has been depressed.
Data may also be entered remotely from central console llQ
via a data link. The central console controls include means for
resetting to zero the address of the function time to be a1tered
and means for incrementing that address. The signals represent-
ing the reset and increment command respectively come in on data
link lines 482 and 480 (FIGURE 3b) and pass through the respec-
tive optical isolators 484 and 486. These signals respectively
reset and clock data link address counter 488. Counter 488 may
be any binary counter with at least eight output bits, but in
t.he preferred embodiment is the MC14040B counter manufactured by
Motorola. When the output of data link address counter 488
matches the output of counter 406, (FIGURE 3d) the address to be
modified is being accessed. The output of comparators 490
enables select gates 452. To write into tne RAMS 430 from the
remote console 110, both the data link read select line 504
(FIGURE 3b3 and the data link write select line 506 ~FIGURE 3a)
must be high. This causes optical isolators 510 and 512 ~FIGURE
3a) to conduct, so that the data input of flip-flop 508 goes
high. Upon the next clock pulse to flip-flop 508, ~hen the
machine is not running during an Sl signal as determined by AND
gate 514, the Q output of flip-flop 508 becomes high, causing
select ga~e 452 to accept data from remote inputs and not from
Y3~'~
thumbwhee1 switches 446. Upon a favorable comparison in com-
parators 490 (FIGURE 3d), select gate 452 is enabled causing
data link 1ines 492, 494, and 496 ~FIGURE 3a), respectively
representing the units, tens and hundreds data from central con-
sole 110 to pass through, respectively, optical isolators 498
500 and 502, and select gate 452 to RAMS 430.
The time at which any component is set to actuate can be
displayed either at the controller or at central console 110.
To display the timing of a function at the controller, the
appropriate function is selected on function select switches 450
(FIGURF 3d). When comparators 476 find a match, value latch
driver/decoders 516 (FIGURE 3f) latch the output of serial to
parallel shiFt registers 432 (FIGURE 3c) which represents the
time of the function matching the function selected by the func-
tion select switches 450. The output of latches 516 drive
displays 518. Latches 516 can be any suitable latches, but in
the preferred embodiment are the MC14543 Decoder/Drivers manu-
factured by Motorola. Displays 518 are, correspondingly, seven
segment light emitting diode displays.
To access the contents of a particular location in RAMS 430
from central console 110, the address is selected as indicated
above, with lines 480 and 482 controlling counter 488 (FIGURE
3b). When comparators 490 indicate a match, the output of RAMS
430 is latched in data out latch 520 (FIGURE 3b), which may be
any three bit latch, but it is preferably the MC14042 Quad Latch
manufactured by Motorola. The output of data out latch 520 is
inverted by inverters 522 and connected to the light emitting
diode of optical isolators 524. Upon the occurrence of a read
select signal on data link line 504, a high voltage is supplied
to the phototransistors of op~ical isolators 524 causing the
read data lines to supply the output data.
Referring now to the component enable circuitry of
FIGURES 5a and 5b, the enable line from comparators 442 enables
decoder 600 (FIGURE 5a) after passing through inverter 602.
Decoder 600 may be any BCD to decimal decoder, but in the
preferred embodiment the MC14028B decoder manufactured by
3~
16
Motorola is used. Address lines ~indicating -the function to be
activated3 601, 603 and 605 a1so are inputs to decoder 603, the
outputs of which act as chip enable lines for decoders 604 which
can be any decoders, but are preferably the same decoders as
decoder 600. Thus, input lines 601, 603, and 605 act as chip
enable lines for decoders 604 while input lines 607, 609, and
611 are supplied to each decoder 604, so that for any given com-
bination of input lines, one output of decoders 604 becomes
high. The decoders 604 are attached to flip-flops such as flip-
flop 606, the two decoder lines to each flip-flop being con-
nected to the set and reset inputs. The output of each flip-
flop 606 goes to valve block interface 106 to enable a particu-
lar function. One input line to each flip-flop 606 enables the
function, while the other input line to each flip-flop stops the
function.
When the controller is initially powered, the electrical
components of the controller begin functioning. Signals to
valve block machine interface 106 are outputted by flip-flops
606. However, the machine does not initially respond to the
command signals. To begin the operation of any given section,
the start button on either the controller or central console 110
must be depressed, causing line 608 to become high, which in
turn passes through optical isolator 610 to one input of AND
gate 612. In order for the section to start in an orderly man-
ner, section operation should commence with one particular func-
tion, e.g., in the case of the preferred embodiment, with the
movement of the arm that transfers the parison from the blank
mold to the blow mold ~ack to the blank mold. Upon the occur-
rence of the revert arm pulse out of decoders 604, flip-flop 614
is reset which causes the ~ output to become high, which in turn
causes the section to respond to the command signals produced by
flip-flops 606. The pressing of the start button also causes
flip-flops 616 and 618 to be reset.
The preferred embodiment of the present invention includes
two different stopping modes. Upon depression of the emergency
stop switch, a high signal on emergency stop line 619 is
3~
transferred through optical isolator 620 which sets flip-flop
614. This causes the section power to turn off as soon as the
parison and blow molds open. Upon depression of the delayed
stop switch, a high signal passes on delayed stop line 621
through optical isolator 623 to set flip-flop 616. This causes
one input terminal of AND gate 625 to become high. In order to
assure an or~erly stop, a certain function should be performed
last. In the case of the preferred embodiment, this should be
the invers;on of the parison between the blank mold and the blow
mold. Upon the next occurrence of this function, the output of
AND gate 625 sets flip-flop 618, which in turn removes the reset
from counter 6?2 which may be any counter having one output line
that becomes high on the third clock pulse after reset, but in
the preferred embodiment is the MC14017B decade counter manufac-
tured by Motorola. As soon as the delayed stop button ispressed, no further molten glass is fed into the section.
Counter 622 then counts each invert operation. 8y the third
activation of the invert function, no glass remains in the
machine. At this point, the output of counter 622 indicating
the third clock pulse becomes high, clocking flip-flop 614, so
that the Q output of flip-flop 614 becomes low, turning off the
power to the section.
All of the integrated circuits described above are prefera-
bly composed of complementary metal oxide semiconductors (CMoSj,
thereby greatly reducing the heat that must be dissipated from
each of the integrated circuits. This enables the integrated
circuits to be much more compactly positioned on a circuit board
and the circuit board to be mounted in a smaller container.
The timing relationships of the various elements of the con-
troller are very important to the successful operation of thecircuit. This timing, as indicated above, is controlled by the
signals 00 through 03 and S0 through S6. For every machine
clock pulse, the 00 through 03 signals each become high at least
once. During each of the 0 pulses, each of the S0 through S6
signals become high exactly once. The period from the beginning
of a 00 pulse through the end of a ~3 pulse represents one
3'~
18
controller cycle, or 1/360 of a section, cycle, with the S sig-
nals further dividing each 0 pulse.
During the 00/S0 unit of time, the output o~ the enter push
button flip-flop 460 (FIGURE 3c) is clocked to the output of
flip-flop 462. The machine clock pulse is advanced through
flip-flop 428 (FIGURE ~e) to counters 422 and 440. Also, paral-
lel to serial shift registers 448 are strobed, so that the data
on thumbwheel switches 446 are entered. Finally, flip-flop 508
~FIGURE 3a) is reset so that select gate 452 is set to receive
information from shift registers 448.
During the 00/S1 period, shift registers 448 are clocked so
that new information is presented to RAMS 430, and shift regis-
ters 432 (FI&URE 3c) are clocked so that ne~ da~a is entered
into shift registers 432 from RAMS 430. Also, flip-flop 420
(FIGURE 3e) is clocked so that the machine reset signal resets
counters 422. Finally, if the section is stopped and if the
read and write select data link lines 504 and 506 are high, then
flip-flop 508 is clocked, causing select gate 452 (FIGURE 3d) to
accept data from the central console 110.
When an S2 signal is produced during the 00 period, data out
latch 520 (FIGURE 3b) enters data from the output of RAMS 430 if
comparators 490 have found a favorable match between RAM address
counter 406 and data link address counter 488.
During the 00/S3 period, the new first data bit is written
into RAMS 430 and counter 477 (FIGURE 3c) is incremented to a
~ount of one if conditions in the last 03/S2 period permit.
Also, if the data link was selected with a data link write com-
mand during the 00/S1 period, and RAMS 430 address is the same
as data link address counter 488 address, then the data by-te
from the data link is written into RAMS 430.
During the 00/S4, 00/S5 and 00/S6 periods, decoder 410
(FIGURE 3d) and RAMS 430 are inhibited, 01 output of decoder 410
is selected, and decoder ~10 and the RAMS 430 are enabled
respectively.
Next, signals are concurrently produced on the 01 and S0
lines. As this occurs, flip-flop 508 (FIGURF 3a) is reset so
19
that select gate 452 accept data from shift registers 448.
Also, flip-flop 458 (FIGURE 3c) is clocked so that the enter
push button signal appears at the clock input of enter push but-
ton flip-flop 460.
The S1 siynal then produces a pulse during the 01 pulse,
causing the second data byte from shift registers 448 (FIGURE
3a) to be shifted to the output line. The next output byte from
RAMS 430 is sh;fted into shift registers 432. Also, if the sec-
tion is stopped and if the data link write select line 506 is
high, then the Q output of flip-flop 508 becomes high causing
select gate 452 to permit data on the data link to be applied to
the RAMS 430 input line.
During the 01/S2 period, latch 520 (FIGURE 3b) is strobed,
entering data from the output of RAMS 430 if the output of RAM
address counter 406 compares favorably with the output of data
link address counter 488.
During the 01/S3 period, the new second data bit is written
into RAMS 430 and counter 477 (FIGURE 3c~ is advanced to the
count of two if the conditions in the last 03/S2 period permit.
If the data link was connected to RAMS 430 with a write command
during the 00/S1 period and the output of RAM address counter
406 is the same as the output of the data link address counter
488, then the data on the data link is written into RAMS 430.
During the 01/S4, ~1/S5 and 01/S6 periods decoder 410
(FIGURE 3d) and RAMS 430 are inhibited, a signal is produced on
the 02 line, and decoder 410 and RAMS 430 are enabled
respectively.
Thus, a signal appears on the 02 line~ When this cor-
responds to a signal on the S0 line, flip-flop 508 is reset
causing select gate 452 to accept data from thumbwheel switches
446 via shift registers 448.
During the 02/S1 period, the third data byte ls clocked from
shift registers 44J3 through select gate 452 to the input of RAMS
430. In addition, the next output byte of RAMS 430 is clocked
into shift registers 432. If the section is stopped and if the
data link write command line 506 is high, then the data link
1ines 492, 494 and 496 are switched by select gate 452 to the
RAM 430 data input lines.
When the 02 pulse occurs at the same time as the S2 pulse,
latch 520 is strobed with the output o~ RAMS 430 if the output
of RAM address counter 406 compares favorably with the output of
data link address counter 488.
During the 02/S3 period, the third data byte is written into
RAMS 430 and counter 477 is advanced to the count of three if
the conditions in the last 03/S2 period permit. If the data
link was selected with the write command during the last 00/S1
period and the output of RAM address counter 40Ç is the same as
the output of data link address counter 488, the data byte from
data link lines 49Z, 494 and 496 are written in RAMS 430.
During the 02/S4, 02/S5 and 02/S6 periods, decoder 410 and
RAMS 430 are inhibited, a signal is produced on the 03 line, and
decoder 410 and RAMS 430 are enabled respectively.
Next, a signal appears on the 03 line concurrently with a
signal appearing on the S0 line. At this occurrence, -Flip-flop
508 is reset, causing select gate 452 to accept data from shift
registers 448.
When the 03 pulse occurs at the same time as the S1 pulse,
the fourth data byte is clocked from shift registers 448 through
select gate 452 to the input of RAMS 430. In addition, the next
output byte of RAMS 430 is clocked into shift registers 432. If
the section is stopped and if the data link write select line
506 is high, then the data link lines 492, 494 and 496 are
switched by select gate 452 to the RAM 430 data input lines.
During the 03/S2 period, shift registers 448 are clocked so
that the fourth data byte from each of shift registers 448 is
outputted to the respective RAM data line. Also, the fourth
data byte from RAMS 430 are entered in shift registers 432.
Finally, if the section has stopped, and if the data link write
select line 506 is high, then the select gate 452 permits data
on the data link lines 492, 494 and 496 to be advanced to the
3S inputs of RAMS 430. During the 03/52 period, if the output o-f
comparators 442 indicate a favorable match, value driver/
decoders 516 are enabled. If enter pwsh button 454 ;s also
depressed and comparators 476 indicate a favorable match
(indicating that -the function select switch is set to the func-
tion currently being accessed), flip-flop 470 is clocked, thus
permitting a write operation into RAMS 430 on the following S3
signal. Finally, latch 520 is clocked with the output of RAMS
430 if the output of RAM address counter 406 corresponds to the
output of data link address counter 488.
When the 03 signal occurs concurrently with the S3 signal,
the fourth data byte from shift registers 448 is written into
RAMS 430 and counter 477 is incremented to a count of four if
conditions in the last 03/S2 permit. Note that the count of
four on counter 477 causes the reset of enter push button flip-
flop 460 so that the data input to flip-flop 462 becomes low.
If the data link was selected with a write command from line 506
during the 00/S1 period and the output of RAM address counter
406 is the same as the output of the data link address counter
488, then the daka from data link lines 492, 494 and 496 is
written into RAMS 430.
During the 03/54, 03/S5 and 03/S6 periods, decoder 410 and
RAMS 430 are inhibited, a signal appears on the 00 line and
decoder 410 and RAMS 430 are enabled respectively.
The components comprising the controller described above are
greatly reduced in number in comparison to prior art systems as
a result of the elimination of multiple components performing
similar functions. In addition, as mentioned above, the employ-
l ment of complementary metal oxide {~H~conductor integrated cir-
~J cuits (CMOS) reduces the heat that must be dissipated from eachchip. Thus a much more compact controller is possible, result-
ing in a minimization of cooling requirements.
Although only one exemplary embodiment of this invention hasbeen described in detail above, those skilled in the art will
readily appreciate that many modifications are possible in the
exemplary embodiment without materially departing from the novel
teachings and advantages of this invention. For example, the
arrangement of the RAMS storage devices can be rearranged in a
22
number of different methods. According1y, all such modifica-
tions are intended to be inclu~ed within the scope of this
invention as defined in the following claims.
