Note: Descriptions are shown in the official language in which they were submitted.
3~
5072-A PLASMA DISPLA~ PANEL DRIVE ELECTRONIC~ IMPROVEMENT
Background of _he Invention
Plasma displa~ panels are presently in commercial
use as digitally add:ressable information display
devices. The panel itself typically consists of two
glass plates w.ith a gas mixture sealed between them.
A plurality o~ X-axis electrodes extend in a mu-tually
paral.l.el array on an interior substrate of one plate,
and a pll.lrality of Y-axis el.ectrodes extend in a
mutually parallel array on the interior of the other
plate. The X-axis electrodes are at a 90 angle
10 to the Y-axis electrodes, therehy forming a plurality
o~ intersections between the X-axis and Y-axis
electrodes. A typical commercially available AC
plasma panel has 512 X-axis electrodes and 512
Y-axis electrodes, yielding 262,144 intersections or
15 cells.
When a voltage of between 180 and 200 volts is
applied across an X-axis electrode and a Y~axis
electrode, a discharge in the gas occurs at the cell
formed by the electrodes, causing a pulse of light
20 to be emitted at this point. Simultaneously, a
charge is collected on the cell wa].ls, which results
in the cell being an "on" cell. Once such a discharge
has been produced and the cell is turned "on", the
collected wall charge acts to continue the discharging
25 when a lesser AC sustain voltage is applied between
the electrodes. In an "on" cell, the gas w.ill
discharge and the cell will emit a pulse of light
at each transition of the applied AC sustain waveform.
The sustain voltage, however, is insuf~icient to
... ... ~ . ~ ........ .
initiate a dlscharge at an X~Y intersection. This
~r,.:, S " ,,,1 r,~ r phenomenon i.s known as inherent memory, and was
originally disclosed by Baker et al in Patent 3,~99,167,
and by Bitzer et al in Paten-t 3,959,190. By precisely
.
3~7
2 ~
timing, shaping, and phasing mul~iple alternating
voltage waveforms supplied to X and Y axes electrodes,
the yeneration~ sustaining, ~nd erasure of light
emitting gas discharges a~ selec~ed locations Dn the
plasma display panel can be controlled.
The ~tate of the ar~ of drive systems for plasma
panels is represented by Patent ~pplication N~.
381,157, ~iled ~uly 6, 1~81, ~ 3Oseph T. Suste~
describing a Drive System For A Pl.asma Panel utilizing
only three voltage lev81s~ and Patent Application
381,1~8, ~iled July 6, lq81, by Larry ~. Weber,
describing a MOSFET Sustainer For A Plasma ~anel Drive
System. ~hese two patents are assigned to the assignee
of the present invention.
These systems utilize Texas Instruments integrated
circuit driver chips to drive the electrodes of the
plasma panel. These chips, each capable of driving
32 electrodes on the panel, are types 5N75500 an~ SN75501.
These are the only currently available driver chips,
and they have several serious design problems that
the manufacturer cannot remedy at this timen The
only alternative to using these driver chips is to
use a resistor diode matrix, wherein each electrode
is connected to two diodes and a resistor. For 512
lines there are also 16 high voltage pulser circuits
and 3~ high voltage switch circuits required. In
order to drive a 512 x 512 plasma display panel, the
discrete electronics alternative to the Texas
Instruments driver chips takes up 650 squaxe inches
o~ printed circuit b~ar~ Using the Texas Instru~ents
driver chips" the number of components xequired
is reduced by a factor of 100, and the printed circuit
board area required is reduced by a factor of 5~
Si~ce assembly and test costs are greatly xeduced ~y
using the ~exas Instruments drive chips~ it is no
, ~
3t7
longer economically feaslble -to build plasma pane]
display systems without using the driver chips.
The most significant problem encountered in using
the Texas Ins-truments driver chips is that of
dissipating the power consumed in these chips.
Power dissipation can be dlvided into S areas:
low voltage logic power, quiescent power, level
shiEting boost power, parasitic power, and notch
dissipation power.
Low voltage logic power is the power used to
control the logical switching process of the driver
chips. This power is not an appreciable cause o~
excess power dissipation within the driver chips.
Quiescent power is the power consumed by the
high voltage switching components within the chip
while the chip is turned on but not performing any
type of operati.on. Since the driver chips are being
used to switch 100 volts, even a small amount of
quiescen-t current drawn by -the chips will result in
a Eairly large amount of power being dissipated in
the chips. The quiescen-t current for the SN75500
chip is 2 mA, and the quiescent current for an SN75501
driver chip is 3 mA. The quiescent power consumed
by the chips is 200 mW and 300 mW, respectively.
25 Since a 512 x 512 plasma display panel system requires
16 oE each of the two types of chips, the quiescent
power of the system's driver circuitry will be ~ watts.
This power level typically represents 10 to 20% of
the enti.re plasma display panel system power.
Level shiftiny boost power is the power consumed
by the chip when it .is being switched between
output stages. The chips use a boos-t current o-E
2 mA to switch Erom the low s-tate to the hlgh state~
~f all of the 32 outputs of the driver chip are to
be switched, a 2 mA current will be drawn by a
switching transistor in the circuitry oE each output
t~
at a dut~ cycle of ~.5%, which results in a tlme-
averaged level of 192 m~ of power per c~ip being
consumed when switching at a standard rate of 50 k~lz.
I'he next major power dissipation problem is
created by the existence of paracitic transistors
in the driver chips. A paracitic transistor is an
inadvertently crea-ted np or pn junction which is
inherent in the Eorming of a pn or np diode. In
order to be-tter understand the problem it is necessary
-to understand the basic operation of the driver chip
switching circuit.
The design of the Texas Instruments driver chips
utilizes 32 totem-pole output stages in order to
perform the switching operation. A totem-pole is
basically two switching transistors connecte~ in
series, with their common lead being the output of
the circui-t. The second switch lead of one transistor
is connected to high voltage, and the second swi-tch
lead of the seGond transistor is connected to ground,
or low voltage. By ensuring that only one of -these
transistors is turned on at a time, the output of
the circuit can be swi-tched from high voltage to low
voltage.
The transistors used in the totem-pole output
stages oE the Te~as Instruments driver chips are
N-channel enhancement DMOS (double diffusèd.ne-tal
oxide silicon) transistors, which are the key for
fabricating high voltage drivers and low voltage
control logic on the same chip. The Texas Instruments
design utilizes a pair of clamp diodes on the output
of the totem~pole to prevent the output level from
' ` -~ rising above the high voltage or below the low
voltage. When these clamp diodes are fabricated,
paracltic bi-polar transistors are formed along with
the diodes. These para~itic transistors, inherent in
junction isolation IC technology, result from the
3~
eY.istence of an additional np or pn junction being
formed wi.th the clamp diodes. The clamp diodes
are the base-emi-tter junction of -the parasitic
transistor, and the additional junc-tion is the base~
collector junc-tion. The resulting transis-tor has
its emitter connected to the common output, its
base connected to either the high or low vol-tage,
and its collector connected to the other voltage
level. This has the effect of placing a 100-volt
10 drop across the base-collec-tor junction of each of
these parasitic transistors. Therefore, when the
base-emitter junction is ~orward biased, curren-t will
flow between -the base and the collector, causing
power to dissipate in this junction. While Te~as
15 Instruments endeavored to make the parasitic
transistor's beta (ratio of co7lec-tor current to
base curren-t) as low as possible, the typical beta
of 0.4 which resulted was not low enough to eliminate
the parasitic transistor as a power dissipation
20 problem.
When the system perforrns a switching operation,
there is a current spike drawn by the panel of 20 mA.
~herefore, a current of 8 mA (0.4 x 20 mA) will
flow through the base-collector junction, resulting
25 in an instantaneous power dissipation of 800 mW
Eor each of the 32 outputs of the chip. The only
thing which prevents -the chip rom immediately self-
destruct:ing is the fact that the current spike lasts
only 300 nS. For purposes of comparison, the
30 c~ampin~ diode portion of the parasi-tic transistor
dissipates only 50 mW of ins-tantaneous power, less
-than one-tenth that dissipated by the parasitic
r transistor. The time-averaged parasitic power
consumed may be as high as 384 mW per chip.
Another type of power dissipated by -the driver
chips is notch dissipation power. The term "notch"
3P~
derives ~rom the level of voltage supplied by the
driver chip's to~em-pole outputs.
If an oscilliscope is placed across the voltage
supplied to the elec-trode and ground, the tr~ce
generated when a vol-tage pulse is sent to the
electrode would initially rise to close to 100 volts,
and then, for a fraction of a second, will drop several
vol-ts beEore re-turning to the lOO~volt level. The
drop in voltage level, being very short, makes the
oscilliscope -trace look like it had a notch removed
from it; hence, -the term voltage notch.
The voltage notch is caused by the high current
drawn by the electrodes, which is approximately 20 mA
iE all 512 cells are being supplied with the
voltage pulse. This current causes the transistors
in a driver chip totem-pole output to develop a
voltage drop which causes less than the 100 vo-ts
to be applied to the elec-trode. The high transis-tor
in the totem-pole of the Texas Instruments chips will
develop an 8.5-volt drop, and the low -transis-tor will
develop a 2.5-volt drop.
Notch dissipa-tion power is the power dissipated
in the switching transistors of the totem-pole, and
the large amount o~ notch dissipa~ion power is caused
by the excess voltage drop across the swi-tching
transistors. 5ince the voltage drops are re].atively
high, a considerable amount oE power must be
dissipated by the switching transistors. The average
power per Eully loaded electrode is 1.3 mW, and -the
power dissipated in these switching transistors due
to notch dissipation power may reach a time average
level of about 39 mW per driver chip.
"'~;'J;'~ The cumulative effect of all o~ the above power
clissipatlon problems in the integrated circuit chip
is that the power dissipated will cause the chip to
operate at a fairly high temperature. I-t has been
observed tha-t the temperature rise of the driver chip
case is over 75C in an ambient environment of 23C.
Since it is generally required that the drive
electronics be encased in a sealed uni-t, the
possibility of failure due to power dissipation i,n
the driver chips becomes even greater. It has been
found that the operating life of a driver chip in
a circui,t using the above-described advanced technology
is only hours to days.
The next problem present in the Texas Instrumen-ts
driver chips is an ou-tpu-t pulse fall time which is so
fast that it genera-tes high instantaneous currents
which will cause noise genera-tion, disrupting system
performance. Both chips have fall times of 30 to 50
nS. The instantaneous current may be calcula-ted by
using -the formula i = c-dv/dt. The capacitance fGr
a typical 512 x 512 panel is 3500 pf, the voltage
change is :L00 V in 50 nS. The ins-tantaneous current
is -thereby 7 Ar a -tremendous amount even for a short
time. This current will cause a voltage to be
induced in nearby interconnecting wires, and this
voltage will cause logic errors ln the system.
In selecting the r,ise time and fall time of the
voltage pulse which is supplied to the electrodes,
there is a compromise involved. If the transition
between voltage levels is too slow, the plasma panel
display cells/ or intersections between X and Y
electro~es, will exhibit poor memory and light emitting
characteristics. Under normal circumstances, the
discharge causiny the emission of light pulse and the
,,,,,, execution of a write or erase operation occurs at a
point on the pulse where the peak voltage level of the"'' -' 'i ' " ~'~ pulse has been reached. Howe~er, if the transition
time is too slow, this discharge will have a tendency
to occur during the rising portion oE the pulse r
before the peak voltage has been reached. The result
is a weak discharge causing poor memory and poor
light emit-ting characteristics in the plasma panel
s~stem.
In contrast, too Eas-t a transiti.on time will
cause noise to be generatecL in the system, gi.ven
the relatively high voltage of about 100 volts that
is being switched. The Texas Instruments driver
chips have fall times of 30 to 50 nS~ If an
electrode of the plasma panel ls charged to 100 volts
in 50 nS, the instantaneous current flowing through
the charging circuit is appro~imately 7 amps. Since
the physical size of a typical plasma display panel is
1 foot x 1 foot, the presence of 512 X-electrodes and
512 Y-electrodes in that area indicates that these
electrodes are extremely close together.
Interconnecting wires to the plasma panel have been
found to have approximately 1 nH of inductance and
the extremely high instantaneous current will
therefore cause voltage drops of several volts in
adjoining wires, which will result in logic
errors in the plasma display pane]. system.
Transition times of between 200 and 400 nS are
generally considered ideal. ~hile the rise times of
the Te~as Instruments driver chips fall within this
range, the fall times are much too fast. The result
of using the Texas Instruments driver chips is an
unacceptablv large number of logic errors.
The next problem associated with these driver
chips is caused by the vol.tage notch described above.
In addition to being a power dissipation problem, the
large voltage notch imposes constraints on the design
of the s~stem. The voltage notch, parti.cularly the
8.5 V drop in the high state, cause the voltage
applied to the panel to be dropped from the desired
100 V to about 92 5 V, when the selected electrode is
being driven to the high sta-te.
3~3~
This lesser voltage level is very near the absolute
~imum required voltage, and any further losses
will cause a Eailure in the operation of the panel.
Since no further loss can be tolerated, precise
reyulation of the power supply, the use of hiyh-
precision components, and careful lavout oE the system
are mandatory. The plasma display panel itself may
have to meet more riyorous standards. All this leads
to higher produc-t cost, and less flexibility in
making system trade-offs.
In addition, a 102~ ~ 1024 panel could no-t be
driven by -these driver chips, since such a panel. would
draw approximately 40 mA Erom each IC, increasing
the voltage notch. Therefore, these chips are
limited to driviny a panel no larger than a 512 x
512 size.
There is also a logic error in the SN7~501 driver
chip. The chip is switched from its low output -to
its high output by a curren-t booster (responsible for
the boost current power dissipation problem described
above). This current booster is essentially a
bi-level current source. When the driver chip output
is in its low s-tate, 10 microamps are supplied.
When a logic signal indicates the driv~r chip is to
gO high, the curren-t booster supplies a 2 rnA boost
current, causing the pull-up out?ut transistor to be
driven on.
The logic error occurs when the Strobe input
pin of the chip (used for the address pulse lnput) is
held low and the sustain pin (used :Eor the distributed
conditioning input) is brought high. This logic
state should cause the driver output to quickly go
to its hi.gh state. The boost current, however, is not
applied, and the output is a slowly ri~ing rarnp,
taking 5 to 10 microseconds to reach the high state.
3~3~
] o
Since an operation on the panel may take less
than the 5 to 10 microsecond rise time o-f the pulse,
it is not o~ any use in addressing the panel. In
the past, systems have been desi.gned around this fl~w
resulting in inefficient and inconvenient operations
being necessita-ted.
Summary of the Invention
In order to understand the operati.on of the present
invention, a brie~ descrip-tion o-f the operation of a
typical plasma panel system and its sustain and drive
circuitry is necessary. There are four control ~unctions
that are used to operate an AC plasma panel: the
write function, the erase func-tion, the sustain function,
and the bulk-erase ~unction. The write function causes
a selected cell on the panel to be charlged ~rom the
"off", or non-light emitting state, to the "on",
or light emitting state. The sus-tain -function
maintains the sta-te of all cells in the panel, i.e.,
causes "on" cells to remain on, and "off" cells to
remain off. The sustain function also causes the
"on" cells to emit light. The erase function
causes a selected cell to be changed from the "on"
state to the "off" state. The bulk-erase function
causes all "on" cells in the panel simultaneously to
be changed to the "off" state.
Operation of the ~our control functions is
generally con-trolled by four logic signals: the X-
sustain signal XS, the Y-sustain signal YS, the
X-~ddress Pul.se XAP and the Y-Address Pu].se Y~P.
These signals, generally supplied by a waveform ROM
(Read Only Memory), are diyita]. pulse trains typically
., . ,, .. , , . . .~ ~ ...... ..... .
operating at a ~re~uency of 50 kHæ. The logi.c signals
are supplied to the sustain and drive circuits,
and cause these circuits to execu-te the four con-trol
functions on the panel.
~ qt~3~
The driver chips are used to drive the elec-trodes
in the plasma panel. Vo:Ltages supplied to the
electrodes are of two types: sustaining and pulsinc~.
The sustain voltages perform -the sustain function
described above. The pulsed voltacJes are used to
write, or turn cells "on", and to erase, or turn
cells "oEf". It is during the switching operation that
-the pulsed voltages are generated, and the problems
described above occur. The driver chips supply
lO these pulsed voltages only to the cells to be written
or erased. This selective supplyiny is the second
function of the driver chips.
The present invenkion solves the problems
inherent in the driver chips by adding to the
15 circuitry two voltage pulser circuits, one for the
X-axis, and one for the Y-axis. The pulser circuits
are inserted between the sustain circuits and the drive
circuits. The Y-voltage pulser circuit provides a
positive pulse, and -the X-voltage pulser circuit
20 provides a negative pulse.
The voltage pulser circuits are used -to turn
the high voltage level supplied to the electrodes
by the driver chips on and off, this high voltage
level being -turned off wher.ever the driver chips are
25 not performiny an addressing function, i.e., a write
or erase function~ The high level voltage is turned
off by connecting the high level input of the driver
chips to the ground input of the driver chips.
For normal sustain operation and during the time
30in write and erase operations when a pulsed voltaye
is not to be sent to -the electrodes, the voltage pulser
circuit corlnects the driver chip yround lead to the
high voltaye input lead. This has the effect of
shorting the parasitic np and pn junctions, as well
3sas the tc~tem-pole output transistors, making the chip
circuitry appear to be a small resistance in series
r~
with two parallel di~des, the diodes connected in
reverse polarity. The most obvious advantage is that
the parasitic -translstors are completely eliminated,
and with them goes the problem of excessive power
dissipation in the parasitic transistors.
A second effec-t of short circuiting the floating
ground and the high voltage input of the driver chips
is to eliminate notch dissipation power in the totem-
pole output staye of these chips by shorting the
10 output transistors~ Since the hiyh voltage potential
is no longer applied to the circuitry of the chips
during sustain operation, quiescent power dissipation
is no longer a problem. Therefore, it can be seen that
quiescent power, parasitic power, and notch dissipation
15 power are eliminated during the sustain operation
and the non-addressing portions of the write and erase
operations, which generally are the bulk of the time
the panel is in opera-tion.
The level shifting boos-t power is also eliminated
20 during sustain operation by the short circuit action
of the voltage pulser circuitry. Since a separate
sustainer circuit is used to provide the sustaining
voltage input to the floating ground o~ the driver
chips, the boost current generator is no longer
25 used to perform this operation. Such a separate
sustainer circuit is disclosed in copending paten-t
application entitled "MOSFET Sustainer Circuit For An
AC Plasma Display Panel", referenced below.
The low voltage logic power, which is a fairly
30 negligible amount, remains as the only one of the
five power components of the driver chips which is not
elim:inated or reduced by the present invention.
Therefore, it can be seen that the present inven-tion
eliminates most of the power which the driver chips
35 were required to dissipate in earlier applications.
3~3~
13
~he bene-fits of the present inven-tion are made more
apparent by the Eact that the temperature rise in the
chips caused by power dissipation with the use oE the
presen-t invention is only a 3 to 5~C rise over the
ambient temperature, compared to a '75C increase
without the present invention. By u-tilizing -the
presen-t invention, the early burn-out problem of the
Texas Instruments driver chips is substantially
eliminated.
The voltage pulser circuit u-tilizes the MOSFET
sustainer of the Weber application incorporated by
reference above, but applies that circuit to a new
use as a pulser circuit. The fast fall time of the
driver chips which resulted in system noise
generation is no longer a problem because the Weber
sustainer used for the voltage pulser circuitry has
a slew rate control which is utilized to prevent -the
fast fall -time inherent in the Texas Instruments
chips. Since the voltage pulser circui-t is
supplying the high voltage level to the driver chips,
by having the voltage pulser circuit go to its low
state, the slew rate of the transition beiny
controlled, the voltage supplied by the driver chips
will fall only as East as the slew rate controlled
25 falling voltage of the voltage pulser circuitry.
The shorting of the ground pin and -the high
voltage pin of the driver chips during the
sustain operation also has the efEect oE eliminating
the prohlem of lowered voltage supplied to the
30 electrodes because of the voltage notch. Since the
driver chips totem-pole-ou-tput stages are shorted,
the voltage drop developed across these transistors
~ is now limited to only a diode voltage drop,
appro~imately 0.7 volts, as contrasted with up to
35 ~.5 volts with the earlier sys-tem. During the time
1~
addressing pulses are being generated, the ground pin
and the high voltage pin of the clriver chips will not
be shor-ted. Since -the high voltage input is supplied
by the voltage pulser circuit, the slew rate control
will prevent the high current levels which caused
the voltage notch. There will be some degree o
voltage notch, but much less -than that experienced
without the voltage pulser circuit.
Since the voltaye notch is reduced, less precise
regulation of the power supply, less precise components,
and more flexibility in system layout are permitted.
I,ower product cost will also result.
Lowexing of the notch voltage also has another
important implication. The present invention would
allow the Texas Instruments driver chips to be used
to drive a 1024 x 1024 plasma panel, a significant
step forward since the larger panel allows much more
flexibility in creating graphic displays.
The final design defect of the Texas Instruments
driver chips is the internal logic error, which is
solved by utilizing the voltage pulser circuit to
bring the voltage output of the driver chip high. When
a write :Eunction is to be performed on the ?lasma panel,
the sustain pin (used for the distributed conditioning
input) is brought high and the strobe pin (used for
the address pulse input) is brought low, before -the
voltage pulser goes to its high state. By doing
this, the output of the driver chip will simply
follow th.e high voltage input from the voltage pulser
circuit. The logic error is bypassed in this manner.
Further advan-tages of the present invention include
.. ... ~ . ~ .. .. , ~ ,.. .
the provi.sion for expansion to include operating modes
and features which may be developed in the future.
Should another manufacturer design and build a driver
chip, that driver chip may well have operational
characteristics different from the Texas Instruments
3~
driver chips. The drive elec~ronics Lmprovements ~f
this i~ven~n provide ~ransparency to ~hese different
characteri~tics.
~lore partiaul.~rl~, there is provided:
A circuit for a plasrna panel comprising:
an integrated circuit comprising:
a first pair of transistors, connected in totem
pole, between a first terminal and a second
terminal, said pair of transistors alternatively
conductive to alternatively connect an output
line to said first terminal or to said second
terminal;
a second pair of transistors, outside of said
integrated circuit~ connected in totem pole
between said first terminal and a voltaqe source,
said second pair of transistors alternatively
conductive to alternatively connect said second
terminal to said first terminal or to said
voltage source.
There is also provided:
A circuit for a plasma panel including an
integrated circuit having a pair of power input terminals,
which selectively connects a voltage source to said panel,
comprising:
a circuit connected between said voltage source
and said integrated circuit for connecting the power
input terminals of said integrated circuit together
and thereby eliminating quiescent power consumption at
selected times.
'rhere is also provided:
Apparatus for reducing the power consumption in
an integrated driver circuit for an AC plasma panel,
comprisinq:
means for selectively disconnecting the power
from said driver circuit; and
means responsive to a stored complex waveform for
controlling said disconnecting means.
3'~
-15a-
~here is further provided:
A system for controlling the generation of
waveforms for an AC plasma panel, driven by driver chips,
2ach of which has a low voltage input terminal a~d a high
voltage input terminal, comp:risinq:
means for generatin~ a first group of waveforms
for controlling complex sustainer waveforms to be
supplied to said panel;
means for generating a second group of wa~eforms
for co~trolling the high voltaqe supplied to said hiqh
voltage input terminals of said driver chips only when
a write or erase pulse is to be supplied to said panel
by said driver chips; and
means for generatinq a third group of ~avefor~s
for controlling said driver chips, so that said driver
chips supply said high voltage to said panel to
perform write or erase operations.
~ hese and other advantage~ of ~he present invention
are be6t understood through reference t~ the drawinys,
in which:
Figure 1 is a bloc~ ~iagram of a typi~al plasma
display pa~el and its drive and sustain electronics;
~ isure 2 is a ~chematic diagram of the ~witching
circu;try for a ~ingle output of the T~xas
Instruments driver chips, used in the driver circuits
of Figure l;
Figure 3 shows the logic error inheren in the .
Texas Instruments driver chips ~ Figure 2, and the
lo~ic input to the pins o~ the chips which wi~l eause
the error;
3~
Figure 4 i5 a block diagram of a plasma display
pan~l and its sustain nd drive circuitry, co~aining
the present invention;
Figure 5 is a schematic diagram of the ~-axis
~ustain, voltage pulser, and driver circ~itry for
the circuit shown i~ Fiyur~ 4;
Figure 6 is a schematic diagram of the X-axis
sustain, voltage pul~er, and driver circuitry for the
circuit shown in Fiq~re 4;
Figure 7, ap~ing ~ith ~g. 2, ~s a sch~mat~c diagram of the circuit
for deriving a floating V~cl from a ~round-based
Vc~l power supply shown in Figures 5 and 6;
Figure 8A is a schematic diagram ~f a single
output stage of the Texas Instruments ~ri~er chip as
lS ~exas Instruments in~ended it to be implemented;
Figure 8B is a schematic diagram of a single
output stage of a Texas Instruments driver chip as
it was actually integrated;
Figure 8C is a schematic aiagram of a single output
stage of a Texas Instruments driver chip with the
voltage pulser circuit of the present inven~ion being
used to short the ground and high volta~e inputs of
driver chip, Fi~s 8A, 8B and 8C a~ring wi-th Figure 3;
Figure 9 is a waveform diayram showing the rise
and fall times o$ the Y-driver output shown ~n Figure
5 as controlled by the Y-pulser output and the logic
control si~nals YAPD and YAPP;
Figure 10 is a waveform diagram showing rise
and fall times of the X-driver output shown in
Figure 6 as c~ntrolled by the X-pulser ou~put and the
`` - ~ logic contro]. signals XAP~ and XAPP; and
Figure 11 is a wa~ef~rm diagram showing the logic
failure of Figure 3, and the manner in which it is
remedied uti:Lizing the present i~véntion.
17
_t iled Description of the Pre_ rred Embodiment
A plasma panel 70 r as shown in ~igure 1, is driven
by an X-axis drivex circui1 250 and a Y-aY~is driver
circult 150. A general descrlption of the circui-try
of Figure 1 is provided be:Low, to aid in the
unders~anding oE the present invention.
~ pair oE sustain circui-ts 210 and 110 are
used to provide -the sustain signa] to the driver
circuits 250 and 150, respectively. Alternatively,
many prior ar-t plasma display driver circuits
u-tilize an inherent sustaining capability of the
Texas Instruments driver chips SN75501, and
thereby eliminate the sustain circuit 210. Float
circuits 211 and 111 are used to supply -Eloating
supply levels o~ Vccl, the low voltage used to power
the logic circuitry, and Vcc2, the high voltage used
to drive the panel/ to the circuits 250 and 150,
respectively. The X-axis sustain circui-t 210 i.s
controlled by an X-sustain signal XS, and the Y-axis
sustain circuit is controlled by a Y-sustain signal
YS. The addressing of individual cells of the panel
70, to accomplish selec-tive writing and erasing of
these cells, is controlled by an X-addr~ss pulse XAP
and a Y-address pulse YAP, supplied Erom a waveEorm
ROM (Read Only Memory, not shown) through a pair of
level shi~t circuits 2~0 and 1~0, which are required,
since the driver circui-ts 250 and 150 operate on
floating ~rounds. The X-address information and
Y--address information is supplied to the driver
circuits 250 and 150 through a pair of level shift
. circuits 93 and 91, respec-tively, and identifies
which cells on the plasma panel 70 are to receive the
~ X and Y address pulses.
The X-border sustainer 86 and the Y-border
sustainer 88, and their logic -timing and con-trols
82 and ~, respectively, are used to provide suE~icient
?~
18
free particles so that write operations can be
carried out with complete a.ccuracy.
Figure 2 shows the schematic diagram Eor a
single output stage in a Te~as Instruments driver
chip used in the driver circuits 2S0,150 (~igure 1
to drive the electrodes in the plasma pane]. 70.
A totem-pole output stage is designed with two DMOS
transis-tors, pull-down transistor 301 and pull-up
transistor 302. For a sustain function, pull-down
transistor 301 will be turned on, so that the output
325 will be supplied the voltage level of the outpu-t
from a sustain circuit, supplied to terminal 29~.
To address a cell, -the logic siynal input a-t 298
will go from 0 to 1, and will cause the pull-down
transistor 301 to turn off and the pull-up transistor
302 to turn on. When pull-up transistor 302 is on,
the output 325 is connected to terminal 296, which i5
the high voltage input of the driver chip. Capacitors
311, 312, and 313, an inverter 320l and a Zener diode
322 are used to properly bias and operate the system.
A transistor 305 and a current source 300 are used to
switch rom the low output to the high output. The
current source 300 is a bi-level current source,
triggered by the logic inpu-t 298. The normal current
supplied by the furrent source 300 is 10 microarnps,
but when the logic input 298 indicates that the circuit
is to switch to the hiyh level, the current is boosted
to 2 mA :Eor 600 nS. The eEfect of -this boosted
current is to turn -the transistor 302 on fairly
~uickly, but at a fairly large cost in terms of
power dissipation.
The SN75501 chip has a logic error which will
result in thLs boost current not to be applied to
the outPut stage for cer-tain combinations of the
susta.in pin (used for a dis-tributed conditioning
input) and the strobe pin lused or the addressing
inpu-t). These pins, not shown in the drawings, are
'33~
lg
~nput: to the driver chip r ~nd ~re described in
T~3xa~ Instrument~ data booXs. ~i gure 3 ~hows t~he
seguencing o the lc:~gic inputs ~o the 7~;ustain ard
~trobe pins of the driver ~:hip~ an~ the output which
will re~ult. It can be ~!3een Shat when th~ ~trobe i6
high ~t a time when al 6u~;tairl pulse i5 ~pplied, the
Ib~i: current i~ properly applie~ ~nd ~he ou~put
will ~ ~he de~ired ~quare wave. ~owever, if the
~trobe i~ held low, ~nd the ~ustain i6 brought high,
the boos~ c:urrellt is no~ ~pplied, and the ou~put
i.s ~ rising ramp rather than a ~are wa~ve. 5ins:e
the ri6e tim~, which varies ~Erom chip to chip, is
typically S to 10 micro~;ec~nds, and an operation
performed on ~he panel may take well less time than
1~ 2 ~icrosecor:ds, the pulse will nQt reaçh its peak
while the operation is ~eing perormed. ~he result is
~n operation which ~oes nt~t properly perform the ~urc:tion.
l!rhe present invention ~ol-Jes the a~ove-described
problems by controlling the supply o high ls~el
voltage t~ the ~river chips contained in driver
~:ircuits 2S0 ,150 (Figure 13 ~ ~he dr;ver chips,
Texas ~nstrultLents SN75500 an~l ~N75501, utilize the
high voltage.~upplied to them orlly wh~n pulsing
~luring write E:nd era~e opera~ic)ns.
~he present $nventil:>n removes the high voltage
level from ~he high volta~e ~ nput lead 296 of the
dlriver c:hips, l!~nd kies this high volkage ~ nput lea~
of the driver chips to the ground lead 294 c~f the
driver chip~. By controlliIlg ~he times when high
voltage is ~upplied to the dri~er :hips, addres~ing
operations caLn ~ti~ 1 be performed. During all times
when th~ hi~h vc>lt~ge pul~e i~ not required to
perform a write or erase operation, the high voltaye
input of the chips will be -kied to the ground of the
chip. sy tying these two :inputs together, most
of the power dissipation problems of the chlp are
eliminated. The manner in which the other problems
inherent in the driver chips are eliminated w.ill
become apparent later in the specifica-tion.
The operation of switching the hiah voltage input
to the driver chips on and off and yrounding the high
voltage input of the chips to the grouncl of -the
chips when -the high voltage input is turned o:Ef is
performed by vol-tage pulser circuits. These voltage
pulser circuits are of the dual MOSFET sustainer type,
as described in the above-referenced and incorporated
application entitled "MOSFET Sustainer For A Plasma
Panel Drive System".
Figure 4 shows the voltage pulser circuits
170,270 of the present inven-tion installed into the
circuit of Figure 1. Float circuits 213, 215, and
111 are used to supply the voltage pulser circuits
170,270 with floating levels of Vccl and Vcc2,
and also-to supply the driver circuits :L50,250 with
floating Vccl power.
The voltage pulser circuits are controlled by two
logic signals, the X-Address Pulse to Pulser XAPP
and the Y-Address Pulse to Pulser YAPP. These pulses
are supplied via level shift circuits 141,241. The
address pulses supplied to the driver circuits 150,250
are now labeled Y-Address Pulse to Driver YAPD
and X-Address Pulse to Driver XAPD; these pulses
perform the same functions they performed in the
~, ,.. . ~ ~ .......... .
circuit of E'igure 1.
Figure 5 is a schema-tic diagram of the Y-sustain
circuit 110, the Y-voltage pulser circui-t 170, and the
Y-axis driver circuit 150, with the variou~ components
of Figure 4 shown in dot-ted lines in Figure 5. The
21
Y-sus-tain circuit 110, -the float cireuit 111, ancl the
level shift 140 operate as they have ln circu:Lts
not utilizing the voltage pulser circuit 170. For a
further deseription of these circuits, see the
above-incorporated applica-tion entit,led "Constant
Da-ta Rate srightness Cont~ol For An AC Plasma Panel".
The high voltage output of the float circuit
111 is on line 13~. This high level vol-tage was
supplied directly to the dri-ver chips on line 152
in applications not using the voltaye pulser circuit
170 ~Figure 1). The vol-tage pulser cireuit 170 acts
to control switching of the high level voltage on line
134 to the driver chips on line 152.
When YAPP is at a logic level of 1, the eon-trol
circuitry 172 will eause the pull-up transistor 176 to
eonnect the high voltage supplled on line 134 to the
positive voltage input o~ the circuit 150 on line
~52 and will cause -the pull-dGwn transis-tor 17~ to
be non-conductive. When YAPP is at a logic level of
0, the control circuitry 172 will cause the pull-down
transistor 17~ to be conductive, and the pull-up
transistor 176 to be non-eonduetive, switching off
the high voltage supplied by the line 134 and
conneeting the positive voltage input 152 o~ the
driver circuit 150 to the floating ground 160,
whieh is the ground input Eor the driver cireuit 150.
This ]ater condition exists during sustain operations,
when YAPP will be at a logie level of 0, so -the high
voltage will not be supplied to the driver ehips.
Even during write or erase operations, the high voltage
will not be supplied to the driver chips during the','~-' ' `'` '1~' entire function; rather, the high voltage will be
supplied to the driver chips only during the actual
time that a pulsing operation utilizing this high
voltage is occurring. In this way, i-t can be seen
that the Y-voltage pulser eircuit 170 is itsel-E
performing the pulsing operation whieh the Y driver
22
chips performed in earlier applica-tions. Since the
transistors 176,17~ in the Y-volta~e pulser circui-t
170 need not meet the sarne constraints imposed upon
Texas Instruments in the development of their
integrated circuit, and because these transis-tors
are outside of the case of the driver 150, they
do not have any power dissipation problems. Thus,
the addition of the voltage pulser circuit 170 will
not adversel~ afect the system in any way.
The circuitry controlling the X-axis driver 250
is shown in Figure 6, and it differs from that of the
Y-axis circuitry in that the X-axis driver circuit
250 includes SN75501 driver chips, which are designed
or negative pulsing. In ncgative pulsing, ins-tead of
adding a pulse on top of the sustainer wave~orm in
order to address the panel, a voltage is subtracted
from the sustainer waveform. The X--sustainer 210 is
exactly~the same as the Y-sustainer, and it functions
in the same manner.
A 1Oat circuit 213 is used to supply the X-vol-tage
pulser circuit 270 with a floating ~CCl~ and to supply
the pull-down transistor 274 with the floating -Vcc2
voltaae level. The -Vcc2 floating voltage is supplied
b~,~ a capacitor 278 and a diode 279 to line 2~7. The
floating Vccl is referenced to line 2~7, and is
supplied to the ~-voltage pulser circuit 270 on
line 2~1 by a convert~r 217, which will be described
in de-tail below. A second float circuit 215 is used
to supply the driver circuit 250 with a floa-ting
Vccl on line 25~ with reference to line 260. This
second float circuit 215 contains a conver-ter 219
which is identical to the converter 217.
5 ,.~ A schematic for this converter is shown in Figure
7. Resistors 290 and 292 are used to bias an FET 280,
one of the resistors 290 being variable. ~dditional
componen-ts of the circuit are a diode 282,
a Zener diode 286, and a capacitor 28~. The FET 2~0
;
23
acts as a cons-tan-t current source and will therefore
be adjustable by the resistors 290 and 292. The
voltage supplied at the ou-tputs is :Eloating with
respect to the grounded Vccl input. Although this
circuit is the preferred embodiment, any circuit
which wi.ll supply a Eloating level of Vccl is
acceptable.
The operation of the X-voltage pulser circuit
270, shown in Fiyure 6, is much the same as the
operation of the Y-voltage pulser circuit 170
descri.bed above. However/ since the X-axis ci:rcui-try
is designed for negative pulsing, when the pull-down
transistor 274 is conductive, and the pull-u? -transistor
276 i.s non-conductive, line 260, the negative voltage
input o-E the driver chips (supplied to the ground
input of the chips), is supplied with the voltage
level Vcc2 lower than the level on line 252, the
floating ground of the driver chips (supplied to the
high voltage input pin o-E the chips). This -Vcc2
is applied only during the addressing operationA
The pull-up transistor 276 is rendered conductive,
and the transistor 27~ non-conductive, except when
address pulses are needed during an erase or write
operation. When XAPP is at a logic level of 1, the
transistor 276 will short the negative voltage input
260 and the floating ground 252 of the driver chips.
When X~PP is at a logic level of zero, the pull-down
transistor 27~ will impress a -Vcc2 pulse on the
sustain signal, to be used for write and erase
operations.
.... . Therefore, for bo-th the X and Y axis driver
circuits, 250, 150, during operation of the system
when voltage pulses are not needed, th.e negative
voltage :input 260 and th~ floating ground 252 to the
X-clriver circuit 250 will be shorted together by the X-
voltage pulser circult 270, and the positive voltage
input 152 and the floating ~Jround 160 to the Y-driver
circuit :L50 will be shorted together by the Y-voltage
pulser circuit 170.
r~
24
Referring again to Figure 2 I two parasi-tic
-transistors 303 and 304 are shown. The desired
circuit Eor the Texas Ins-truments driver chips
includes a pair of clamp diodes, which are shown in
Figure 8A as ~303 and D304~ The diode D303 would
prevent -the outpu-t from falling lower than the level
oE the nega-tive voltage input 260 / which was
connec-ted to terminal 294 ~ The diode D304 functions
to prevent the output 325 -Erom risiny to a level
higher than that o the floating ground input 252 ~
which is connected to -terminal 296~ In the process
of fabricating the diodes D303 and D304 ~ the parasitic
hipolar transistors 303 and 304 r shown in Figure 8B,
were created. The present invention connects the
high voltage chip input 296 to -the ground input 294
when the system is not pulsing, so that the circuit
shown in Figure 8C is the ne-t result The -terminals
294 and 296r connected together, are shown as the
terminal 295 in Figure 8C. These terminals 294 r 296
are shorted,as described above, by the pull-down
transistor 174 of the Y-voltage pulser circuit 170
(Figure 5) ~ or by the pull-up transistor 276 of the
X-voltage pulser circuit 270 (Figure 6)~ The
resulting circuit of E'igure 8C has a resi tance 308,
representing the inherent resistance o-f the diodes
D3031 D304~ connected in series with a pair of ideal
diodes, which are connected in parallel, in reverse
polarity. These diodes are the diodes ~303 and D304
desired in the Texas Instruments chip. The other
junc-tions oE the transistors 303 and 304 ~ shown in
. . ~ Figure 8E3, are eliminated from the circuit, becawse
they are shorted out by the shorting of terminals
294 and 296~ Therefore, power dissipation problems
of the parasitic transistors are comple-tely eliminated
except during -the relatively short period of time
that address pulses are being generated.
~6~
A second problem which is solved by shor-ting -the
terminals 29~ and 296 toge-ther is ~he elimlnation of
the notch dissipa-tion power during the time the
circuit is not pulsiny. During this time, there is
no longer a voltage drop across the pull-up and
pull-down transis-tors 301, 302 in the integrated
circuit chip. Even when the circuit is pulsing
during a write or erase operation, the voltage pulse
has a maximum slew rate determined by the voltage
pulser circuits 170~ 270. Since this slew rate
contro] will limit the amount of curren-t flowing
through the transistors 301, 302 in -the driver chip,
the voltage drop across these transistors is
substantially reduced~
Since the high voltage input and the ground of
the dri~er chips are shor~ed during all operations
other than when a pulse for an erase or write
function is occurring, -the sys-tem will draw no
quiescent power. Since this power is not drawn by
the chip, it does not have to be dissipated within the
chip. In addition, since circuitry external from
the chip is perEorming the sustain and pulse operations,
the number of times that the high level boost cwrrent
of the current generator 300 ~Figure 2) would be
required are greatly reduced, thus greatly reducing
the level shifting boost power which would normally
have to be dissipated within -the chip.
Therefore, during sus-tain operation and non-pulsing
portions of write and erase operations, the only power
dissipated by the chip is low voltage logic power.
Therefore, even if the system is operating in a 100%
addressing rate, the only time when power will be
dissipated by the chip is during the actual pulsing
period, which is approximately 10% of the overall
time. Therefore, approximately 90% of the power
dissipated in the chip is eliminated.
26
The method of elimina-ting the ast fall time
of the driver chip output and the resul-tlng system
noise generation is shown in Figure 9 for the Y-axis
circuitry, and in Figure 10 for -the ~-axis circuitr~.
A descrip-tion for the Y-axis circuitry is as
follows. Figure 9 shows the possible ways in which
the slew rate control of the voltage pulser can be
utilized to con-trol rise tirne and/or fall time. The
first example, controlling neither rise nor fall
~o time, is undesirable because of the first fall time
of the chips. The second example shows how rise
time may be controlled. The third example shows how
to control fall time, and is a solution to the
fast fall time of the driver chips. The final
example controls both rise and fall time, and also
eliminates the problem of fast fall time in the
chips. The sys-tem of the present invention, therefore,
presents a high degree of flexibility in that
both rise and/or fall time may be controlled.
The voltage pulser 170 is used to generate the
addressing pulse (Y-pulser outpu-t). The YAPP signal
shown causes the Y-pulser output voltage to be
generated. By supplying the appropriate YAPD logic
signal, the output of the Y d~-iver circuit will
con-trol the rise time, the fall -time, or both the
rise and fall time of the driver output voltage, as
described above, which is conducted to the Y-electrodes
on the plasma panel 70. By making the YAPD logic
signal go low at points a elther beEore, or simultaneously
with the occurrence oE YAPP going high, the driver
output will follow the rising ramp of the voltage
pulser output. On the other hand, by making the YAPD
Logic signals go low at points b, after YAPP has gone
high, the rise time is not controlled by the voltage
pu:Lser circuit, bu-t rather by the driver circuit.
The fall time may be controlled in a similar
manner. By allowing the YAPD logic signal -to return
t~
27
to the high sta-te at the points indicated by c,
either before or simultaneously with the YAPP going
low, the fall time is not controlled by the voltage
pu]ser circuit, and is allowed to fall as rapidly as
the driver circuit allows. However, b~ having the YAPD
logic siynal remain low until khe points indicated by d,
after YAPP has gone low, the driver ou-tput will follow
the pulser output, thus conkrolling -the fall time
of the pulse. The X-axis circuitry operates in a
similar manner, as shown by Figure 10. In this way,
the rise time and fall time may be controlled, and
problems associa-ted wi-th the fast fall time of the
driver chips are eliminated by allowing the voltage
pulser circuits to use their inherent slew rate
control circuitr~ to control the slew rate of the
driver output voltage.
The solution to the logic error is shown in
Figure 11, and is similar to the rise and fall time
solution just discussed. The left side of Figure 11
shows the output failure, and the right side shows
the solution. The logic signals shown in Figure 11
are applied to the sustain pin (not shown) and the
strobe pin (not shown) of the driver chip. The
solution is provided hy perforrning the pulsing
operation with the voltage pulser circuit 270. By
bringing the sustain pin high some period of time
beEore the pulse is to occur, the driver chip will
simply Eollow the X pulser output. Therefore, it
can be seen tha-t the solution to the logic error is
to bring the input to the sustain pin of the SN75501
chip high a suEficien-t period of time in advance of
the rise of the X-voltage pulser circuit 270
output voltage.
The notch voltage drop across the output
transistors 301,302 (~igure 2) of the driver chips
is also eliminatecl during the sustain function and
non-pulsing portions o:E -the write and erase -func-tions,
28
since transistors 301 and 302 are shorted by the
voltage pulser circuits 170, 270 (Fiyures 5 ~nd 6)
during these operations. The only voltage notch which
will appear is the voltage drop across khe diodes
D303 and D304 (Figure 8C), il:Lustrated by -the
resistor 308.
The voltage no-tch during the time that addressing
pulses are being performed is also considerably
smaller, as mentioned above, because the voltage
pulser circuits 170, 270 include slew rate controls.
The slew rate controls will llmit the amount of
current, -thus resulting in lower voltaye drops across
the transistors 301, 302 (Figure 2~ duriny -the
pulsing Eunction. Since the voltage no-tch is greatly
reduced, the characteristics of the plasma display
itself and the power supplies are not nearly as
critical, and thus the overall cost of the plasma
panel system may be reduced by using less precise
components.
It can therefore be seen that the power dissipation
problems of the Texas Ins-truments driver chips are
virtually eliminated. Four of the five power dissipation
factors, quiescent power, level shifting boost power,
paracitic power, and no-tch dissipation pow~r,
are completely eliminated during the sustain
operation and non-pulsing portions of the write and
erase operations. This is illustrated by the fact
that the temperature rise over ambient tempera-ture
is now only 3-5C as compared to a 75C rise in a
system not using voltage pulser circuits. The fas-t
fall time inherent in the driver chips has been
solved by using the slew rate control of the voltage
pulser circuits. Therefore, generation of system
noise is no longer a siynificant problem.
The notch voltage problem has been virtually
eliminated, allowing plasma design engineers
2~
consiclerably more leeway ln extending the versatility
of plasma panel operations and in achieving lower
system cost due to the use of less precise
components. In addition, the el.imination of the
notch voltage allows a 1024 x 1024 plasma di.splay
panel to be drlven. The loyic error inheren-t in
the design of the Texas Instruments driver chips
has been eliminated by using the voltage pulser
circuits to generate the output pulse used to address
the panel.
JBB/LSM:pb
