Note: Descriptions are shown in the official language in which they were submitted.
;i3
-- 1 --
"S IGNAL SAMPLING GATE CIRCUIT"
In a color video tape recorder for recording and
reproducin~ color si~nal and luminance signal by the
agenc~ of a magnetic tape, the brightness signal and
color signal are usually separately processed. In
recording, the luminance signal (i.e., Y signal) is
frequency modulated in a frequency deviation ran~e of
3.5 to 4.8 ~IHz, while the color signal, which is at
3.58 MHz, is frequency converted to a low frequency
signal at 688 kHz. Since the color signal is frequency
converted to the low fre~uency signal for recording 011
maynetic tape, in playhae]c what is called color noise
is proc3ueed in the reproduced image on the reeeiver
screen due to crosstallc between separate tracks. In
order to remove this crosstalk in the color signal, it
is in practice to record the eolor si~nal by inverting
the phase Eor every horizontal seanning period (1 H) for
a traek (A track) oE -the magnetic tape while recording
it in the eonsisten-t phase for another trac)c (B track).
In playbaek, the si~nal that has been recorded in the
A traek by inverting the phase Eor every 1 ~-~ is
subjected to phase inversion for every 1 ~I to recover
the original phase. The use of a plurality of heads
in the recordin~ and reproduction of signal with a
color video tape recorder ealls for various additional
controls. For example, in the ACC circuit the color
signal reproduced by A llead in the playback mode and
~9~2~i~
that reproduced b~ s head must be separately subjeeted
to ACC deteetion voltage processiny for the ACC aetion,
that is, the ACC eireuit must inelude separate ACC
deteetion voltage proeessing eireui~s for the A and
s heads respeetively. This means that a plurality of
hold eireuits for holdinc3 ACC deteetion voltage siynals
to be sampled must be provided. Where hold eireuits
~or holding ACC signals with respeet to signals from A
and B tracks, for instanee, respectively, it is an
important problem to correetly time the switehing of
these hold eireuits to the switehinc3 of heads.
Aceordinc3].y, a slgnal samplincJ cJate eircuit, whieh can
seleetivel~ suppl~ siynals Eor samplinc) to a plurallty
oE ho:ld eireuits under the eontrol oE a s~litehin(3 pulse
sic3nal, has been ealled for. Sueh a eireuit is desired
not only for the ACC aetion but also Eor precludinc3 the
mal~unetion of the eolor killer eireuit.
The invention seeks to provide a circuit suitable
$or supplyîng signals to be sampled, obtained from a
plurality oE signal heads in the eolor VTR, to
respeetive hold cireuits, and particularly it has Eor
its object to provide a si(3nal samplincJ CJate eircuit,
whieh is efEee-tive for suppressinc3 sa(3s occurring at
the transient time of switehing sic3nals from respective
heads one over -to anotner, thereby preventing the
malfunetion of the cireuit operated by the output
signals of the hold eireuits such as an ACC cireuit
S3
and a color killer circuit.
~noth~r object of the invention is to provide a
signal sampling gate circuit, which comprises sampling
transistors connected between a sampling signal
generator circuit and the aforesaicl hold circuits,
signals generated from the sampling signal generator
circuit being coupled through the sampling transistors
-to the hold circuits according to a first gate signal,
and switchlng transistors connected to the respective
sarnpling transistors and turned on by a second gate
signal, and in which one oE the sam~ling transistors
connected to the "on" sta~e one o the switching
transistors held "on" by the secollcl gate sic~nal is
adapted to be forcibly turned ofE irrespective of the
first gate signal for alleviating the interference
between the hold circuits.
A still further object of the invention is to
provide a signal sampling gate circuit, which permits
the use oE a common ACC detector circuit for both
recordlng and playback modes with such an arran~ement
that the frequency oE the input to the ACC detector
circuit is made the same in both the modes and that the
output of the ACC detector circuit is held according to
a head switch pulse.
A yet further ob~ect of the invention is to provide
a signal sampling gate circuit, in which the output oE
the ACC detector circuit is distributed to hold circuits
S3
-- 4 --
for respective heads according to a pulse Eor eaeh
track, and in recording the signal extracted from a hold
eircuit correspondiny to one of the heads is supplied to
~CC amp~ifier and also to color killer switch, that is,
in whieh the color VTR ACC detector output is also
utilized as a eolor killer siqnal.
This invention can be more fully understood from
the following detailed description when ta~en in
conjunetion with the accompanyiny drawinys, in which:
Fig. 1 is a schematic block diagram showiny an
embodiment of the siynal samplinc~ yate circuit aeeordiny
to the inventlon applied to a color video tape recorder;
Fiy. 2 is a waveform diayratn showing says oceurring
at the transient time o~ switchiny signals Erom
respeetive heads one over to another; and
Fig. 3 is a eircuit eonnection diagram showing a
specific circuit construetion oE the siynal sampling
yate elreuit aeeordiny to the invention applied to a
color video tape reeorder.
2~ The invention appertains to a siynal sampling gate
circui~ which is suited Eor the processiny oE color VTR
siyna] where the ACC detection voltaye in an ACC loop is
switch&~d for every track.
In the VTR system, usually one track of a maynetic
tape is made available for the recording and reproduc-
tion of a signal for one field. Yor the transfer oE
siynal to and from the magnetic tape, a plurality of
-- 5
ma~netic heads are provided on a cylinder which is in
frictional contact with the tape. This is done so for
the purposes of improving the resolution of reproduction
and the recording density on the magnetic tape.
Typically, two or four recording heads are provided
in this system. The invention will be described
hereinunder in conjunction t7ith a signal sampling
gate circuit employed in a tt~o-head color VTR.
In the color VT~ having two heads (A and E3 heads),
the A and B heads are each responsible to a sk3nal for
each Eleld. For example, signal oE od~ ELel(ls is
sup~liecl to the A h~ad, and sl9nal o~ eve~l E1e~tl~ to
the B head. In this case, an ACC action Eor maintainin~
a constant level of the signa~s handled by the A and
B heads is required. This essentially dictates the
necessity of providing separate ACC actions Eor the
signals oE the respective odd and even tracks in the
magnetic tape. In other words, independent ACC circuits
have to be provided for the individual heads. In
another aspect, at the time oE switchin9 oE a hold
circuit for holding the ACC detection voltage with
respect to the A trac~ and that for holding the ACC
detection voltage ~ith respect to the B track, transient
signal sags are produced, t~hich adversely affect not
only t~e ACC action but also tlle color killer action.
The effectiveness of the signcll sampling gate
circuit according to the invention for solving the a~ove
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problems in the color VTR and the useful effects that
can be provided to the color VTR system itself by
the incorpor.ation of the circuit according to the
invention wl.ll become more apparent from the following
description.
Fig. 1 shows a block diacJralll of a color VTR
incorporating the signal sampling c~ate circuit
according to the invention.
With the signal sampling gate circuit according
to the invention applied to the color VTR as shown in
F`ig. 1, it is possible to reduce ma].Eunction oE the ACC
and a color killer wilich makes uce o~ the ACC c1etection
voltacJe, use a common ~CC cletector c:i.rcl.lit .Eor modes Eor
the ACC action and color killer act.ion in both recorc~ J
and playback modes and provide the color killer action
in a mixer circuit where luminance signal and color
signal are mixed together.
Now, the embodiment of the signal sampling yate
circuit according to the invention applied to the color
VTR, shown in Fig. 1, will be described irst in
connection with the recording mode.
~ ^7hen ~:he recording mocle is set by a mode selection
switch SW0, moc]e selection switches Sl~11 and SW2 are
both set to the side of a recording (~) terminal.
In the recorc3ing mode, the signal to be recorded, at
a frequency fO (of 3.58 ~l7,), is supplied to the
R terminal side of the mode selection switch SWl-
i3
-- 7
Thus, the color signal to be recorded is Eed to an ACCamplifier 10. The ACC amplifier 10 amp]ifies the color
signal input to a predetermined level, and it provides
as its output a color signal amplified to the predeter-
mined level and at the frequency fO. For recording thecolor signal on magnetic tape, its frequency conversion
from the Erequency fO (3.5~ MHz) to a low frequency
f1 (688 kHz) is necessary. ~ low frequency converter
11 effects this low frequency conversion of the color
signal for recording. The color signal at fO men-tioned
above is Eed to a termina~ Tlo oE the frequency
converter: lL, ancl a si(3nal at a ereqllency o~ '} 27 M~z
(= fO -~ f1) is Eed Erom a Erequency converter 12 to
another terrninal Tll. The input to the terminal T
at the frequency (fO -~ fl), is obtained as a signal
at a frequency of (44 ~ 4)fH, appearing from an AFC
circuit 13, and the output oE an oscillator 14 which
is oscillatiny at a peculiar frequency of Eo = 3.53 MHz
are addikively comhined in the Erequency converter 12
mentioned above. Thus, in the recording mode the
frequency converter 11, receivin~ t~le signal at fO at
-the terminal T1o and the signal at (fO t- fl) at the
terminal Tll, provides the low frequency converted
signal output at fl (6~8 kHz). The low Erequency
conversion oE the color signal to be recorcled, ;s
coupled from the frequency converter 11 throuyil a filter
15 to a mixer 16, ~hich combines the color signal (C)
-- 8
and brightness signal (Y) to be recorded. lhe level of
the color si~nal fed to the mixer 16 is held constant by
an ACC loor~ which is formed by an ACC detector 17 of a
sync detection system, a signal samplin~ gate circuit 18
for coupling the ACC detector output to either hold
circuit l9A or 19B, a head switch circuit 20, a DC
amplifier 21 and the ACC amplifier 10 Wit}l the mode
selection switch Sl~72 set to the R terminal side.
As will be described hereinafter, to a playback
(PB) terlninal of the mode selection circuit SW2 in the
ACC loop a reproduced si~nal at 3.58 M[lz i-, Eed throu~Jtl
the outpu~ terrninclL T12 o tlle~ aEoremerltionell Erequcllcy
converter 11 and a 3.5~ MHz bancl-pass i1ter (BPF) 22 at
the time of the playback mode. The fact that the
frequency of the output of the mode selection circuit
SW2, i.e~, the input siynal to the ACC detector cireuit
17, is the same (3.58 MHz) at the time of the recordin~
mocle and at the time of the playback mode is very
important. In the recording mode~ whi:Le the co:Lor
signal (~0 = 3.58 MHz) is convertecl to lo~ Ereq~lency
signal, the ACC action is provided with respect to the
3.58 MHz signal. In the playbac~ mode, while the low
frequency signal at 688 MHz is fed to tne ACC amplifier
10, the ACC action is a~ain providecl with respect to
3.58 M~-lz si~nal ~hich is this time obtailled throu~h
frequency conversion in the frequerlcy converter 11.
The fact tllat the sarne frequency is handled in the ACC
- 9 -
loop at the time of both the reeording and playbaek
mocles means that a single ACC deteetor eireuit suffiees
for the ACC deteetion in both the modes. In other
words, with the cireuit eonstruction as sho~ln in Yig. 1,
a single ACC deteetor circuit can be commonly used for
both the recording and playback modes. The faet that
the ACC eireuit 17 ean be operative in both the
reeording and playbaek modes is attributable to the
use of a signal sampliny gate eireuit l8 aceording to
the inventi.on in the eolor VTR system sho~lrl in Fig. 1.
~3esides, the aE~plieation o~ the siynal salnplirly ~Jal:e
eireuit aeeordincJ to t~le inverltion to a eolor VTI~
system does not permi-ts the use of a eommon ACC deteetor
eireuit for both the reeording and playback modes as
mentioned previously, but also permits further useful
effects to be obtained as will be diseussed hereinunder.
The ACC deteetor eireuit 17 mentioned above
proeesses three different signals, namely eolor signal
in -the reeordincJ mode, siynal reprodueed by A heacl in
the playhaek mode and signal reprodueed by ~ head in
the playhaek mode. In this eonneetion, -the eircuit has
to be eonstructed sueh that it is possible to iden-tify
~hich one of these -three different signals the ACC
deteetion voltaye fed back to the ACC amplifier 10
appertains to in either recording or playhack mode.
The signal sampling ga-te circuit 18 according to the
invention greatly contributes to the solution of this
-- 10 --
prGblem .
In the playback mode, with the mode selection
switches SWl and SW2 set to the playback mode side,
the low frequency converted color signal at fl = 638 kHz
is fed from a head H2 which acts as a playbac]~ mode
head through the mode selection switc~l S~11 to the ACC
amplifier 10. This low frequency converted color signal
is frequency converted to the high frequency color
signal at fO = 3.58 MHz before it is supplied to the
ACC detector circuit 17. Thus, in the playbac]c mode
the frequency of the inpu~ signal. to the ~CC detect~r
ci.rcuit 17 is 3.S8 ~l~lz as in tlle recordincJ mo(le. The
ou-tput of the ACC detector circuit 17 is coupled through
a terminal T20 to -the signal sampling gate circuit 18,
~7hich is shown enclosed within a dashed rectangle in
Fiy. 1. The ACC detection signal from the ACC detector
circuit 17 is coupled to the aforementioned terminal
T20 of the signal sampling gate circuit 18, and a hurst
gate pulse, which controls the detecting operation oE
the ACC detector circuit 17 and also the operation oE
the signal sampling gate circuit 1~ receiving the signal
from the ACC detector circuit 17, is coupled to a
terminal T21. Further, a head switch pulse, which
is indicative of which one of the A ancl B heads is
providing the sigrlal being processed, is coupled to
a termi.nal T22. The result of the sync detection
processing with a 3.5~ ME~z C~ signal supplied through
2~3
a terminal T23 and the 3.58 MHz color signal supplied
from the mode selection switch SW2 is coupled to the
terminal T20 in synchronism to the afcrementioned burst
gate pulse. The ACC detection siynal appeariny at the
terminal T20 is seleetively coupled through the signal
sampling gate circuit 18 to either one of terminals
T25 and T26 according to the head SWitC}l pulse signal
coupled to the terminal T22. ~he signal sampling gate
circuit 18 is eomposed of sampling switch circuits 18A
and 18B. The burst gate pulse si~nal rom the terminal
T21 and head switcil pulse signal froln the terminal
l~2 are supplled to both the sam~llrlg swltch cire~lit~
18A and l~B. The sampling switch circuits 18A anc1 l~B
funetion to transmit the detection signal from the ACC
detector eireuit 17 to respective hold cireuits l9A and
l9B. At this time these cireuits are alterna-tely or
complementarily rendered conduc-tive in accordance with
the aforementioned head switch pulse signal. During the
period during which the head SWitCil pulse signal
indicates the A head, the ACC detection signal provided
from the ACC detector ciLcuit 17 during the pulse period
of the burst gate pulse supplied through the terminal
T21 is coupled through the sampllny switch circuit 18A
to the hold cireuit 19A while clurin~ the period durin~
which the head switell nulse signal inc1icates the ~ head
it is coupled throu~h the samplin{~ switch circuit 18B
to the holcl circuit 19B. It is to be noted in the
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operation of the signal sampling gate circuit 18 that
the conduction of either of the sampling switch circuits
l8A and 18B is determined solely hy the head switch
pulse siynal supplied to the terminal T22.
This has an effect of suppressing sit3nal sags Sl
and S2, as shown by dashed lines in Fig. 2I that ~ould
otherwise result at the transient time of switching of
the ACC detection signal with respect to the A head and
that with respect to the B head. Fig. 2(a) shows the
waveforms of the signal obtained at tl1e output terminal
T20 oE the ACC detector circuit 17 in F`ig. l, ~7hich
sho~s an e~arnple o~ application oE the sitJIlal salnplin~3
gate circuit according to the invention to a color VTX
system, Fig. 2(b) shows the waveforms of a signal
appearing at an output terminal T27 of the hold circuit
l9A whic'n holds the ACC detection signal with respect
to the A head, Fig. 2(c) shows the waveform oE a signal
at an output terminal T28 of the hold circuit 19B
which holds the ~CC cletection signal with respect to
the B head. The signal sat3s Sl and S2 as shown in
Figs. 2(b) and 2(c) cause malEunction of the circuit.
~lore particularly, in the case of the sit~nal sag Sl the
ACC voltage is unnecessarily increased in the portion
Sl is il1creased, so that the gain of -the color amplifier
is excessively reduced by the ACC action. In the case
of the signal sag S2, the things are conversed, that is,
the gain of the color amplifier is exces~ively increased
~12~
13 -
by the ACC action. Also, malfunction of the eolor
killer is eaused. These malfunetions are eaused by the
signal sags Sl and S2 for every field to eause eolor
irreyularities in the reproduetion from the color VTR,
partieularly on an upper portion thereof. This dra~baek
ean be overeome by the eireuit shown in Fig. 1.
More partieularly, the sags Sl and S2 shown in
Figs. 2(b), 2(c) would be eaused if there is a time
constant cireuit between the ACC detector eireuit on
one hand and the hold eireuits for holding the deteetion
voltage for every field on the other hand. The system
shown in Fig. 1, where the si-~nal samp].ln(J cjate eireuit
aeeordinc~ to the invention is applled to a color VTR, is
free Erom sueh a tlme constant elreuit that wou:Ld eause
signal sa~s as mentioned, that is, lt is free from any
cause for the generation of sags of the signal to be
held as the ACC signal. This is so beeause of the faets
that in the system of Fig. 1 the frequeney of the signal
input to the ACC detector eireuit 17 is 3.58 Ml~z either
ln the reeording or playbaek mode and that the ACC
cleteetor eireuit 17 itselc is construeted for eommon
use both in the recording and playbac}~ modes. In case
of the frequency of the input si~nal to the detector
eireuit is fO = 3q58 MHz at the time oE the playbaek
mode and fl = 688 kHz at the time of the recording mocle,
althouyh the ACC detector circuit may be commonly used
for both the recording and playback modes, it wouk1 be
- 14 -
necessary to provide time constant circuits for the
detector circuit input frequency differ between the two
modes. Otherwise, it would be necessary to provide
separate ACC detector circuits for the recording and
playback modes respectively. It is only when the
requirements that the ACC detector circuit is commonly
used for both the recordiny and playback modes and that
the frequency of the input signal to the ACC detector
circuit is the same in both the modes are met that it is
needless to provide any time constant circuit would
cause mal~ nctions of the ~CC arld color klller het~/een
the output terminal of the ACC detector circuits ancl the
input terminal of the hold circuits.
With the si~nal sampliny ~ate circuit 18 accordiny
to the invention applied to the color VTR system shown
in Fiy. 1, there is no need of providing any time
constant circuit between the output terminal T20 oE
the ACC detection circuit and the hold circuits 19A
and 19B, so that says with respect to the ACC detection
signal, that would cause malfunctions of the ACC and
color killer as described above, can he eliminated.
Thus, the arranyement that the ACC circuit 17
in Fig. 1 is commonly used for both the recording and
playback~ modes and tl~at the frequeilcy oE tile sicJnal
input to the detector circuit 17 is made the same in
both the modes does not only have the mere effect with
reyard to the circuit construction that the detector
~:~9~2~
- 15 -
circuit is used for both the modes, but also nas an
effect with regard to the operation that the mal-
functions of the ACC and color killer can be eliminated.
With the ~CC detector circuit input signal frequency
made equal in both the recording and playback modes and
with the provision of the signal sampling gate circuit
18 between the output terminal T20 of the ACC detector
circuit 17 which is constructed for common use for both
the modes and the input terminals T27 ancl T28 of the
hold circui.ts 19A ancl 19B, it is possi~le to eliminate
sac~s that would otherwise occ~lr on the si~Jtlals held by
the hold circuits 19A and 19B.
The hold signals obtained at the output terrninals
T27 and T28 of the hold circuits l9A and 19B are
coupled to the head selection circuit 20 according to
-the head switch pulse signal supplied to the terminal
T22. In the playback mode, the head selection circuit
20 selectively and alternately couples the signals
~rom the hold circuits 19A and l9B to a terminal T2g
according to the head s~itch pulse signal supplied to
the terminal T22. In the recordiny mode, the terminal
T29 of the head selection circuit 20 is held connected
to either terminal A or B to receive the signal
therefrom. At the time of -the recording mode, the
si~nal to be recorded is one obtained from an antenna
or a coa~ial cable, and at this time it is less likely
that the heads should be s~itched.
- 16 -
The ACC voltage signal obtained at the terminal
T29 of the head selection circuit 20 is coupled through
a DC amplifier 21 to the ACC amplifier 10 to control the
gain thereof. It is also used as a color killer signal.
~lore par-ticularly, it is also coupled in the pla~back
rnode through a DC amplifier 30 which is a color killer
siynal amplifier to a rnixer 40 in which a color signal
(C) obtained from the aforementioned 3~5~ MHz ~P~ 22
~hich converts the low frequency converted color signal
at El = 688 kHz to the high frequency color signal at
fO = 3.58 MHz and luminance siyna] (Y) are combinec].
The mixer ~0 has a color ~iller switch (no~ shown), and
in pla~bac)c it provides a color killer action acco~dill~J
to the output voltage Erom the output terminal I30 oE
the DC amplifier 30. The output terminal T30 is a:Lso
connected to the mixer 16 which is made operative in the
pla~bac} mode. In the recording mode the low frequency
converted color siynal at fl frorn the filter 15 and the
luminance signal are mixed in the mixer 16 which is
operative in this mode and the OUtp~lt oE the mixer is
recorded on the magne-~tic tape via a recorcling ilead H1-
The mixer 16 for -the recordin~ mode has a color ]ciller
switch (not shown), and the voltaye signal from the
output ~erminal T30 of the DC amplifier 30 to ~/hich the
aforementioned ACC volta~Je signal is coupled is utilized
as the color killer siynal. In other words the ~CC
signal obtained at the terminal T2~ mentioned above is
2S3
utilized as the color killer si~nal in both the
recordin~ and playhac~ modes. It is to be noted at
this time that the color killer action in the recording
and playback modes is provided by the respective mixers
16 and 40. To provide the color killer action by the
mixer 40 particularly at the time of the playback has a
siynificance. In playback the low frequency converted
color signal at fl = 688 kHz that has been produced at
the time of recordiny is reconverted to the original
hiyh frequency of Eo = 3.53 MHz. This hiyh Erequency
eolor si~nal ~t Eo is introduced to other circuits than
its own signal path througtl the Eloating eapcleltarlee
between eircuit elements. If it is introduced into
the mixer, undesired foreign colors appear on the
reproduction on the screen even if color killer ackion
is providecl in the color killer stage. Such malfunction
of the color killer ean be eliminated by providin~ the
eolor killer aetion in the mixer ~0 as shown in Fig. 1.
Fi~. 3 shows a eireuit diagram of an exclmple oE
the eireuit eonstruetion where tile signal samplin~ ~te
eireuit aeeording to the inventiorl is applied to a eolor
VTR. In Fiys. 1 and 3, like parts are desiynated by
like reference numerals.
Referriny now to Fig. 3, the mocle selection switch
eircuit S~11 selectively couples the hiyh frequency color
si~nal f0 from a terminal Rl and the low Erequency
converted color signal fl from a terminal PBl to the
LZ~3
- 18 -
ACC amplifier 10. Mode selection control signals are
coupled through resistors Rlo and Rll to transistors
Qlo and Qll respectively. For the recording mode, the
terminals T50 and T51 are rendered to a low level and
a high level respectively by the control signals. At
this time, the transistor Q1o is turned on, and the
transistor Qll is turned off. The potential on the
terminal Psl is thus brought to the ground potential,
and only the signal from the terminal Rl is impressed
upon the base oE a transistor Q12 to turn or~ tile
transis~or Q12~ whereby the si~nal fO is supuliecl to
the ACC ampliEier 10. For the playback mod~, ~h~
translstor Qlo is turned off while the transistor Qll
is turned on by the control signals at the terminals
Tso and T51. Thus, the terminal R1 is thus brought
to the ground potential, ancl the signal fl from -the
terminal PBl is supplied throucJh a transistor Q13 to
the ACC amplifier 10. The bases o~ the transistors Q12
and Q13 are biased from a voltac;e source E1 throucJil
respective resistors R12 ancl R13. A resistor R14 is
provided Eor permitting the signal impressed upon either
transistor Q12 or Q13 as an emitter follower output to
the ACC amplifier 10.
The.gain of the ACC amplifier 10 is controlled
by the signal selected by the mode selection S~itc[l
circuit S~11. The AC amplifier 10 is constructecl as a
differential amplifier ~ith transisto-fs Q20 to Q25 and
- 19 -
resistors R20 to R22. The signal obtained from the
load resistor R22 is output through the emitter of a
transistor Q26 with the emitter connected to a resistor
R23 as an emitter-follower output to the Erequency
converter 11 and switch S1~2- The signal fro~-n the mode
selection s~litch circuit Sl~l is applied as a change of
the terminal voltage across the resis-tor Rl~ to the
base of a transistor Q21 as a current source for the
aforementioned differential amplifier. Another current
source is constituted by a transistor Q20~ and a circuit
Eormed by a transistor Q27 conrlected to the base of
the transistor Q20 and resistors R2~, R25 and R20
becomes symmetrical with the circuit formed by the
first-mentioned current source transistor Q21 and
resistor R21 when either one of the transistors Q12
and Q13 in the mode selection switch circuit SWl is
turned on. In this arrangement, by making the opposing
resistances equal, extreme DC stability and practical
.immunity to the influence oE temperature changes can be
obtalned. The diEferential amplifier mentioned above
is ~iven its bias voltage by a circuit formed by voltacJe
source E2, a current source Il, resistors R26 to R29
and transistors ~28 and Q23. The emitter voltage on
a transistor ~29 is impressed as bias upon the common
base j~]ncture of the transistors Q23 and Q24 of the
differential amplifier, and the emitter voltage on a
transistor 2~ is impressed as bias upon tlle common
i3
- 20 -
base juncture between the transistors Q23 and Q24.
The transistors Q2~ and Q29 in the bias circuits are
connected as respective emitter follower in order that
the difEerential amplifier will not be in1uenced by
the impedance changes on the side of the voltage supply
E2- The bias circuits for the differential amplifiers,
i.e., the hias circuit for the transistor Q28 and
that for the transistor Q29~ are also constructed as
symmetrical circuits to each other for eliminating the
influence of temperature changes upon the differential
am~lifier. ~rhe constant current source ll is provided
to prornote the symlnetry oE the circuits. Tlle c~ain oE
the di~erenti.al arnpllfier which Eunct.ions as the ~CC
amplifier is controlled by the relative potent:Lals on
the base of the transistors Q23 and Q24 and on the
base of the transistOrs Q22 and Q25 This gain
control voltage is obtained by controllin~ the base
sicle impedance of the transistor Q28 by a circuit
formed by a transistor Q30 connected to the base of
the transistor Q2g and a resistor R30. In other words,
the gairl oE the ~CC ampliEier is deterrnined accordillg
to the ACC volta~e applied to the base of ~he transistor
Q30. lhe transistor Q30 is necessary for providing the
ACC action, and it is connected to the base side of the
transistor Q20 With the aforementioned constant
current source Il connected to this transistor, the
symmetry of the bias circuits for the clifferential
- 21 -
amplifier is enhanced, that is, the differential
amplifier is made less susceptible to telnperature
changes .
The signal appearinc3 at the output terminal ~10
of the ACC amplifier 10 is supplied to the frequeney
converter 11 ancl also to the mode seleetion s-7iteh SW2.
When the mode seleetion switch SW2 is set to the
recording mode side, the eolor sl~3nal at f0 = 3.58 ~IHæ
to be recorded is supplied froln the R terminal of the
switeh throucJh a eapaeitor Cl to the ACC detector
circuit 17. In the p.l.aybac~ mo(le, the color si.qnal at
fl = 683 kllz :is converted throucJh the rreq~lerlcy
eonverter eireuit 11 to the hi(3h frequeney signal at
f0 = 3.58 MHz which is supplied -t.hrough the capaeitor
Cl to the ACC detector eireuit 17.
The ACC detector eireuit 17 includes a dually
balancecl differential amplifier haviny transistors
Qsl to Qs3~ resistors R50, R51 and R56 and a eurrent
source I2, a bias c;.rcult for biasinc~ thi.s differential
amplifier and having volta~e sources E3 and E~ and
resistors R53 to R55, and an output eireuit havinc3 a
transistor Q59 and a resistor R57. In the ~CC deteetor
eireuit 17 of this construe-tion, the syne deteetion of
the 3.58 ~lllz CW si(3nal eoupled throu(]ll a eapaeitor C2 to
the terminal T23 and the 3.58 ~Irl~ reeordin~3 or playbae};
mode eolor signal eoupled from the output terminal of
the mocle seleetion s~itch SW2 -throuc~h the capacitor
3~19~S~
Cl is effected by the aforementioned dually balanced
differential amplifier in accordance with the burst gate
pulse supplied to the terminal T21. The de-tection
output is coupled through an emitt:er-follower transistor
Q59 to the signal sampling gate circuit 18.
To -the signal sarnpling gate circuit 18, are coupled
the burst gate pulse from the terminal T21 and the head
s~1itch pulse from the terminal T22. The signal sampling
gate circuit has a gating function to couple the output
oE the ACC detector circuit 17 to the hold circui.ts 19A
and 19B according to the head switch pul.se sigllal, ancl
accordi.ng to the invention it is .Eeatured ~ha~. ~hi.s
gating function depends solel~ upon the head s~itch
pulse.
The signal sampling gate circuit 18 has a
construction as described in detail hereinunder. The
emitter of the output transistor Q59 in the ACC detector
circuit 17 is connected through a resistor R60 to the
.base oE a transistor Q60 and is also connected through
a resi.stor R61 to the base of a tt-ansistor Q62 and also
to the collector of a transisto:r Q63- Tr~nsistors Q64
and Q65 are connected to the emitter of the respective
transistors Q60 and Q62. The transistors Q63 and Q65
are connected as a di~ferential pair, and their common
emitter juncture is corlnected through a transistor
Q66 to a constant current source I3. L,i~e~ise, the
transistors Q6~ and Q64 are also connected as a
- 23 -
differential pair, and their common emitter juneture
is conneeted throu~h a transistor Q67 to a eonstant
current source I3- The base of the transistor Q66 is
connected to the base of t~e transistor Q6~ which has
its collector connected to the base of the transistor
Q~0. The base of the transistor Q67 is connected to
the collector of the transistor Q69~ which has its
eollector connected -to the base of the transistor Q62.
The terminal T22, to which the head switch pulse is
supplied, is eonnected to the base o:E the transistor
Q69~ is also connected throuyh an inverter 60 to the
base of the transistor ~6~1. Thus, the heacl SWi.tCtl
pulses supp.lied to the base of the transistor Q6~ and
that supplied to t~le base o:E the transistor Q69 have
opposite polarities. Of the output terminals rr25 and
I~26 of the signal sampling gate circuit, the terminal
T25 is eonneeted to the hold cireuit 19A which ineludes
a resistor R70 and a capacitor C70 and the other
terminal r~26 is conneeted to the hold cireuit 19B whieh
ineludes a resistor R71 and a eapacitor C71.
The operation of the siclnal samplincJ cJate eircuit
18 having the eonstr~cti.on described above will now be
described. The output of the ~CC deteetor eireuit 17
is coupled from the emitter of the emitter-follower
transistor Q59 to the input terminal T20 of the signal
samplir~g ~ate circuit 18 according to the burst gate
pulse supplied to the terminal T21- The head switch
-- 2~ --
pulse supplied to the terminal T22 is supplied in
opposite phases to the transistors Q6~3 and Q69 with the
input to the inverter 60. The bias voltages are set
such that when the burst gate pulse of the negative
polarity appears at the terminal T21 the transistors
Q61 and Q63 are turned off while the transistors Q64
and Q65 are turned on. At this time the transistors
Q60 and Q62 are held in the on state during the
negative polarity burst gate pulse period. Since the
head switch pulse is coupled from the terminal T22 to
the bases of the transistors Q60 ancl Q62~ wit~l the
appearance of the positive polarity head switch pulse
(correspondin~ to the A head at this time) the
transistor Q69 is turned on while the transistor Q62
is turned off. That is with the appearance of the
head switch pulse of the positive polarity corresponding
to the A head the transistor Q62 is turned off while
the transistors Q60~ Q6'1~ Q67 and Q69 are turned on.
At this time the ACC detection signal corresponding to
the A head, obtained from the terminal T20, is coupled
through the emitter of the transistor Q60 to the hold
circuit 19A. If the level of the ACC detection signal
coupled to the hold circuit l~A at this time is low
the e~cess charge in the capacitor C70 in the hold
circuit 19A is discharged through the transistors Q64
and Q67 and current source I3. I~hile the head switch
pulse is of the negative polarity (correspondin~ to the
- 25 -
s head), the transistor Q69 which contributes to the
operation of sar,lpling the ACC detector siynal with
respect to the A head is "off", and the ACC detection
voltage sampled by the hold circuit 19A is held.
Similar operation to that described above with
respect to the A head takes place when the ACC detection
voltage with respect to the s head is held in the hold
circuit 19B. The gating ac-tion for coupling the ACC
detector signal to the holc] circuit 19A or l9B is
effeetecl as one of ~.he transistors Q60 and Q62 is
turned on while the otiler is turnec1 oE~ accorcliny to
the head switeh pu.l.se suppl:Led to the termillal T2
The hold signal selectively held in the hold
eireuits 19A and l9B according to the head switch pulse
signal, is eoupled throuyh the head selection switch
eireui-t 20 whieh is eontrolled by the mode seleetion
switch SWo to the DC amplifier 21 whieh DC amplifies
: the alternate ACC signals of the hold cireuits 19A and
.19B in synehronism -to the head swltch pulse si~nal.
The head seleetion switch circuit 20 couples the output
siynals from the terminals T27 and T2~ of the hold
eireuits l9A and 19B to the terminal T29 in synchronism
to the head switch pulse siynal. ~n other words, the
ACC aetion ~7ith respect to the color siynal derived
from the A head and the ACC action ~7ith respect to the
color signal derived from the B head are provided in
synchronism to the head switch pulse. To discriminate
- 26 -
which one of the A and s heads the color signal is
obtained from is necessary or providing the ACC action
particularly in the playback mode. In the recor~ing
mode, the color signal with respect to which the ACC
action is provided is not the signal obtained from the
A or B head but the signal obtained from a television
antenna or through a coaxial cable. The function of
the head selection switch circuit 20 is therefore
unnecessary at the time of the recordincJ mode. The
head selection switch circuit 20 is helcl inoperative
i.n the r~orc1ing mode hy arranginc3 such th~t th~
terrninal T29 of ttle head selection switch circuit 20
is connected to either terminal r~27 or T2~ while the
high or low level is set for the head switch pulse input
to the terminal T22 at the time when the recording mode
is set by the mode selection switch SWo-
The ACC detection signal is coupled through the
head selection switch circuit 20 to the terminal T2g
of the DC ampliEier 21 for DC amplification. The DC
amplifier 21 includes an emitter-follower transistor
Q80 ha~ing the base connected to the terminal T29, a
resistor R~,o connected to the emitter of the transistor
Q80~ amplifying transistors Q81 and Q82~ resistors
Rgl and R82, a diode D80 and a bias circuit formed by
transistors Q83 and Q8~ and resistors R83 to R86. Tlle
base oE the transistor Q82 of the differential ampliier
constituted by the transistors ~ol and Q82 is biased by
;3
- 27 -
a constant voltage VRefl which is provided by the bias
circuit mentioned. The ACC voltage appearing at the
terminal T29 is coupled through the transistor Q~0
to the base of the transistor Q81 which forms the
differential pair with the transistor Q82. The
different}.al pair of transistors Q81 and Q82 compares
the aforementioned constant voltaye V~e~l and the ACC
voltage, and current accordin~ to the result of the
voltage comparison flows through the diode D80 and
resistor R~2 to vary t~le anode voltage on the diode D80.
The im~e(lallce oE the ~CC ampliEier 10 looked E~om the
col:Lector side oE the transistor Q30 is controlled
according to the variation of the voltage on diode
Dgo which corresponds to the ACC voltage. Throuyh this
control the gain of the ACC amplifier 10 is controlled.
In this way, the ACC action is provided.
Irhe ACC signal described above is also coupled to
the DC amplifier 30 for generating a color killer signal
from the emitter of the transistors Q90 and Q91~ that
is, it is also used as a control siynal Eor the color
killer operation. The DC amplifier 30 is constituted
by a differential amplifier including transistors Qgo
and Qgl and resistors R90 and R91. This differential
amplifier is biased by the aforementioned hias circuit
for the DC amplifier 21, and its bias voltage is set
to be lower than a constant voltage VRef2. The
differential pair of transistors Q90 and Q91 compares
L2~3
- 28 -
the constant voltage VRef2 with that o~ the DC amplifier
21. The voltage obtained from a resistor R91 as the
resul-t of comparison of voltayes is used as the color
~iller control voltage. ~t the time of the recording
mode, this color killer signal is cut off in the mi~er
16, which mixes the low frequency converted color signal
at fl = 688 kHz and luminance signal, by operating a
color killer signal switch (not shown) provided in the
mixer 16.
The bias voltacJe VRef2 Eor the DC ampliEier 30 for
providing the color killer control sicJna:L is set to be
:Lower tllan the bias voltac~e VRefl Eor the l)C alllplif-i.er
Eor ampliEying the ACC signal in order to dela~ the ACC
action with respect to the color killer action so that
the color image reproduction can be instantly switched
over to the monochrome one without causing color flicker
to appear on the reproduction.
It is to be emphasized that the ACC signal obtained
from the signal sampling gate circuit 18 according to
the invention ean be utilized as the color killer
control signal by prOCessinCJ through the DC amplifiers
21 and 30 in the above construction. Also, the ACC
action can be delayed with respect to the color killer
action. Fur-ther/ a common bias circuit can be used for
the DC amplifier 30 with respect to the color killer
control signal and that 21 with respect to the ACC
signal, while permitting the delay of the ACC action.
