Note: Descriptions are shown in the official language in which they were submitted.
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BACKGROUND OF THE INVENT~ON
The present invention rela-tes to the collection and reporting of time
related data; and, more particularly, to a me-thod and self-containecl
system for collecting, storing, processing and reporting la~or time and
related costs for use in time management.
In order to manage a business so that it can be run in a profitable
manner, knowledge of labor cost, in terms of time spent by an employee
on a job, is essential. In the past, various devices for collecting such
information have been employed. For example, the popular time clock has
been utilized since the turn of the century. Basically, the function of the
time clock is to print the instantaneous time on a card as the card is
pushed into the clock. The time clock merely reports the instantaneous
moments in time when it is actuated and does not have -the ability to
compute elapsed time. Furthermore, the time clock does not provide any
correlation between an employee, the activity being performed by the
employee and the job or client with which the activity is associated. The
clock also does not provide any cost data in relation to any of these
three factors of interest. In addition, the infs)rmation recorded by a time
clock is not in a suitable form for subsequent automa-tic computations.
In response to these drawbacks of the standard time clock, other
methods of time or cost accounting have been developed. One of these
me-thods utilizes a time card on which the beginning and ending times for
a particular job are entered. While some of these methods employ time
clocks to imprin-t this informa-tion, the data is generally entered by hand.
Hand-written codes are subject to misinterpretation. Furthermore, the
hand or machine calculations necessary to compute elapsed time on a job,
from information on the card, are time consuming and subjec-t -to inac~
curacies. These calculations are seldom completed in time to be available
to provide sufficient information for management -to most effectively
analyze and utilize the data.
With the adven-t of computers, the information recorded on a time
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card can be fed into a main frame computer for processing and
subsequent analysis. Hcwever, in order to feed the information into the
computer, it must first pass through the hands of a key punch operator
who normally is not familiar with the substance of the data and can
easily rnisin-terpret handwriting. The key punch operator has no ~lay of
verifying or correcting any data on the time card. In addition, the
transfer of information frorn the time card to a computer readable format
seldom takes place soon enough for the employee to remember what trans-
pired and thereby correct any errors. As a result, timekeeping systems
employing the time card method are not successfully utilized.
More recently, semiautomated types of data collection systems for
entering data regarding employee activities or operations and the job or
c] ient to which they relate have become available . One such device
employs a ten-channel strip chart recorder in which the duration of
various activities are recorded on the chart. This device allows a user to
define different activities for each of ten function keys and provides a
time recording for each activity. In opera-tion, at least one key is always
depressed, which results in every activity being recorded. The device is
awkward to use and does not summari~e the time spent on each activity.
This information has to be obtained by manually counting the number of
recorded divisions on a strip chart for each activity and then summing
them .
Another type of data collection system utilizes a number of data
input stations located at strategic points around a work area. The input
stations are capable of reading information on employee badges and input
punch cards which are used to report daily attendance, production setup ~
operation, and down time for machine problems and material shortages.
This system is highly expensive and requires a large computer for
support .
In addition to the previously noted drawbacks, these da-ta collections
systems suffer from other disadvantages. They do not provide immedia-te
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feedback ot` entered information for verification by the employee. In
addition, little or no supervisory data i5 available in an on--line,
real-time basis. The data provided by these systems is seldom available
until hours or days after the information is collected because the system
us dependent on a main frame computer which is often unavailable ~/hen
the need for processing the da-ta arises.
OBJECTS OF THE PRESENT INVENTION
It is therefore a general object of the present invention to provide a
novel timekeeping method in which useful time related data is collected,
10 processed and reported for subsequent analysis.
It is a further object of the present invention to provide a novel
self-contained timekeeping system for performing these functions, and
thereby elimina-te the need for peripheral support equipment.
I t is another ob ject of the present invention to provide a novel
timekeeping method and system in which activity related data is
immediately displayed for verification of its correctness by an employee
before it is stored.
It is yet another object of the present invention to provide a
simultaneous printout of the data as it is entered into the system for use
20 by a supervisor in verifying and analyzing employee activity.
It is yet a further object of the present invention -to provide a novel
timekeeping system which can furnish instantaneous and summarized
repor-ts regarding employee activity as well as summarized reports on
labor cost, machine cost, material cost and other factors of interest in
the effective management of a business.
BRIEF DESCRIPTION OF TIIE DRAWINGS
These, as well as other objects and advantages of the present
invention, will become appar ent upon a perusal of ~he following
description of the preferred embodiment of the invention, -taken with the
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accompanying drawings in which:
Figure 1 is a perspective/block diagram illustra-ting the basic
components of a timekeeping system constructed in accordance with the
present invention;
Figure lA illustrates one example of the manner in which data can
appear on the display of the data entry terminal;
Figures 2 is a block diagram illustrating in general the various
circuits and data routes within the central processing unit as well as
their connections to external equipment;
Figure 3 is a block circuit diagram illustrating in detail the circuit
connections of the microprocessor unit and the EPROM memory units;
Figure 4 is a block circuit diagram illustrating in detail the RAM
memory units and their input/output buffers;
Figure 5 is a circuit diagram, in partial block and partial
schematic form, of a data entry terminal including a keyboard entry
unit;
Figure 6 is a partial schematic and partial block diagram of a card
reader which can be substituted for the keyboard entry unit of the data
entry terminal;
Figure 6A is a schematic circuit diagram of the card reader logic
circuit;
Figure 7 is a partial block and partial schematic circuit diagram of
a serial input/outpu t device for transferring information between the data
entry terminal and the microprocessor unit;
Figure 8 is a partial block and partial schematic diagram of a
circuit for controlling a cassette recorder;
Figure 9 is a schematic- diagram of the input/output interface
adapter circuit;
Figure 10 is a circuit diagram oî the clock for controlling the
30 storage of time related information in the central processing unit;
Figure 11 is a partial block and partial schematic circuit diagram of
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the baud rate generator circuit;
Figure 12 is a block circuit diagram of the printer control circuit;
Figure 13 is a schematic circuit diagram of the power failure
detection circuit;
Figure 14 is a block circuit diagram of the calculator circuit;
Figure 15 is a partial block and partial schematic circuit diagram of
a printer logic circuit;
Figure 15A is a schematic circuit diagram of a solenoid driver
circuit; and
Figure 16 is a schematic circuit diagram of the peripheral interface
circuit for enabling the central processing unit to be operatively
connected to another unit of the same type, or a computer, for example.
DETAILED DESCRIPTION
... . _ . . ..
In order to elucidate the various features and advantages of the
presen-t invention, the same is described hereinafter with reference to the
preferred embodiment thereof illustrated in the accompanying drawings. It
will be appreciated, however, that the following description is intended
to be illustrative and not limitative.
The general operation of the timekeeping method of the present
20 invention can best be understood with reference to the basic components
of a system constructed in accordance with the invention such as that
illustrated in Figure 1. The timekeeping system collects source data in
the form of a binary coded decimal employee number, an activity number
and a job or clien-t number. This data is entered into a microprocessor
based central processing unit 100 by means of a data entry -terminal 102.
The data entry terminal 102 can be a numeric keyboard, a card reader
for reading cards having the source data encoded as punched holes, or
some other form of suitable device for encoding data as electrical
signals. By way of example, the data entry terminal 102 can transmit the
30 source data to the central processing unit 100 in an asynchronous serial
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format containing one start bit, eight data bits and two stop bits. A
plurality of data entry terminals can be located at strategic points
through the employees ' work area. For example, in a manufacturing
plant, a data entry terminal can be located at each machine on which an
ac-tivity to be recorded is performed. It will be apprecia-ted that the num-
ber of da ta entry terminals in the system will be limited by the
input/output capability of the central processing unit 100.
In operation, the employee en ters the source data into the da-ta entry
terminal 102. The data is immediately displayed on the -terminal for
10 immediate verification, and correction if necessary, by the employee as it
is being entered. When all of the data is correctly entered into the data
entry terminal and verified as correct by the employee, an ENTER button
is depressed on the entry terminal to transmit the information to the
central processing unit 100. One example of the manner in which the
source data can be displayed on the data entry terminal is illustrated in
Figure lA. It can be seen that the source data comprises a two-digit
employee number, a two~digit ac tivity number, and a four-digit job or
client number. This information remains on the display only while it is
being entered by the employee and is erased as soon as the ENTER button
20 is actuated. During those times tha-t source data does not appear on the
display, the eight digit places of the display can be used to indicate the
month, day and time ( in hours and minu-tes ), as illustrated in Figure lA .
When the employee actuates the ENTER button to feed the source data
into the central processing unit 100, a "begin time" is attached to the
data and the transaction is stored in an active memory area of the
central processing unit labeled l'Transaction Memory". When the employee
begins another job or activi-ty, the elapsed time for the previous
transaction is au-tomatically computed by a calculator within the central
processing unit 100 and stored chronologically in an historical memory
3 0 sec tion of the CPU ~ labeled the "Main Memory" sec tion . The new
transaction is then stored in the transaction memory, and the new begin
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time is attached thereto.
As each transaction is entered into the central processing unit, it is
also fed to a hard copy printer 10~ to provide an "audit trail" record of
the transaction. The hard copy printout of the data provides a means to
prevent loss of the data, for example, if -the memory units within the
central processing unit 100 should somehow be erased. In addition, the
hard copy printout provides a supervisor wi-th an instantaneous record of
each employee ' s activity. By way of example, each time an employee
terminates one activity and begins a new one, the printer 104 can print
10 one row of informa-tion containing the employee number, the activity
number of the previous activity, the job or client number for the previous
activity, the beginning time for the previous activity, the ending time for
the previous activity (i.e., the beginning -time for the new activity), the
elapsed time for the previous activity, the activity number for the new
activity, and the job or client number for the new activity. With such
information, a supervisor is constantly kept up-to-date on the activity
sta tus of each employee .
The timekeeping system continues to collect and store tran action
data in this manner. The accumulated data can be automatically or
20 manually blocked into a number of different periods in the main memory.
For example, one block of data can include all the transactions taking
place in a 24-hour period. Sufficient memory capacity will enable an
entire month worth of data -to be collected and stored in the main memory.
At any selected time, various types of reports can be generated from
the stored data. For example, active transaction status reports, grouped
by employee, activity c,r job/client can be printed. The status of
individuals can be displayed instantly on any terminal. Likewise,
detailed historical reports sorted by employee, activity or job/client, or
summary reports showing only totals in these categories can be
30 generated. Any of these reports may be for a selected single period, a
range of periods or all the periods stored within the main memory. They
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may contain only time related data or they may contain cost information
as well.
Cost tables can be generated to store employee salary ra-tes, activity
bonus factors, and machine rates. A percentage overhead rate may also
be stored and be used to allocate overhead costs to each job on a
percentage basis. In addition to these tables, material costs can be
entered and stored in the system by job number. With these tables,
complete job cost reports can be generated using the historical data in
the main memory. As discussed previously, these reports can be sorted by
l O employee, activity or job . The cost tables, the material cost data, and
the memory data can be recorded either automatically or manually onto a
cassette tape 106 for permanent storage. In addition, the data stored in
the main memory can be transferred onto a cassette tape at the end of a
preselected group of periods, for example, at the end of each month. This
stored data provides a system backup in case of system failure or power
outage and can be loaded back into the system, usually at a time when
the system is not being used to collect real-time data, for additional
analysis, corrections, data additions, estimations for future jobs, etc.
Additional tables can be created and used to provide the ability to
20 select a particular time during the day when an automatic period change
will -take place, eOg., midnight. In addition, the central processing unit
can be programmed to provide a signal to an external relay at
predetermined times during the day to perform such functions as
activating a plant horn, for example. Likewise, the central processing
unit 100 can be programmed to automatically generate predetermined
reports at a period change time or over any selected range of periods at
a time when the system is least active,
If desired, the central processing unit 100 of the timekeeping system
can be optionally connected to a computer 108 to enable data reports to
3 0 be generated in connection with other similar timekeeping systems, for
example . Simi larly, the timekeeping system can be connected to another
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similar timekeeping system to thereby expand the capabilities of the
system .
Referring now to Figure 2, -the major circuits comprising the central
processing unit 100 along with their connnections to equipment external to
the CPU, are illustrated . The cen tral processing unit 100 includes a
suitable conventional microprocessor 110 which is capable of performing
the functions previously described. For example, the microprocessor 110
can be a Motorola 6800 or 6809 chip. An erasable programmable read only
memory (EPROM) 112 is connected to the microprocessor data bus and
10 includes all the programming necessary to enable the microprocessor to
carry out the above-described functions. A random access memory (RAM)
114 is also connected to the microprocessor data bus and provides the
memory capacity for the main memory and transaction memory portions of
the central processing uni-t. A serial input/output device 116 provides an
interface between the microprocessor 110 and the data en-try -terminals
lQ2. As discussed previously, the data entry -terminal may be keyboard or
card reader type devices which are directly connected to the serial
input/output device, In addition, source data may be entered into the
central processing unit by a remote terminal such as a printer terminal
118 or a handheld recorder, for example, which can be connected to the
serial input/ou-tput device 116 by means of a telephone line and a remote
entry buffer 120. The remote data entry terminal 118 enables the
activities of an employee not normally located within a confined work
area, such as a salesman, for example, to be recorded.
A cassette control circuit 122 is also directly connected to the data
bus of the microprocessor 110 and provides an interface for the transfer
of data between the microprocessor and a cassette recording unit 106.
In a ddition to the previously described circui-ts which are directly
connected to the data bus of the microprocessor 110, a number of other
30 circuits for performing diverse functions can be tied to the microprocessor
by means of an inpu-t/output in-terface adapter 124. The adap~er 124 is
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connected to the data bus for the microprocessor 110 and provides a
parallel connection of a plurality of input/output bus slots to the
microprocessor data bus, thereby enabling a plurali-ty of ~ifferent
circuits to receive control signals from the microprocessor. Among the
various circuits which can be connected to the microprocessor 110 by the
interface adapter 124 are printer control circuits 126, a clock circuit, a
power failure detection circuit, and a baud rate genera-tor 128, a
hardwired calculator 130, a plant control (timer circuit) 132, and a
peripheral interface circuit 134, for example.
The printer control circuits 126 control one or more printers 104
which provide the hard copy printouts of the audit trail and summary
reports. The clock circuit and baud rate generator 128 provide signals
for internal use by the microprocessor and its related circuitry, and the
power failure detection circuit monitors the incoming power signal to the
central processing unit 100 and ac tuates an alarm 136 if the power falls
below a predetermined level. In addition, the power failure detection
circuit can operate to inhibit further operation of the central processing
unit until the power is restored to the proper level. The calculator 130
provides the computations necessary to generate the data relating to
20 elapsed time and cost. The plant control circuit 132 can actuate various
relays 138 to perform predetermined functions at preselected -times. The
peripheral interface circuit 134 enables the central processing unit to be
tied to a computer, the central processing unit of another time-keeping
system, a CRT terminal etc.
Referring now to Figure 3, a more detailed illustration of the circuit
connection between the microprocessor 110 and the EPROM memory unit 112
is given. As noted previously, the microprocessor can be a Motorola G800
or 6809 chip. The chip includes eight data input/output terminals D0-D7,
sixteen address terminals A0-A1~, as well as a plurality of other
30 terminals for receiving and sending control signals, some of which are
illustrated in Figure 3. I-t will be apparent to those of ordinary skill in
3~
the art that other suitable microprocessors can be u-tilized in the context
of the present invention as well. The transmission of data to and from the
microprocessor 110 along the data lines D0-D7 is controlled by a
read/write control circuit 140. As illustrated, each channel of the control
circuit 140 includes a pair of conversely connected buffers respectively
responsive to complementary signals so that data can flow in only one
direction on the data lines at any one time.
Associated with the microprocessor 110 is a low power control latch
141. The latch is responsive to a low power interrupt signal LP I which
l O indicates that the power being supplied to the timekeeping system is
below a predetermined level. In response to such a signal, the latch
produces a reset signal which interrupts the operation of the micropro-
cessor 110. This signal is also supplied to a number of other circuits in
the central processing unit 100 as an inhibit signal for the duration of
the period during which the power signal is low. When the power is
restored, the LPI signal is terminated, and after a delay introduced by
an RC circuit comprising a resistor 142 and a capacitor 144, the reset
signal is terminated and the microprocessor 110 begins to function again.
The delay introduced by the RC circuit 142, 144 can be approximately one
2~ half second, for example, to provide time which will allow the memory
unit to stabilize before the microprocessor begins its operation.
The various data, address and control signals provided by the
microprocessor to the remaining circuitry within the central processing
unit 100, and vice versa~ are labeled on the left hand portion of Figure
3. The same labels appear in the Figures illustrating the remaining
portion of the central processing unit 100 to facilitate an understanding
of the interconnection of the various circuits comprising the preferred
embodiment of the timekeeping system. In this preferred embodiment, all
of the circuitry illustrated in Figure 3 is located on a single printed
30 circuit board having connectors corresponding to those illustrated in the
Figure. This board is preferably connected to a motherboard (not shown)
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to which all of the other various modules incorporating the other circuits
of the system can be connected. The motherboard provides all address,
data, control and power signals in common to all of the circuit boards
connected thereto. The motherboard prefera bly also contains a back-up
power supply for retaining the data stored in the memory units in the
event of a primary power failure.
In addition to the previously cLescribed circuit components, Figure 3
also illustrates various additional circuitry for providing suitable
buffering for all of the address, data, and control signals which are
10 transmitted to and from the microprocessor control board.
A detailed illustration of one embodiment of a RAM memory circut 114
suitable for use in the context of the present invention is illustrated in
Figure 4. The memory itself is comprised of a number of individual
storage elements interconnected to provide the necessary storage capacity.
One example of a commercially available chip which can be used to
provide such storage is the TMS-4046 Static Ram Chip manufactured by
Texas Instruments.
The memory circuit illustrated in Figure 4 has the capability of
storing 16K bytes of information. By suitable configuration, three
20 additional similar circuits can be interconnected with a memory circuit
such as that illustrated in Figure 4 to provide the capability of storing
up to 64K bytes of information. Any 16K area of address space within the
64K range is individually addressable by means of an address register
146. As illustrated in Figure 4, one output terminal of the address
register is connected to an address line 148 by means of a jumper 150, to
enable the first 16K area of address space to be accessed. In a similar
manner, a jumper cable would be connected to one of the output terminals
of the address register 146 of the other memory circuits to provide
respective accessing of the other 16K areas of address space within the
3 total memory unit .
The memory circuit also includes buffer circuits 152 for suitably
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conditioning the address signals A0-All which are utilized to access
individual storage spaces within each memory unit of the RAM memory,
and a read/write control circuit 154 for enabling data to be entered into
and read from -the memory unit.
In an embodiment of the presen-t invention having the ability to store
64K bytes of information, a 40K area of address space can be allocated to
the RAM memory unit, with most of the remaining memory space being
reserved for the EPROM memory and a small portion being utilii ed for
input/output address space. In the RAM memory unit, a lK area of
l 0 storage space can be allocated to each of the transaction memory and the
memory for storing various tables, buffers, temporary data and flags,
with the remaining portion of the RAM memory being utilized for the main
memory portion.
Referring to Figure 5, one embodiment of a data entry terminal
suitable for use in the present invention will be described. Source data,
including an employee number, an activity number and a job/client
number, is entered into the system by means of a keyboard 156. The
keyboard contains 16 key switches S0-S15 which are manually operated by
the employee to provide signals to a hexidecimal encoder 158. The
20 hexidecimal encoder transforms the signals from the key switches into a
four bit binary signal which is provided -to a universal asychronous
receiver-transmitter (U/ART) 160. In addition, the decoder 158 triggers a
one shot multivibrator 162. The U/ART 160 provides parallel to serial con-
version of the signal from the encoder 158 and, in response to a signal
from the multivibrator 162, transmits the data from the keyboard to the
microprocessor 110 over an optically isolated transmit line 164.
The U/ART 160 also receives data from the microprocessor 110 in a
serially encoded form over an isolated receive line 165 and converts this
information to a parallel format . The information from the microprocessor 9
30 which has been converted by the U/ART 160, is provided to a series of
hexidecimal-to-7-segment decorders 166, after suitable buffering. The
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decoders 166 control a plurality of single digit seven segment display
units 168. As discussed previously, the display units 168 are preferably
normally ac-tivated by the microprocessor 110 to disp:Lay the month, day,
and time in hours and minutes. However, when the keyboard is actuated
by an employee to enter source data, the display of the date and time is
interrupted and the information being entered by the employee is
indicated in the display unit for verification.
In the embodiment illustrated in Figure 5, the display unit includes
eight single-digi-t displays 168 for indicating a two-digit employee
number, a two-digit activity number and a four-digit job/client number.
It will be apparent, however, -that other display configurations can be
used. For example, a three-digit employee number, a three-digit activity
number and a six-digit job/client number could be utilized, if desirable.
An alternative embodiment of a device for entering source data into
the data entry terminal, comprising a card reader which can be
substituted for the keyboard, is illustrated in Figure 6. The card reader
includes a card reader logic circuit 170 illustrated in detail in Figure
6A. The logic circuit has a plurality of light emitting diodes 172 and
corresponding photo transistors 174 for reading encoded information in the
form of holes that are punched into cards inser-ted into a reader. The
card reader logic also includes a series of control transistors 176 for
sequentially sampling the data on a card by selectively actuating a
group of light emitting diodes at a time and presenting this data to the
U/ART 160 in the terminal. In the embodiment illustrated in Figure 6,
eight groups of four diodes are sequentially actuated to provide the
information relating to the source data. The actuation of the sampling
transistors 176 is controlled by means of a sequencing circuit including
an oscillator 178, a counter 180 and a register 182 for providing the
necessary control signals to the transistors.
In addition to the light emitting diodes 172 and photo transistors 174
for reading the punched holes i.n a data card, the card reader logic 170
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3~3B
also includes an additional light emitting diode and photo transistor 184
and a microswitch 186 for detecting when a card or cards are inserted
into the card reader and correctly positioned. These sensing elements
provide a pair of card detection output signals CD which are fed to a
logic circuit for initiating the operation of the light emitting diode
sequencing circuit. In addition, the carddetecting signals CD trigger a
one shot multivibrator 188 which provides a strobe pulse each time a data
character is presented to the U/ART 160 of the data entry terminal.
The serial input/ou tput device for transmitted data signals between
l 0 a plurality of data entry terminals 102 and the microprocessor 110, is
illustrated in schematic form in Figure 7. The embodiment illustrated in
Figure 7 includes eight serial input/output channels to thereby connect
eight different data entry terminals to the microprocessor. Each channel
includes three leads comprising an input lead 164 for receiving data
transmit-ted by a data entry terminal, an output lead 165 for transmitting
data to the data entry terminal, and a common lead for connection to the
common lead of the data entry terminal. Information received from the
data entry terminal over the input line 164 is converted from serial to
parallel format in a uniquely addressable U/ART 190. Af-ter suitable
buffering, -the information is transmitted to the microprocessor over the
data lines D0-D7.
In a similar manner, data from the microprocessor to be displayed
on the display unit of the data entry terminal is presented to the U/ART
corresponding to the terminal on which the information is to be
communicated. The U/ART converts the parallel encoded information from
the microprocessor to a series format and transmits the information to the
data entry terminal over an output line 1~5.
Referring now to Figure 8, a detailed schematic circuit diagram of a
circuit for controlling a cassette recorder 106 is illus-trated. The circuit
includes a suitable read/write control circuit 192 and a U/ART 194 for
respectively con-trolling -the feeding of information -to and from the
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microprocessor and for converting the information between serial and
parallel formats. Serial data to be written on a cassette tape is sent from
the l~/ART 194 to an encoder 196 which encodes the digital da-ta in to a
phase-encoded format that can be written onto the tape. In a similar
manner, serial data read from the cassette tape is converted from the
phase encoded format into digital data in a decorder 198 and then
converted into a parallel format in the IJ/ART for presentation to the
microprocessor 110.
In addition to the circuitry for reading and writing information on
10 the cassette, the cassette control circuit also enables the microprocessor
unit to address a status register in the cassette recorder to determine the
status of the cassette, such as cassette rewound, write protect, or
cassette present. Likewise, suitable circuitry for enabling the micropro-
cessor to send command signals, such as forward/rewind, read/write,
go/stop, to a command register is located on the cassette control circuit
board .
An input/output interface adapter suitble for connecting a plurality
of different types of circuits to the data bus for the microprocessor 110 is
illustrated in Figure 9. Along the left hand and bottom edges of the
20 figure is illustrated the pin connections for connecting the adapter to the
microprocessor data bus, by means of the motherboard, to receive the
control, address and data signals from the microprocessor and the
previously described circuits directly connected to the microprocessor
data bus. The flow of data signals along the data lines D0-D7 is con-
trolled by means of a read/write circuit 198.
All of the signals are suitably buffered and routed to a plurality of
parallel connected multiple pin busses into which individual modules can
be plugged. One of these multiple pin busses 200 is illustra-ted in Figure
9. Each bus is separately addressable by the microprocessor 110 through
30 an address register 202. In response to a received address input signal,
the address register 202 provides an OlltpUt signal which enables a
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~923~B
selected bus 200 to transmit signals between the module connected thereto
and the microprocessor data bus, to thereby allow the microprocessor to
be custom configured to any external input/output requirements.
The numbers il]ustrated in Figure 9 with respect to the individual
terminals of the bus 200 are utilized in the same manner with respect to
the connec tors illustrated in Figures 10-16 to thereby further facilitate an
understanding of the interconnection of the various circuits.
Referring to Figure 10, a free running timer that is used to generate
a high priority interrupt signal NMI to the microprocessor 110 once per
l 0 minute is illustrated. The timer includes a suitable crystal controlled
oscillator 204 providing a stable frequency output signal. This signal is
suitably divided in a counter or frequency divider 206 to produce a pulse
every 60 seconds. This pulse is suitably buffered and presented to the
microprocessor by means of the input/output interface adapter circuit 124
to momentarily interrupt the operation of the microprocessor and cause the
information relating to the time of day and date, which is stored in the
memory registers of the central processing unit I to be updated.
A baud rate generator for supplying a plurality of different clock
signals to the interface adapter circuit 124, for use by the modules
20 connected thereto, is illustrated in Figure 11. The baud rate generator
also includes a crystal controlled oscillator 208 for producing a
stable-frequency output signal. This output signal is suitably divided in
a counter or frequency divider 210 having multiple output terminals.
Clock signals at different frequencies appear at the respective output
terminals of the counter 210, and are suitably buffered to provide
appropriate baud signals which enable the information presented to and
from the various circuits within the central processing unit to be entered
and read at the most efficient rates. In the preferred embodiment of the
invention, five baud rates of 150, 300, 600, 1200 and 2400 are produced
3 by the baud rate generator .
Referring now to Figure 12, a printer control circui-t for suitably
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buffering and sending parallel data from the microprocessor to a printer
is illustrated. The printer control circuit includes a peripheral
interchange adapter (PIA) 212 which contains buffers for suitably
conditioning the data signals to be presented to the printer, One example
of a sui-table peripheral interchange adapter which can be used in the
context of the present invention is the Motorola 6820 PIA. In addition to
providing data bits, the peripheral interchange adapter 212 also sends a
data strobe signal to the printer to indicate the time at which a row of
informa tion is to be printed . In addition, the peripheral interchange
l 0 adapter receives a ready/busy status signal from the printer and is
responsive to this signal to control the supply of information to be
printed .
Furthermore, the peripheral interchange adapter can include suitable
logic for providing a relay closure in response to predetermined signals
from the microprocessor. This relay closure can be used to control events,
such as activating a plant horn at predetermined times for example. The
relay can be connected to the peripheral interchange adapter 212 by
means of a suitable op-tical isolation circuit 214.
The reference numbers appearing on the input terminals of the
20 printer control circuit illustrated in Figure 12 and the output terminals
of the clock circuit of Figure 10 and the baud rate generator of Figure 11
illustrate one manner in which these three independent circuits can be
incorporated on a single module board to thereby provide economies in the
amount of space required for the various circuits and the number of
boards to be utilized.
Referring to Figure 13, one embodiment of a power failure detection
circuit is illustrated. The circuit includes an inductive pickup 216
having a bridge rectifier 213 and a filter 220 for providing a DC output
signal related to the level of the signal of an AC powerline (not shown).
30 This output signal is compared to a reference signal in a threshold
comparator 222. Whenever the detected value of -the power signal falls
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below the threshold level set by the reference signal, the threshold
comparator 222 produces an output signal which is suitably buffered and
presented to the low power control latch circuit 141. As discussed previ-
ously, the low power control latch circuit produces a reset signal which
interrupts the operation of the circuits in the central processing unit,
including the microprocessor for the duration of the time in which the AC
power signal is below the threshold level. Once the signal is restored to
the proper level, the threshold comparator 222 terminates the low power
interrupt signal LPI to thereby enable the control latch to allow the
10 operation of the central processing unit to resume .
A suitable hardware calculator circuit which can be utilized to
perform computations relating to the raw data entered into the
timekeeping system is illustrated in Figure 14. The calculator circuit can
included suitable calculator chip 224. One example of a commercially
available calculator chip which is suitable for use in the contex-t of the
present invention is the MM57109 manufactured by National Semiconductor.
Data from the microprocessor 110 in the form of operands and commands,
is presented to -the calculator chip 224 by means of a peripheral interface
adapter 226. The peripheral interface adapter 226 also returns the results
20 Of the calculations performed by the chip 224 to the microprocessor 110.
The necessary clock signals for the chip can be supplied by means of an
RC timer circuit 228.
A logic circuit for controlling a printer in response to the output
signals of the printer control circuit 126 is illustrated in Figure 15. The
printer logic circuit receives encoded data in parallel format from the
printer control circuit and sequentially loads this data into a first
in/first out ( FIFO) buffer 230. Upon the detection of an appropriate
command signal, such as a carriage return signal or a signal indicating
that the last character in a row has been printed, the data in the FIFO
30 buffer 230 is seguentially sent to a decoder 232. The decoder generates
signals for controlling a series of solenoid drivers 234 which cause the
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23~3
print head to print the desired characters. One example o~ a suitable
solenoid driver circuit for actuating a solenoid 236 is illustrated in
Figure 15A. At the end of a print cycle, -the printer logic circuit is
enabled to accept additional data from the microprocessor.
One example of a peripheral interface circuit 134 which can be used
to interconnect the central processor unit with a sirnilar such unit or with
a computer for the generation of comprehensive data reports is illustrated
in Figure 16. The primary component of the interface circuit is a
universal asynchronous receiver transmitter 238. As discussed previously,
10 the U/ART provides parallel-to-serial and serial-to-parallel conversion of
transmitted data. In the interface circuit, the data appearing on the
data lines D0-D7 in parallel form from the microprocessor 110 is converted
into a serial format for transmission to the peripheral equipment on an
output line 240. Serial data from the peripheral equipment arriving on an
input line 242 is converted into parallel format for transmission to the
microprocessor along the data lines D0-D7. The U/ART 238 is also capable
of receiving Clear to Send (CTS) and Data Terminal Ready (DTR) signals
for enabling the control of data transmission to be provided by the
external device connected to the central processing unit 100. In addition
20 to another central processing unit or a computer, the peripheral interface
circuit also enables the tirnekeeping system to be connected to a cathode
ray tube monitor device or a modem device.
From the foregoing description of its preferred embodiment, it will be
appreciated that the present invention provides a selfcontained device for
collecting and reporting data and does not reguire any additional suppor-t
equipment. In addition to the functions of collecting and reporting data,
the system provides immediate feedback to an employee for verification of
source data as it is entered, and simultaneous printout of the information
to prevent loss of data and to provide an audit trail format for
3 verification by a supervisor. The microprocessor control base for the
timekeeping system can be programmed to present both active and
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3~1~
historical data in a variety of usable formats. In addition, through the
use of tables providing inforrnation relating to cost fac-tors such as
employee salaries, bonus rates, machine rates, overhead, etc., total time
and cost related information can be provided as well as merely time
rela-ted data. The ability to store the tables as well as collected data on
cassette tape provides a high degree of versatility to the system.
The present invention may be embodied in specific forms other than
that previously disclosed without parting from the spirit or essential
characteristics thereof. The presen-tly disclosed embodiment is therefore
10 considered in all respects as illustrative and not restrictive. The scope
of the invention is indicated by the appended claims ra-ther than the
foregoing description, and all changes which come within the meaning
and range of equivalency of the claims are therefore intended to be
embraced therein.
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