Note: Descriptions are shown in the official language in which they were submitted.
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VERTICAL IGFET WITH INTERNAL GATE
AND METHOD FOR MAKING SAME
The present invention relates to insulated gate
field effect transis-tors (IGFETs). More par-ticularly, it
relates to vertical IGFETs which are substantially planar
in structure and which are used in power switching
applications.
Background of the Invention
Vertical IGFETs are so named because they
incorporate source and drain electrodes on opposite
surfaces o~ a semiconductor wafer. When a preZetermined
voltage is applied to a gate electrode, a vertical current
flow between the source and drain electrodes is
established. The gate electrode is typically insulated
from the semiconductor surface by a silicon dioxide layer,
such IGFETs being referred to as metal-oxide-semiconductor
~MOS) FETs. Conventionally, the insulated gate electrode
is disposed on the same semiconductor surface as the
source electrode, as disclosed in U.S. ~atent 4,145,700,
POWER FIELD EFFECT TRANSISTORS, issued March 20~ 1979, to
C. G. Jambotkar, or it is disposed in a groove in a major
semiconductor surface, as disclosed in U.S. Patent
4,145,703, HIGH POWER MOS DEVICE AND FABRICATION MET~OD
THEREFO~, issued March 20, 1979, to R. A. Blanchard e-t al.
Vertical IGFETs wherein the gate electrode is
disposed on a major semiconductor surface are referred to
as planar, vertical IGFETs herein, and are commonly
referred to in the semiconductor industry as VDMOS
(vertical, double-diffused MOS) devices. Grooved,
vertical IGFETs are commonly referred to in the
semiconductor industry as VMOS devices. Being insulated
gate structures, both VMOS and VDMOS devices are typically
operated in the enhancement mode, and, being vertical
devices, they are commonly used in power switching
applications. When the predetermined voltage is applied
to the gate electrode, a channel is formed in the
semiconductor area immediately beneath the oxide of the
insulated gate and provides a path for current flow
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between the source and drain electrodes. Thus, in a VDMOS
device, the channel is formed at a major semiconductor
surface, and in a VMOS device the channel is formed along
the surface of the groove in the major semiconductor
surface. In both cases, the gate electrode is externally
disposed on the semiconductor wafer and therefore
necessarily consumes a certain amount of surface area.
Summary of the Inven-tion
A novel vertical IGFET and method for
fabrication are disclosed herein. A silicon wafer with
first and second opposing major surfaces has a source
electrode on the first surface and a drain electrode on
the second surface. The gate elec-trode is internally
disposed in the silicon wafer, and includes a finger
portion which is surrounded by an insulating layer such as
silicon dioxide. A predetermined voltage applied to the
gate electrode finger portion will regulate current flow
between the source and drain electrodes.
Brief Description of the Drawing
FIGURE l is a cross-sectional view of a
depletion-type vertical IGFET incorporating the present
nventlon .
FIGURE 2 is a cross-sectional view of an
enhancement-type vertical IGFET incorporating the present
invention.
FIGURES 3 through 6 illustrate the basic
processing sequence used to fa~ricate a vertical IGFET of
the present invention.
FIGURE 7 illustrates an exemplary configuration
of the gate electrode in devices of the present invention.
It illustrates the view taken through cross-sectional line
7-7 of FIGURES l and 2.
Detailed Description of the Preferred Em~odimen-t
Illustrated in FIGURE l is an exemplary
vertical, depletion-type IGFET device 10 incorporating the
present invention. The device 10 comprises a
substantially planar monocrystalline silicon wafer 12
having first and second opposing major surfaces 14 and 16,
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respectively. A source electrode 18 is disposed on the
first surface 14, an a drain electrode 20 is disposed on
the second surface 16. Portions of the wafer 12 adjacent
to the major surfaces 14 and 16 are doped with N or P type
conductivity modifiers so as to provide source and drain
regions 22 and 24 in ohmic con-tact with -the source and
drain electrodes 18 and 20, respectively. With the
exception of the insula-ted gate electrode, which will be
described subse~uently, the bulk of the silicon wafer 12,
i.e., the volume be-tween the source and drain regions 22
and 24, is of similar conductivity type to the source and
drain regions, but of relatively low conductivity. For
example, as illustrated, both the source and drain regions
22 and 24 might be of N~ type conductivity, having
relatively high carrier concentrations of about 1019 cm 3,
whereas the bulk of the wafer 12 might be of N- type
conductivity, having a carrier concentration of about 1~15
cm
It should be noted that although the FIGURE 1
illustration shows the source and drain regions 22 and 24
to be present only near the wafer surface 14 and 16, the
structure is not so limited. In that the regions 22 and
24 serve to reduce source-to-drain resistance, it may be
desirable, for example, to have these regions extend more
deeply into the wafer. Such an example will be shown
subsequently, in a description of enhancement-type device
40 of FIGURE 2.
In the preferred embodiment shown in FIGURE 1, a
plurality of insulated gate fingers 26 are disposed along
a plane which is internal to the wafer 12 and which is
substan-tially parallel to the major surfaces 1~ and 16.
It should be noted, however, that a functional device
could also be formed utilizing a single gate finger 26.
In the preferred embodiment, the fingers 26 are arranged
in a ladder-shaped pattern, as further illustrated in
FIGURE 7, although it should be recognized that the
finger like configuration is not limited to this pattern.
Each finger 26 incorporates a gate electrode 28 of, for
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example, relatively heavily doped polycrystalline silicon,
and is surrounded by an insulating layer 30 of, for
example, silicon dioxide. External electrical connection
to the insulated gate fingers 26 is made by a gate
electrode contact 32 in direct ohmic contact with a
portion of the gate electrode 28.
The design spacing between opposing fingers is
determined by the si~e of the depletion region which each
finger will generate in the semiconductor region 29
therebetween when the gate electrode 28 is appropriately
biased. Thus, in the depletion-type device 10, wherein it
is desirable to pinch off a "normally on" source-to~drain
current, the maximum spacing between opposing insulated
gate fingers 26 should be approximately twice the distance
that the depletion region of each finger 26 extends into
the semiconductor region 29 between fingers.
Illustrated in FIGURE 2 is a vertical,
enhancement-type IGFET device 40 incorporating -the present
invention. The basic structure of the enhancement-type
device 40 is similar to that of the depletion-type device
10. The device 40 also incorporates a silicon wafer 42,
having first and second opposing major surfaces 44 and 46
respectively, with source and drain electrodes 48 and 50
respectively, disposed thereon. Source and drain regions
52 and 54, of first conductivity type, extend into the
wafer from the firs-t and second surfaces 44 and 46, and a
plurality of insulated gate fingers 56 are disposed along
an internal plane of the wafer which is substantially
parallel to the major surfaces. The source and drain
regions 52 and 54 ex-tend to the plane on which the
insulated gate fingers lie so as to define the body region
62 of second conductivity type, between each pair of
ne.ighboring fingers 56. In the preferred embodiment, the
source and drain regions 52 and 54 are of relatively high
conductivity compared to the body regions. Additionally,
the conductivity of the source and drain regions 52 and 54
might be graded, e.g., higher at the wafer surface(s) than
near the body regions 62.
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Each insulated gate finger 56 again includes a
gate electrode 58 of, for example, relatively heavily
doped polycrystalline silicon, and is surrounded by an
insulating layer 60 of, for example, silicon dioxide. An
external gate elec-trode contact 64 ohmically contacts the
gate electrode 58.
A variety of configura-tions for the gate fingers
56 is also possible with the enhancement-type device,
although in the preferred enbodiment, a laddex-shaped
structure, as illustrated in FIGURE 7, is used. It should
be noted, however, that in an enhancement-type device
there are fewer restrictions on the configuration for the
gate fin~ers 56. Since an enhancement-type device is
normally off, there is no necessity for each gate finger
56 to be in pro~imity to a structure such as an opposing
finger 56, against which source-to-drain current is
pinched off. Operationally, the IGFET device 40 behaves
as a typical enhancemen-t-type device. The device 40 is
normally off, and current flow between the source and
drain electrodes 48 and 50 is regulated by a voltage
applied to the insulated ga-te fingers 56. When a
predetermined voltage is applied to the gate electrodes 58
via gate electrode contact 64, a conductive channel region
is created in each body region 62 in an area adjacent to
the gate oxide 60.
The basic processing steps for fabricating -the
devices 10 or 40 of FIGURES l and 2 are shown in FIGURES 3
through 6. As shown in FIGURE 3, the starting point for
processing is a monocrystalline silicon substrate 70
having opposing major surfaces 72 and 74. Depending upon
whether a depletion-type device or an enhancement-type
device is being fabricated, the substrate 70 will be doped
with an appropriate concentration of a particular
conductivity modifier. A relatively heavy dopant
concentration may be desirable so as to decrease power
dissipation in the completed device. On the other hand, a
relativley low concentration may be desirable for ease of
device fabrication.
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A first silicon dioxide layer 76 is formed
across the subs-trate surface 74. A first oxide layer 76
might have a thickness of approximately lO00 Angstroms and
it can be formed, for example, by thermal oxidation. A
polycrystalline silicon layer 78 is then formed across the
first oxide layer 76. The thickness of the
polycrystalline silicon layer 78 will ul-timately determine
gate length and it might have a value in the approximat~
range of 5000-20,000 Angstroms. ~s is illustrated, the
polycrystalline silicon layer 78 is relatively heavily
doped -to a particular conductivity type. This doping can
be performed either during the polycrystalline s1licon
deposition or following the deposition by conventional
doping or ion implantation procedures.
The doped polycrystalline silicon layer 78 is
next photolithographically defined so as to form a
pattern, comprising a plurality of fingers 80, and each of
the fingers 80 is oxidized so as to form a surrounding
second silicon dioxide layer 82, as illustrated in FIGURE
4. The first silicon dioxide layer 76 is then removed
from areas of the substrate surface 74 between the
oxidized fingers 80, as illustrated in FIGURE 5. This may
be accomplished photolithographically, for example, by
first protectin~ the oxidized fingers 80 with photoresist
and then etching the first silicon dioxide layer 76.
As shown in FIGURE 6, an epitaxial silicon layer
84 is next grown from the exposed surface 74 such that it
fills the space between the oxidized fingers 80 and forms
a layer 84 of monocrystalline material over all of the
oxidized fingers 80. The surface of this epitaxial layer
84 is identified at 86 in FIGURE 6, and it will ultimately
form the first wafer surface 14 or 44 illustrated in
FIGURES l or 2, respectively. The epi-taxial layer 84 can
be formed by what is now referred to as the epitaxial
lateral overgrowth (ELO) technique.
Basically, the ELO process involves a
repetitious, two-phase, depositing/etch cycle whereby
monocrystalline silicon is grown from a monocrystalline
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silicon surface which is exposed within the apertures of
an overlying silicon dioxide mask. When the silicon which
is being epitaxially deposited grows through the apertures
to a thickness greater than that of the mask, the
epitaxial growth proceeds laterally, across the surface of
the mask, as well as vertlcally. Ul-timately, a continuous
monocrystalline silicon layer overlying the aper-tured mask
is formed.
The depositing/etching cycle can be performed
within a conventional reactor at atmospheric or reduced
pressure. During the depositing phase of the cycle, the
substrate is exposed to a gas mixture which comprises a
silicon-source gas such as SiH2Cl2 and a carrier gas such
as hydrogen. Additionally, it may be desirable to include
a silicon-etching gas such as HCl during the depositing
phase. During the etching phase of the cycle, the
substrate is exposed to a gas mixture comprising an
etching gas such as HCl and a carrier gas such as
hydrogen.
During the depositing phase, silicon deposits
from the silicon-source gas onto exposed surfaces of the
substrate and mask. The silicon that deposits onto the
surface of the monocrystalline substrate follows the
monocrystalline lattice structure at that site, whereas
the silicon which precipitates onto the mask deposits in
the form of isolated, non-single-crystalline aggregates.
The gas composition and duration of the etching phase is
designed so as to completely remove all of the
non-single-crystalline aggregates which were formed on the
mask following the depositing phase. Although this
etching also removes some of the monocrystalline silicon
growing from the exposed area of the monocrystalline
substrate, the etch rate of this monocrystalline silicon
is relatively low compared to the etch rate of the
non-single-crystalline aggregates. Thus, after a single
depositing/etching cycle, more silicon is deposited on
exposed silicon surfaces during the depositing phase than
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is etched during the etching phase, and all of the
deposited material is monocrystalline in nature.
The monocrystalline silicon deposited by the ELO
process can also be simultaneously doped as it is ~eing
deposited. For e~ample, in the deple-tion-type device 10,
arsenic or some other N -type conduc-tivity modifer can be
introduced during the depositing phase of the
depositing/etching cycle. Additionally, when this is
done, the dopant concentration can optionally be varied
during the deposition so as to yield a conductivity
gradient in the deposited layer. When fabricating the
enhancement-type device 40, a P type dopant such as boron
can be introduced during the initial phase of the
depositing cycle so as to form the P type body regions 6~.
The P type dopant can then be replaced with an N type
dopant after the epitaxial deposit has achieved a
thickness approximately equal to that of the oxidized
fingers 80. Thus, the depth of the N+ source region 22 in
the depletion-type device 10, and the depth of the N-
~
source region 52 in the enhancement-type device 40 can be
readily varied during the ELO deposition process.
Alternatively, high-conductivity source regions 22 and 52
can be fabricated by a process such as ion implanation
after the ELO layer is formed. Such an ion implanation
might also be used to form high-conductivity drain regions
24 and 54.
In the case of both the depletion-type device 10
and the enhancement-type device 40, a contact opening
through the epitaxial layer 84 can be made next so as to
expose an area of heavily doped polycrystalline silicon 28
or 58 where the external gate electrode contact will be
formed. External source, gate and drain electrode
contacts 18, 32 and 20, or 48, 64 and 50 can then be
formed in a conventional manner, such as evaporation,
using a conventional electrode ma-terial, such as aluminum.
In addition to being a novel structure, devices
of the present invention provide several advantages over
`` conventional VDMOS and ~MOS devices. The source electrode
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contacts 18 and 48 are substantially planar structures.
In addition to providing greater contact area to the
corresponding source regions 22 and 52, there planar ohmic
contacts are rela-tively easy to fabricate. The large
contact area between the source electrode contac-t and the
source region also lowers the contact resistance at that
interface.
The fabrication process for making the devices
10 and 40 is also relatively simple. Conventional VDMOS
and VMOS devices re~uire single or multiple ion
implantations so as to define source and body regions.
These implantations are not re~uired in devices of the
present invention. There is only a single critical
photolithographic step in the fabrication sequence for
devices of the present invention, i.e., the patterning of
the gate electrode. In contrast, conventional devices
require several critical photolithographic steps for
fabricating both internal semiconductor regions and
external electrode contacts. Furthermore, the need for an
insulating layer between conventional multilevel source
and gate electrode contacts on the semiconductor surface
is eliminated by the source and gate electrode contact
configuration described herein. Lastly, the structure and
fabrication process described herein provide a readily
manufacturable depletion device. The fabrication of
conventional depletion-type devices requires etching deep
grooves into the semiconductor and deep diffusions for
doping the sides of these grooves. The present invention
eliminates the need for deep etchings and diffusions, as
well as the need for depositing electrode material on the
walls of the semiconductor grooves.
