Note: Descriptions are shown in the official language in which they were submitted.
333t~ 9D-RG-13421
POWER CIRCUIT FOR INDUCTION COOKING
Background of the Inven-tion
This invention relates generally to induction
heating arrangements and, more particularly, to po~ler
circuits for induction cooking appliances. Induction
eooking is attractive for domestic use because the use
of induction heating to heat a cooking utensil is a
theoretically efficient process. Heat is generated
only in the metallic utensil where it is wanted.
The ordinary ~as range and electric range, by eo~parison,
have greater losses due to poor coupling of heat to
the utensil and heating the surrounding atmosphere.
However, the frequency of power supplies available
in the home, generally on the order o~ 50 to 60 Hz, is
too low to effectively drive an induction heating coil.
For eooking appliances, ultrasonlc frequencies on the
order oE 20 KHz provide much more satisfactory results.
Inverter circuits commonly employed in
induction cooking appliances to convert the 60 ~
line voltage to the high-frequency signal for driving
the induction coil use filtered LC resonant circuits
to provide the desired ultrasonic frequency signal.
Examples of such inverter circuits may be found in
U.S. Patent 3,781,503 issued December 25, 1973 to
Harnden, Jr. et al and U.S. Patent 4,074,101, issued
February l~, 1978 to Kiuchi et al. In the LC resonant
circuits used in such resonant circuit inverters, the
effective inductance becomes quite large due to the
induction heating coil of the power circuit. Because
of this large inductance a large capacitance is
required. In addition to -the capacitance required for
the resonant circuit, a smoothing capacitor is ~
~ 9D-RG-13~1
required to filter the rectified line vol-taye. This
capacitor also is necessarily large. The large
capacitors required for such circuits are expensive
to the extent that the cost of the capacitors becomes
the dominant cost of the power circuit.
Alternatives to resonant circuit inverters
include inverter circuits of the push-pull type which
typically include a transformer having a center tap
winding with the ends of the primary windings
connected to switching devices driven in push~pull.
Such push-pull arrangements conventionally employ a
feedback circuit 4~ including a feedback -transformer
to sense load current and control the frequency of the
switching device in accordance with sensed load current.
Examples of such inverter circuits are disclosed in
U.S. Patent 3,383,582 issued May 14, 1968 to John D.
Bishop et al and U.S. Patent 3,973,165 issued August
10, 1976 to Thomas Eugene E;ester. The feedbac]c
transformer and other circuit elements employed in
such feedback circuitry are prohibitively expensive,
making such circuits relatively unattractive for
cookiny appliance applications.
In view of the shortcomings of the prior art
it is appa~ent that there is a need for a power circuit
for an induction cooking appliance which eliminates
the costly capacitance assoicated with the resonant
circuit inverters and which elimina-tes the costly
transformer feedback arrangemen-ts associated with
push-pull inverters o~ the prior art.
It is therefore an object of the present
invention to provide an induction heating arranyemen-t
in which an induction heating coil is energized by a
--2--
3~
9D-RG-13~21
pulsating power supply and in which energization of the
coil is controlled by switch means operative -to cause
the direction of current in the induction heating coil
to oscillate at a frequency which is independent of
load current.
It is a further object of the present inven-tion
to provide an induction heating arrangement of the
above mentioned type in which the switch means is
operative to cause the direction of current in the
induction coil to oscillate at a requency which
~aries directly wi-th the amplitude of the power supply.
It is a further object of the present
invention to provide an induction heating arrangement
of the above mentioned type in which the energy
delivered to the coil with each current pulse is
uniform from pulse to pu]se.
It is a further object of the present
invention to provide an induction heating arrangement
of the above mentioned type which eliminates the need
for large costly capcitors and costly transformer
feedback circuitry.
SUMMARY ~F THE INVENTION
In accordance with the present invention, an
induction heating arrangement adapted for energi~ation
by a pulsating power supply of relatively low
frequency is provided.
An induction heating coil is coupled to the
power supply by switch means ~witchable between first
and second conduction modes. In the first conduction
mode, switch means couples the power supply to the coil
so as to cause current from the power supply to flow in
the coil in one direction. In the second conduc-tion
--3--
~33~ 9D-RG-134~1
mode, the switch means couples the power supply to the
coi]. so as to cause current to flow in the coil in the
opposite direction. Control signal generating means
generates a control signal which oscillates between a
first state and a second state at a frequency which
is hi.gh relative to the frequency of the power supply
and which is independent of load current.
In a preferred form of the invention, the
frequency of oscillation o~ the control signal varies
directly with the amplitude of the power supply.
The control signal is coupled to the switch means and
operative to oscillate the switch means between its
first and second conduction modes as the control signal
oscillates between its first and second states,
respectively. By coupling the power supply to the
coil in this manner, the direction of current in the
coil oscillates at a frequency which varies directly
with the instantaneous ampli.tude of the power supply.
The resultant current in the coil. comprises a train
oE alterna-te current pulses of opposite direction.
The magnitude of each pulse varies directly with the
instantaneous amplitude of the power supply and the
duration of each pulse varies inversely with the
amplitude oE the power supply. Consequently, the
energy delivered to the coil by each pulse, which is
proportional to the product of the amplitude and
duration of the pulse, is essentially uniform from
pulse to pulse.
In the illustrative embodiment herein
described, the induction coil is a center tapped coil
which is coupled to the power supply by switch means
comprising a pair of power transistors arranged for
--4--
~33~ 9D~RG-13~21
push-pull operation. A voltage controlled oscillator
generates a control signal haviny a frequency which
varies directly with the instantaneous magnitude of
the power signal. This control signal is converted
b~ logic circuitry into a pair of driviny signals for
driving the transistors in push-pull fashion at a
switching rate corresponding to the frequency of the
control signal. The logic circuitry introduces
momentary time delays between the switching GFF of
one transistor and the switching ON of the other
transistor to permit dissipation of reverse current
in the coil.
The efficiency of the power circuit of the
illustrative embodiment is enhanced by holding both
transistors in concurrent non-conduction modes when
the magnitude of the power signal is less than a
predetermined threshold level such as during the first
30 and last 30 of each power signal cycle.
BRIEF DESCRIPTION OF TEIE DR~WINGS
FIG. 1 is a simpliEied schematic diagram of
a power circuit for an induction coo]cing appliance
illustratively embodying the inductin heating
arrangement of the present invention.
FIG. 2a illus-trates the voltage waveform of
the input power signal for the circuit of FIG. 1.
FIG. 2b illustrates the voltage waveform
of the power signal, Vs, applied to the input tap of
the induction coil of the circuit of FIG. 1
FIGS. 2c-2e illustrate conduction cycle
repitition rates for the power circuit of FIG. 1,
for various operator selected power settings.
FIG~ 3 i~ an enlarged exaggerated illustration
--5--
3~3 9 D- RG- 1 3 ~L 2 1
of one conductive cycle of Vs with the operating modes
of the power transis-tors of FIG. 1 superimposed thereon
to illustrate the manner of operation of the power
circuit of FIG. 1
FIG. 4 is a simplified schematic circuit
diagram illustrating the circuitry of block 40 of
FIG. 1.
FIG. 5 i5 a simplified schematic diagram
illustrating the circuitry of block 42 of FIG. 1.
FIGS. 6a-6h illustrate input, output and
various internal logic signals for the circuit o~
FIG. 5.
FIG. 7 illustrates a typical waveform of
the current in the induction coil of FIG. 1, correlated
in time with the signals illustrated in FIGS. 6a-6h.
FIG. 8 iS a simplified schematic circuit
diagram illustrating that portion of the circuitry
of hlock 44 of FIG. 1 associated with one of the
transistors of FIG. 1.
DETAILED DESCRIPTION OF T~IE INVENTION
The induction heating arrangement of the
present invention is applicable to a variety of
inductive heating applications; however, it will
be described herein with reference to an induction
cooking appllance such as an induction surface unit
fox a range or a portable cooking or food warming
appliance applications for which it is particularly
advantageous. Typica].ly, in such an appliance an
induction heating coil is appropriately mounted in a
horizontal position immediately below a non-metallic
supporting surface commonly referred to as the cooking
surface which may be made of a thin shee-t of glass,
--6~
~ 3~ 9D-RG-13421
"
ceramic or plastic. This cooking surface supports the
cooking utensil to be heated. The cooking utensil, a
cooking pot or pan, is typically made of iron.
Energy for heating the utensil i5 transferred to
the utensil from the coil by driving the induction heating
coil at ultrasonic frequencies to generate a high frequency
alternating magnetic field. The magnetic flux emanating
from the coil inductively couples the utensil. The
utensil may be considered to function as a single-turn
secondary winding with a series resistance load, the
magnitude of khe resistance representing the resistive
part of the eddy current and hysteresis losses in the
utensil. The current and voltage induced in the utensil
can be estimated to a first order of approximation by the
transformer laws.
According to the present invention, the induction
heating coil is adapted for energization by a relatively low
frequency pulsating power supply. Non-resonant push-pull
inverter circuit means are provided to couple the pulsating
power signal from the power supply to the coil. The inverter
circuit means includes switch means arranged in such a
~nn~r that current pulses of opposite direction alternatively
flow in the coil at a pulse repetition rate which is high
relative to the frequency o-E the power signal, preferably
in the ultrasonic range. The current pulse repetition rate
is determined by the switching rate of the switch means.
Means are provided to generate a control signal for switching
the switch means at a rate which is independent of current
flow in the coil.
In a preferred form of the invention, the
control signal generating means generates a control
signal for switching the switch means at a rate which
-- 7
~333~3 gr)_RC;-l3~2l
varies directly with -the magnitude of the power supply.
By -this arrangement, when -the instantaneous voltage of
the power supply is low the switching rate is low,
resulting in a relatively long ON time for the coil in
each direction. Sin~e the power supply voltage is low,
the rate of current buildup in the coil is relatively
slow and the longer ON time allows sufficient current
buildup to deliver the desired amount of energy to the
coil. Similarly, when the instantaneous voltage of the
power signal is high which causes rapid current
buildup in the coil, the switching rate is also high,
resulting in a relatively short ON time for the coil
in each direction to prevent current buildup in excess
of circuit component limits. The energy delivered to
the coil during each current pulse is proportional to
the product of the magnitude and the duration of the
coil aurrent pulse. Varying switching frequency
directly with the magnitude of the power supply varies
the pulse duration inversely with the magnitude of the
current pulse. ~y varyiny the switching frequency in
this way, the product of the magnitude and duration is
essentially constant, resulting in the amount oE energy
delivered to the coil with each current pulse being
relatively uniform from current pulse to current pulse.
In the illustrative embodiment of the present
invention shown in simplified schematic form in FIG.
1, the pulsa-ting power supply 10 is a 60 H~ 120 v AC
power supply such as is -typically available in the
home. The alternating current input signal VI provided
by the power supply illustrated in FIG. 2a is rectified
by a conventional diode bridge 12. The output signal
V from bridge 12 is an unfiltered fully rectified
--8--
~3~3~ g~-RG-13421
pulsating power signal such as shown in ~'IG. 2b. Ho-t
line ]4 connects the active output terminal of hridge
12 to the center tap 18 of induction heating coil 20.
The end terminals 22 and 24 of coil 20 are connected
to the collectors of power transistors 26 and 28,
respectively. Transistors 26 and 28 are arranged to
function as switch means for coupllng power signal
Vs to coil 20. The emitters of transistors 26 and
28 are connected to ground line 16 to switchably
couple terminals 22 and 24 to ground line 16. Normally
reverse biased protective diodes 32 and 34 are arranged
in parallel with transistors 26 and 28, respectively,
to provide a path for transient reverse current in
the coil when the transistors switch out of conduction.
Conventional RC snubber circuits 36 and 38 clamp the
voltage at the collectors of trnaistors 26 and 28
below the breakdown voltage for protection against
inductive spikes.
The switch means comprising transistors
26 and 28 is switchable between a first conductive
mode in which transi.stor 26 is conductive and
transistor 28 is non-conductive; a second conductive
mode in which transistor 26 is non-conduc-tive and
transistor 28 is conductive; and a non-conductive
mode in which both transistors are non-conductive. t
By this arrangement~ when the switch means is in its~
conductive mode, the current flows in one direction
through the coil from center tap 18 to terminal 22.
When the switch means is in its second conductive
mode, current flow through the coil is in the opposite
direction from center tap 18 ~o terminal 24. By
oscillating the switch means between its first and
_g_
9D-RG-13~21
3~
second conductive modes, current pulses of opposite
direction rela-tive to the coil alternately flow in the
coil. When operated in this manner, the frequency a~ which
coil 20 is d:riven is determined by the switching rate o:E
transistors 26 and 28.
~ his switching means rate is controlled by control
signal generating means 40 which monitors the AC signal from
power supply 10 and generates a control signal having a
frequency which varies directly with the magnitude of the
power signal Vs in a manner to be described with reference
to FIG. 3. The control signal from block 40 is split into
two logic signals by logic and timing means 42, one signal
for each transistor. Each logic signal is then amplified by
the pre-amp driving circuit of block 44. The resulting
trigger signals from block ~4 are coupled to the base of
their associated transistors. This arrangement of power
transistors 26 and 28 controls signal generating means 40,
and logic timing means 42 provides non-resonant push-pull
inverter circuit means for controlling energization of heating
coil 20.
In the circuit of FIG. 1, the magnikude o:E the
instantaneous current in the load is determined by the magnitude
of the instantaneous voltage V applied to center tap 18 and the
length of time each of transistors 26 and 28 is conductive. If
the switching frequency of the transistors is too low, current
in the coil can exceed the operating limits of the circuit
components. If the switching rate is too high, current buildup
in the coil will be insufficient to deliver sufficient energy to
the coil to permit adequate heating of the inductive load.
Thus, to use a constant switching frequency in the
circui-t of FIG. 1, the f~e~uency selected must be
high enough to limit current buildup in the coil at
high values of Vs acceptable levels and low enough
9D-RG-13421
3~
to provide the desired heating performance. Depending
on the output heating requirements of the induction
heating arrangement, switching rates high enough to
limit current buildup at high values of Vs may not
permit sufficient current buildup at low values to
deliver sufficient energy to provide adequate heating
of the load.
It was found that operatin~ o-f the coil of
the illustrative embodiment at a constant frequency
of 20 KHz permits too much current buildup in the
circuit when V is near its peak value. Operation at
higher frequencies on the order of 30 KHz satisfactorily
limits current buildup when V is high, but does not
allow sufficient current buildup when V is low to
provide the heating performance desired for cooking.
One approach which would provide sufficient
heating while switchiny at a fixed or constant
frequency and which is technically feasiable though
unattractive from a cost standpoint would be to filter
the output from bridge 12 so that Vs is essentially
a smoothed DC signal. The switching frequency could
then be set high enough to limit the current without
concern over insufficient current buildup during low
portions of V .
The preferred approach for overcoming the
difficulty presented by a constant switching frequency,
in accordance with one aspect of the present invention,
is to vary the driving frequency, i.e., the switching
rate, directly with the magnitude of the power signal
V . In this way, the coil runs at a relatively low
frequency, i.e., a relatively long ON time at low
values of Vs and at high frequency, i.e., a relatively
9~-RG-13431
333~
short ON time, as V nears its peak value. By increasing
the ON or conductive time for each transi~tor for
low V and de~reasing the ON time for high V , the
energy delivered to the coil during each ON time, which
is a function of :the product of the magnitude of the
current pulse and the duration or width of the curren-t
pulse, is essentially uniform from pulse to pulse.
~ s seen in FIG. 2b, the power signal Vs
applied at center tap 18 is fully rectified unfiltered
120 volts RMS pulsating at a frequency of 120 Hz, with
each power signal cycle being of 8.3 millisecond
duration. Coil 20 is driven at a frequency in the
ultrasonic range by alternately switching transistors
26 and 28 ON and OFF on the order of 200 times each
during each 8.3 millisecond power signal cycle. FIG.
3 provides an enlarged out of scale illustration of a
single half cycle of the power signal Vs. The light
portions ~7 represent perlods when transistor 26
is ON and transistor 28 is OE`F; the shaded portions
4~ represent periods when transistor 28 is ON and
transistor 26 is OFF. The cross-hatched regions ~9
represent periods of total non-conduction during whi.ch
both transistors are concurrently non--conductive. The
purpose for these periods will be described further on.
The pulse widths within the conductive portion of the
8.3 millisecond envelope are greatly exaggerated out
of scale to clearly illustrate that as the amplitude
of Vs increases the ON time for both transistors
propotionally decreases. In reality, in the illustrative
embodiment the duration of ON time for each transistor
varies from a minimum of roughtly 15 microseconds for
Vs near its peak to a maximum of roughly 25 microseconds
-12-
~93~3~ 9D-RG-13421
when Vs is at its minimum value within the conductive
portion of the 8.3 millisecond power siynal cycle, i.e.,
at the beginning and at the end of the conductive
portion of the cycle.
The periods of concurrent non-conduction
at the beginning and end of each power signal cycle
enhance the operating efficiency of the circuit. A
significant advantage of the present invention is that
it permits use of an unfiltered powex signal, thereby
eliminating the need for costly filter elements. It
is well known that inverter power circuits operate
at higher efficiencies at high V values such as when
V is held up by a filter capacitor during the low
portions of the line voltage. However, such
capacitors, in addition to being expensive components,
lower the power factor of the circuit. ~3y operating
unfiltered, the power factor for the power circuit is
kept relatively high. The low operating efficiency
at low values of Vs is countered by holding both
transistors in the non-conductive mode concurrently
for a predetermined period at the beginning and at the
end of each cycle of the power signal V to prevent
energization of the coil when the magnitude of the
power signal Vs is too low for effi.cient circuit
operation. As shown in FIG. 2c and FIG. 3 where the
cross-hatched portions represent periods of non-
conduction, in th~ illustrative embodiment a delay
angle on the order of 30 and a conduction angle on the
order of 150 is employed to prevent current flow in
the coil during the first and last 30 of each cycle
when Vs is undesirably low.
Control of output power, that is, control of
-13-
3~3~3C~ 9D-RG-13421
the energy de]ivered to the utensil in accordance wi-th
operator selected power set-tings, is implemented by
counting cycles of the power signal and is in effect
periodically rendering the transistors concurrently
non-conductive for complete cycles of the power signal.
The rate at which the transistors are rendered non-
conductive for complete power cycles, or viewed the
other way around the repetition rate for conductive
cycles is set in accordance with the power setting
selected by the usex. Conductive repetition rates for
various power settings are illustrated in FIGS.
2c-2e where waveforms representing the power signal
V of FIG. 2b are superimposed with cross-hatching to
identify those periods during which no current flows
in coil 20 because both transis-tors 26 and ~8 are in
their non-conductive modes. E'IG. 2c illustrates a
conductive cycle repetition rate of 1/1 in which there
are no fully non-conductive cycles. This corresponds
to a power settincJ of 100%. In FIG. 2d every other
cycle is non-conductive, and in FIG. 2e, 3 of 4 cycles
are non-conductive providing conductive cycle repetition
rates of 1/2 and 1/4, respectively, corresponding to
power settings of 50% and 25%, respectively. The
output of power setting control block 46 is a logic
signal, which is generated for each power signal cycle
to set the repetition rate in accordance with the power
setting selected by the user. The logic signal assumes
a first logic state to initiate conductive cycles and a
second logic state -to initiate non-conduction cycles. An
3C arrangemen-t for generating such signals to control the
output power of a conventional heating element is
disclosed in detai] in United States Patent Number
--1~--
~ ~ , 9D-RG-13421
~33~3~
4,256,951 issued March 17, 1~81. This signal is provided
to block 40 as an input used in generating a control
signal for controlling the switch rate of transistors
26 and 28.
Circuitry employed in block 40 of the
illustrative embodiment of FIG. 1 is shown in schematic
formin FIG. 4~ The circuit of FIG. 4 generates a
square wave control signal, OSC, which performs
essentially three functions: disables current flow in
the coil at the beginning and the end of each cycle of
the power signal V to enhance operating efficiency;
oscillates at a frequency proportional to the magnitude
of signal Vs when the ma~nitude of Vs is above a
predetermined threshold value to set the switching rate
of transistors 26 and 28; and responds to the operator
power level selection signal from block 46 to provide
the conductive cycle repetition rate corresponding to
the selected power setting for the coil.
The circuit of F:[G. 4 is coupled to the 120
volt 60 Hz AC power supply 10 via step down signal
transformer 50 which steps the voltage down from 120
V RMS to 12 V RMS~ Transformer 50 may be of the type
readily commercially available and identifiable by the
designator PC-12-100. The AC output signal from
transformer 50 is rectified by full wave rectifier
52 which can be a readily available ~C chip identified
by the designator VM 48. Rectifier 52 produces a signal
V ' which is in phase with the proportional in magnitude
to power signal Vs. V ~is applied to chopper circuit
54 and oscillator 56.
Chopper circuit 54 sets the delay and
conduction angles for V by preventing the con~rol signal,
-15-
~ 9D-RG-13421
OSC, from switching transistors 26 and 28 into conduction
by holding OSC in a non-oscillating state when the output
signal from bridge 52, V ', is less than a predetermined
threshold value corresponding to V being less than a
predetermined threshold value. It is this threshold
value of Vs ' which ef~eetively set the delay and
conduction angles for V which, as previously described
with reference to FIG. 3, are preferably set at 30
and 150, respectively. V ' is coupled to the positive
input of a voltage comparator 56 which may be an IC
chip readily commercially available and identifiable
by the designator LM 311. Voltage comparator 56 has
its negative input tied to a voltage biasing network
which includes resistor 58 in series with zener diode
60 and which is fed by a DC logic voltage source of
-~10 volts DC. In this circuit, the value of the zener
voltage, Vz, is the predetermined threshold voltage
which sets the delay and conduction angle for Vs.
Selection of zener vo].tage at Vz=3.3 volts sets the delay
and eonduetion anyles at approximately the desired
30 and 150 , respeetively. The output signal from
eomparator 54 is applied as one input of the TTL AND
eircuit 62 where it functions as an enable signal.
When Vs ' is in a portion of its eycle in
whieh its magnitude is less than 3.3 volts, corres-
ponding to both Vs ' and Vs being in that portion of the
cycle between 0 and 30 or between 150 and 180 the
output of eomparator 56 in a logical zero, thereby
holding OSC, the output of AND eircuit 62, in a
non-oscillating low state and preventing the triggering
of transistors 26 and 28 during such periods. When
Vs ' is greater -than 3.3 volts corresponding to Vs being
-16-
~33~ 9D-RG-13~21
in the portion of its c~cle between 30 and 150 , the
output of comparator 56 is high permit-ting the output
signal of AND circuit 62, OSC, to swing in accordance
with the other gate inputs.
The signal which determlnes the switching
rate of the transistors during the conductive portions
of the power cycle is provided by oscillator circuit
64 which generates an output signal having a frequency
which is directly and linearl-y proportional to V
and, consequently, to V . This function is performed
in circuit 64 by a voltage controlled osciallator 66
which may be an integrated circuit available commercially
as an eight pin dual inline package numbered 566
(SN566, LM566, etc., depending upon the manufacturer).
Normally, when using the 566 IC as a voltage controlled
oscillator, a fixed bias is applied to pin 6 and the
modulating input is applied to pin 5. However, in such
a configuration, the usable voltage range for pin 5
is limited to the range of 75%-lO0~ of the supply vol-tage.
To avoid this limitation on the swing of the modulating
voltage which in FIG. 4 is Vs '~ which swings for 0
volts to approximately 16.8 volts, pin 5 i9 used as
the fixed bias point and pin 6 as the modulating point.
Pin 5 is biased to a DC voltage by resistors
68 and 70 fed by DC voltage source of -~lO volts, and
held at that voltage. Pin 6 is tied to a DC bias point
by connection of resistor 72 between pin 8 and pin 6
with DC bias voltaye of +10 volts applied to pin 8.
Pin 6 is also tied to the positive output of rectifier
52 via resistor 74 which function as a modulating
current source sending a current of variable magnitude
to pin 6. The magnitude of the current supplied to
~33~ gD-RG-l3~21
pin 6 ~rom this current source varies dixectly with
V '. Diode 75 connected in series with resistor 74
blocks current from the 10 Volt DC source through
resistor 74 when Vs ' is low. Capacitor 77 connected
between pin 5 and pin 6 functions as a high frequeIIcy
bypass filter.
Timing capacitor 76 is connected from pin 7
to ground. The frequency of the oscillator output
signal at pin 3 i5 determined by the rate at which
capaci.tor 76 is charged. Whe Vs ' is zero, there is
no modulating current from the current source to pin
6. The frequency oE the output signal under this
condition is determined solely by the timing resistor
72 and capacitor 76. When V ' is not zero, additional
charging current is delivered to pin 6 proportional to
the value of Vs ' As this current increases, the
charging time for CapaCitGr 76 decreases proportionally,
causing the frequency of the output signal to increase
proportionally. As this current decreases, the
charging time increases and the frequency decreases.
For resistor 72 at 3.3 K ohms and capacitor 76 at .006
uF, the constant unmodulated frequency, i.e. the
output frequency for Vs ' equal to zero volts~ is
approximately lO KHz. For Vs ' equal to its peak value
of approximately 16.8 volts, the output frequency is
roughly 30 KHz. Thus, the frequency of the output
signal from pin 3 varies from 10 KHz to 30 K~Iz as Vs
varies from zero to its peak value. At the start of
the conductive portion of the 8.3 millisecond envelope
the value of the modulated frequency from pin 3 has
~,r,~ already increased --~e 10 KHz, so the OSC -frequency
~ e~ r~ ~ rl ~
varies-~rcm 20 K~z t~ 3Q KHz across the conductive
-18-
, ~ ,, 9D-RG-13~21
por-tion of Vs.
The PNP-NPN CiXCllit comprising txansistors
78 a.nd 80, biasing resistors 82, 84, 86, 88 and gO,
and diode 92 re-biases the square wave output from
pin 3 of oscillator ~-~ to TTL voltage levels. The
collector voltage of transistor 80 which oscillates
at the frequency of the output signal at pin 3 is
applied as an input -to AND circuit 62. During the
conductive portions of each power cycle r the control
signal OSC oscillates at the frequency of the signal
at pin 3.
The remaining input to AN~ circuit 62 is
derived from power contxol means 46. Block 46 responds
to the operator power setting by generating high signal
for conductive power signal cycles and a low signal
during power signal cycles which ~re to be non-conductive,
in order to control the power output of coil 20 in
accordance with the power setting selected by the
operator. Thus, when bloclc 46 dictates a non-conductive
power signal cycie, OSC, the output of AND circu.it
62 is held in a low non-osci:Llating state which holds
transistors 26 and 28 in their non-conductive modes.
The parameters for the components of the
circuit of FIG. 4 are listed in TABLE I.
-
-
-
,
-lg
~ 33~ 9D-RG-13421
TAsLE I
Resistor 56 5 K Res.istor 8~ 5 K
Resistor 68 1 5 K Resistor 90 5 K
Resistor 70 10 K Capacitor 76 .01 uF
Resistor 72 3.3 K Capacitor 77 .001 uF
Resistor 74 3.9 K Zener Diode 55 3.3 volts
Resistor 82 5 g Transistor 78 2N2907
Resistor 84 10 ~ Transistor 80 2N2222
Resistor 86 10 K
As an alternative to the control signal
generating means 40 (FIG. 1) illustratively embodied
in the circuit of FIG. 4, logic circuitry or a micro-
processor could be used to generate the control signal
OSC. In one such arrangement, a pulse generator is
adapted to generate timing pulses at a constant
repetition rate which i.s high relative to the desired
frequency range for the control signal, and a digital
counter to count the timing pulses. A zero crossing
detector respon~ive to the pulsating power supply
generates a count initi.ating pulse with each zero
crossing of the power supply which resets the counter.
Since the power signal V is not ~iltered, and is in
phase with the power supply, and the count is referenced
to the zero crossing the supply, the amplitude of Vs
which is a rectified replica of the power supply is
predictable at each count. By appropriate logic
circuitry or microprocessor programming, each transition
of the control signal between its first and second
states can be programmed to occur at a predetermined
count. Thus, the desired periods of concurrent non-
conduction, as well as the desired relationship
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between current pulse duration or ON time and the
amplitude of the supply, are provided by programming
each transition oE the control signal OSC to occur at
the appropriate count.
The logic and timing control circuitry
represented as block 42 in FI~. 1 will now be described.
~s described with reference to FIG. 1, transistors 26
and 28 are alternately conductive. However, it is
necessary after turning OFF either power transistor
to momentarily hold both transistors OFF to allow the
reverse current in the coil to be dissipated. The
logic and timing network responds to the control
signal OSC from oscillating means 40 (FIG. 1) to
generate a pair of timing signals with appropriate
time delays for switching the power transistors ON
and OFF at a switching rate corresponding to the oscill-
ating fre~uency of OSC. The logic circuit of block 42
for the il~ustrative embodiment oE E'IG. 1 is illustrated
schematically in FIG. 5.
The square-wave control signal, OSC,
(FIG. 6a) from block 40 is applied to input terminal
102~ Inverter 104 inverts OSC, e~fectively splitting
OSC into two signals, the original signal OSC and OSC
(FIG. 6c) which appears at the Outpllt of inverter 104.
Appropriate time delays are introduced by one-shot
multi~ibrators 106 and 108. Multivibrators- 106 and
108 may be so-called 555 ICs readily available
commercially in an eight-pin dual inline package
(designated differently, depending upon the
manu~acturer; for example, SN 72555, LM 555, etc.).
In the circuit of FIG. 5, multivibrators 106 and 108
are each connected in a standard one-shot multivibrator
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~3330 9D-RG-13421
configuration, wi-th pins 4 and 8 tied to a fixed high DC
bias voltage. Timing for the multivibrator 106 is provided
by the external RC combination of resistor 110 connec-ted to
commonly connected pins 6 and 7 and driven by the DC bias
voltage, and capacitor 112 connected between pin 5 and
ground. Timing for mllltivibrator 108 is provided by similarly
connected resistor 114 and capacitor 116. Pin 1 of each
multivibrator is tied directly to ground. Pin 5 is bypassed
to ground by capacitor 118 for multivibrator 106 and
capacitor 120 for timer 108 to prevent pickup of stray
signals.
The undisturbed state Eor multivibrators 106 and
108 is pin 3 low~ When the input to pin 2 goes low, the
output at pin 3 goes high and remains high for a period T,
the duration of which is determined by the external RC
combination in accordance with the relationship T = .693 RC.
As the time T expires, the output at pin 3 returns to its
undisturbed low state. The output at p.in 3 is inverted by
inverters 122 and 124 for multivibrators 106 and 108,
respectively, and applied as inputs to AND circuits 126 and
128, respectively. Each transition of OSC initiates a
trigger signal for one of power transistors 26 and 28
(FIG. 1).
To provide the desired concurrent non-conductive
periods for transistors 26 and 28 between switching one
OFF and the other ON, a time delay is introduced at the
beginning of each half cycle of OSC. This is accomplished
in one half cycle by logically ANDing the inverted output
of multivibrator 106, OSCD with the output of inverter
104 OSC and in the other half cycle by logically ANDing
the inverted output of multivibrator 108 OSCD with OSC.
Signals OSC and OSC are coupled to AND circuits
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3 9 D- RG~ 1 3 ~ 2 1
12~ and 126, respectlvely, by race delay networks 130
and 132, respectively. Each race delay network
comprises a pair of inverter gates with a capacitor
coupled to ground interposed therebetween. These race
delay networks introduce sligh-t delays to eliminate race
conditions which could otherwise permit both power
transistors to be briefly concurrently ON.
The parameters for the circuit components
of FIG. 5 are listed in TABLE II.
TABLE II
Resistor 110 l K Capacitor 120 .01 uF
Resistor 114 l K Capacitor 130 .01 uF
Capacitor 1]2 .05 uF Capacitor 130a .l uF
Capacitor 116 .05 uF Capacitor 132a .1 uF
Capacitor 118 .01 uF
For the circuit parameters listed above, the
period or pulse width of the delay pulse at pin 3 of
each multivibrator is on the order of 1-2 microseconds.
Referring now to E'IGS 6a-6h, to demonstrate
circuit operation for the circuit of FIG. 5, control
signal OSC (FIG. 6a) from the oscillator control circuit
of FIG. 4 is a square-wave oscillating between logical
high and low states. As OSC goes low, OSCD (FIG. 6b)
goes high providing a logical high pulse of limited
duration. This high pulse is inverted by inverter 122
and the resultant signal ~SF~ (FIG. 6e) is ANDed with
OSC to provide the logic signal PVBl (FIG- 5g) which
controls the triggering of transistor 26 (FIG. l).
~g~ goes high as OSC goes low; however, the low state
of ~5~ prevents PVBl from immediately going high.
Thus, PV~l is delayed from ~g~ for the 1-2 microseconds
~3~ 9D-RG-13421
duration of the low OSCD pulse. At the end of the low
pulse, OSCD goes high, permitting PVBl to go high whlch
triggers transistor 26 into its conduction mode. When
OSC goes high, OSC and consequently PVBl goes low,
switching transistor 26 into its OFF or non-conductive
mode. As OSC goes low, OSCD, (FIG. 6d), the output
of multivibrator 108 generates a high pulse of 1-2
microseconds duration. This pulse is inverted by
inverter 124 whose output OSCD (FIG. 6f~ is ANDed with
OSC by AND circuit 128. The low s-tate of OSCD holds
P~B2 low for the duration of the pulse, thereby
introducing a delay of 1-2 microseconds before PVB2
follows OSC high to trigger transistor 28 into conduction.
A comparison of PVBl and PVB2 (FIGS- 6g and 6h,
respectively) shows the 1-2 microseconds delay at the
beginning of each positive going pulse during which
both PVBl and PVB2 are low holding both transistors
26 and 2~ in thier non-conductive modes.
Race delay circui-ts 130 and 132 insure that
transitions in OSC and OSC do not arrive at AND circuits
126 and 128, respectively, ahead of the pulses from
multivibrators 106 and 108, respectively, thereby
avoiding race conditions which might otherwise allow
both transistors 126 to be conducting concurrently, a
condition which should be avoided.
FIG. 7 illustrates the alternate current
pulses of opposite direction flowing in the coil, with
current flow -from coil terminal 18 to terminal 22 as
viewed in FIG. 1 being defined as pGsitive and current
flowing from terminal 18 to terminal 24 being defined
as negative for representation purposes in this figure.
A comparison of FIG. 7 with FIGS. 6G and 6H
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3~
9D-RG-13421
shows the changes of direction of current in the coil in
response ~o the control signa], OSC, which is provided by
the circuit of FIG. 4 and divided into a pair of trigger
signals PVB1 and PVB2 by the circuit of FIG. 5. The
current pulses 134 depicted as positive in FIG. 7
result when transistor 26 is switched into its eonduction
mode in response to eontrol signal OSC assuming its low
state, i.e., switehing from high to low. The pulses
136 depicted as negative oceur when transistor 28 is
switched into conduction in response to control signal
OSC assuming its high state, i.e., switching from low
to high. The decaying portions of the pulses designated
138 represent the reverse current flowing in the coil
during the momentary time delay between the switching
OFF of one transistor and the switehing ON the other.
It is to be understood that the pulse
widths shown in FIGS. 6a-6h and FIG. 7 represent only
a segment of the current pulse train assoeiated with
eaeh 8.3 milliseeond eyele of the power signal V . The
variation in pulse width between pulses shown is
impereeptible. ~lowever, it is to be understood that
the pulse width and magnitude of the pulses represented
in these FIGURES vary fxom roughly 25 microseeonds to 15
mieroseeonds as the instantaneous voltage Vs varies from
the threshold value of 168 volts during eaeh 8.3
milliseeond cycle o-E signal Vs. As previously
deseribed, this variation in pulse widths is illustrated
in exaggerated fashion in FIG. 3.
FIG. 8 sehematieally illustrates the amplifier
cireuitry of bloek 44 (FIG. 1) for transistor 26.
The trigger signal for transistor 26, PVB1 from the
circult of FIG. 5 is the input to this circuit. The
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~33~
9D-RG-13421
ou-tput signal VBl is a replica of PVBl amplified to
provide the necessary levels for triggering power
transistor 26. This pre-amp circuit is designed to
provide active ON and active OFF during signals. ~he
ON signal is generated by amplifier circuit 142 which
is a standard commercially available IC package
(designated S-2580) comprising 8 identical amplifier
circuits, only one of the eight amplifiers being shown.
While use of one of the available amplifier circuits
as shown performs satisfactorily, for greater
reliability and component longevity, it may be
desirable to connect two or more of these amplifiers in
parallel to reduce the power load on the individual
amplifiers. Preferably, Eour of the eight amplifier
clrcuits in the package are tied in parallel for the
pre-amp circuitry for transistor 28 (not shown). PV
is inverted by inverter 144 and amplified by amplifier
142. The output of amplifier 142 is tied to the base
drive of output section 146 via resistor 148.
The OFF signal is generated by amplifier
sections 160 and 162. Amplifier 160 may be a six
amplifier IC chip readily available commercially
(designator UHP-495). As with amplifier 142, a single
one of the sic available amplifier performs satis-
factorily. However, in a preferred form of the
circuit, two of the amplifiers are tied in parallel for
the driving circuit of each of power transistors 26
and 28. Amplifier 162 is an IC chip readily commercially
available (designator ULN 2004). The ULN 2004 chip
provides seven identical amplifier circuits on the chip.
As with amplifiers 160 and 142, an individual one of
the circuits as shown will perform satisfactorily but,
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~333V 9D-~G-13421
in a preferred form, four of the seven amplifiers are
tied in parallel for use in driving transistor 26
and the remaining three are similarly tied in parallel
for use with transistor 2~. r~he output of amplifier
162 is also tied to the base drive of output section 146.
Output section 146 is an NPN-PNP push-pull
circuit with an output signal VBl. When PVBl swings
high, the output of amplifier 142 switches transistor
150 into conduction to provide a base current on the
order of 1.5 amps to transistor 26 (FIG. 1) thereby
rapidly switching transistor 26 into conduction. When
PVBl swings low, the output from amplifier 162 swings
to a negative 5 volts to switch transistor 152 into
conduction so as to rapidly deplete the current from
the base of power transistor 26 to rapidly switch it
out of its conduction mode.
The pre-amp circuitry for driving transistor
28 and its operation i9 identical to that shown and
described in FIG. 8 for transistor 26 and has been
omitted for clarity and brevity.
It is apparent Erom the foregoing description
that an induction heatin~ arrangement is provided by
the present invention which provides the desired ultra-
sonic frequency operation of an induction coil energized
by a 60 Hz power supply which eliminates the need for
large expensive filter capacitors and expensive feedback
circuitry associated with the induction heating
axrangements of the prior art.
While in accordance with the Patent Statutes
a specific embodiment of the present inven-tion has been
illustrated and described herein 9 it is realized that
numerous modifications and changes will occur to those
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~3~
9D-RG-13421
skilled in the art. It is therefore to be understood
that the appended claims are intended to cover all such
modifications and changes as fall within the true spirit
and scope of the invention.
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