Note: Descriptions are shown in the official language in which they were submitted.
COMPUTER PROGRAM PROTECTION METHOD
AND APPARATUS
Inventors: Huba L. Toth and Arpad Paul Toth
BACKGROUND OF ~HE INVENTION
The present invention relates ~o the field of digital
computers and specifically to program pxotection methods
and apparatus forming part of such computers.
Progr~m protection is for ensuring that computer sot-
ware is authorized to be used with a particular computer
~ystem. Before a system will accept a computer program,
it is desirable to have the computer system check,
through program protection methods, to ensure that the
program is authorized. For purposes of this appli-
cation, ~he term ~program pro~ection" is in~ended to
mean the methods and apparatus which function to ensure
that the computer system will accept and utilize only
the properly authorized computer software.
The need for program protection arises for a nu~ber of
reasons. One need for program protection aris~s when a
~omputer system requires software with special features
FORTN2/FPA
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x~
particularly adapted fox the system. If a comput~r
program has not been specially adapted to run on the
computer system, then the running of the computer
software may cause unwanted errors. Program protection
is also desirable to ensure that computer programs have
been properly tested before they axe permitted to run on
the computer system.
Only computer programs which have required features and
which have h~en property tested will be authorized.
Another need for software protection occurs in order to
facilitate the marketing of computer software.
Fxequently, computer programs are marked under license
to run only on a particular hardwaxe system. Under such
circumstances, there is a need to identify whether or
not the computer program is authorized for a particular
computer system. If an attempt is made to load an un-
authorized computer program, the eomputer system should
reject that program.
Another need for program protection arises to dis-
tinguish between different versions of computer
programs. For example, an original program may differ
substantially from new releases of a program containing
updates and improvements. Such ngw releases may require
special hardware features or may require a special fee
before authori~ation is proper.
In addition to the foregoing, those skilled in the field
of computexs will recognize that other reasons exist for
having program protection in data processing systems.
For many computer syste~s, computer progxams are stored
and delivered to users of computer systems on magnetic
FORTN2~FPA
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media. Freq~lently, the magnetic media are flex~discs
since they are small, light-weight and easily trans-
portable. Flex-discs have obtained widespread usage in
the marketing of computer programs. Because magnetic
discs are readily reproducible and are readily modifi-
able, they have presented substantial problems when
program protection has been desired.
Various methods have been proposed for protect-
ing computer software particularly when the software is
stored on magnetic discs. Such protection methods have
not provided adequate flexibility for authorized uses nor
sufficient protection from unauthorized uses~
In accordance with the above background, it is
the objective of the present invention to provide im-
proved program protection methods and apparatus for use
in data processing systems.
SUMMARY OF THE INVENTION
-
The present invention relates to computer pro-
gram protection apparatus in computer systems. The pro-
tection apparatus includes disc sensing means for gen-
erating a program protection signal whenever a magneticdisc is newly engaged for use in the system. Whenever
a disc is newly engaged in the system~ the disc is inter-
rogated to ascertain whether or not the disc is author-
ized for use on the computer system. If the disc is
not authorized, the system will not accept the disc.
If the disc is authorized, the disc is accepted for
normal use.
vtd/ ~
Briefly stated, the present invention is for a
computer system adapted for receiving computer programs
from a disc in a disc d~vice and constitutes a program
protection apparatus comprisiny: detection means for
provi.ding a program protection signal when a disc is
engaged in the disc device tc initiate a determination of
whether the disc is authorized for use in -the system;
authorization means, responsive to the program protection
signal, for interrogating the disc, the authorization
means including: master detector means, responsive to a
master indicator on the disc, for providing a master
signal when the disc is a .-naster; rneans for providing
a virgin identifier code; means for causing disc data
to be read from a predetermined field of the disc in
response to the master signal; comparator means for
comparing the disc data with the virgin identifier code
to provide a virgin signal when the disc data and the virgin
identifier code are the same, the virign signal indicating
that the disc is a virgin because disc data has not been
written over with a unique code; system identifier register
means for storing a system identifier unique to the com-
puter system; and means, responsive to the virgin signal,
for writing the system identifier into the predetermined
field of the disc whereby the disc becomes a non-virgin
master.
In another aspect, the present invention is for
a computer system adapted for receiving computer programs
from master and non-master discs and constitutes a pro-
gram protection apparatus comprising: disc detection means
for providing a program protection signal when a disc has
been newly placed in the system; authorization means, re-
g. vtd/`~ . 4
sponsive to the program protection signal, for interrogating
the disc, the authorization means including, means for
sensing the presence of a master disc indicator on a
timing trac~ of the disc and providing a master signal
when the master disc indicator is de-tected, means for
interrogating a master disc which has been newly placed
in the system to determine whether or not the master disc
is a virgin and generating a virgin signal if the master
disc is a virgin, system identifier register means for
storing a system identifier unique to the computer system;
means for storing a system identifier in a predetermined
field of a virgin master disc, and means for comparing the
contents o the predetermined field on a newly installed
disc to the system identifier and providing an authoriza-
tion signal if there is a match enabling the disc to
be accessed normally by the system.
In accordance with one feature of the invention,
a master aisc detector is provided for determining whether
or not a newly engaged magnetic disc is a master disc.
Master discs are of two types, virgin or non-virgin. A
virgin master disc is one that does not have an author-
ization identifier for any authorized user system. A
virgin master disc can be authorized for use on any
properly authorized system. When a master disc is newly
engaged in the system, it is tested to determine whether
the master is a virgin or non-virgin. IE the master disc
is a virgin, then the system functions to store an author-
ize system identifier on the disc. Once the authorization
system identifier has been stored on the disc, the disc
is no longer a virgin and has become a non-virgin master.
Thereafter, whenever the disc is loaded into the author-
~. ~
- 4a -
vtd/ ~
izing system, the system checks and ascertains that the
disc is authorized to run on the system.
If a disc is not a master, the disc may be an
authorized copy of a master which is authorized to run
on the system. Whenever a disc is newly engaged in the
system and the master detectof determines that the disc
is not a master, the system checks to determine whether
or not the disc is an authorized copy. If the disc
is an authorized copy, the system is enabled to access
the disc for normal reading or writing of information.
Whenever a particular pro~ram is to be accessed
on a disc which is an authorized disc, the program is
checked to see if the program is authorized for use on
the computer system. If the program is authorized, and
the disc is authorized, then the system is permitted to
access the disc and the computer program stored thereon.
In accordance with the above summary, the
present invention achieves the objective of providing
a program
4b
vtd/`~
protection method and apparatus which facilitates a dis-
tribution of authorized computer programs on authorized
discs while preventiny the use of unauthorized programs
and discs.
The foregoing and other objects, features and ~dvantages
of $he invention will be apparent from the following
more particular description of preferred embodiments of
the invention as illustrated in the accompanying
drawings.
Brief ~escription of the Drawin~
Fig. 1 depicts an overall data processing system in
accordance with the presen~ invention.
Fig. 2 depicts a schematic representation of a disc
assembly for engaging and driving a flex-disc to read
and write data in the operation of the Fig. 1 system.
Fig~ 3 depicts a flex-disc, including both a timing
indicator and an authorization indicator for a master
d~sco
Fig. 4 depicts a waveform representative of the output
from a indicator detector for a master diso of the Fig.
3 type operating in the assembly of Fig~ ~.
Fig. S depicts an electrical schematic representation of
a master disc detector utili~ed in the Fig. 1 system.
Fig. S ~epict~ a s~hematic electrical representation of
an a~tb~riz~tion circuit for detecting authorized magne-
tic discs in the Fig. 1 system.
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s
DETAIL~D DESCRIPTION
Overall System - Fi~. l
In Fig. 1, the processing unit 2 connects to a memory
management unit (MMIi) 6 to central logic bus (CLB) 22.
The central logic bus 22 includes address bus 17, data
bus 18 and control lines 19. The processor 2 also
receives a first level interrupt signal, INIT, and a
second level interrupt signal, VIR, from the bus unit
5-0. These interrupt signals are utilized in connection
with the program protection m~chanism.
In Fig. 1, a plurality of bus units 4 and 5-0,. O ., 5-3
connect to the central logic bus 22. Typically, the bus
unit ~ is a random acces~ memory which functions as a
main store memory for the data processing system of
Fig. 1. The bus units 5-0 through 5-3 typically include
inputJoutput devices such as keyboards, flex-discs, and
hard-disc storage devices, paxallel input/output
devices, processing units an~3 other types of units~
In Fig. 1 J the bus uni~ 5-0 includes a flex~disc device
25 and conventional control circuitry for interfacing
the flex disc device 2 with the FigO 1 system.
The flex-disc device ~5 and bus unit 5~0 are employed in
the system for loading computer programs into the
system. The system is designed to accept only those
discs and programs that are authorized or use in the
F:ig4 1 system.
In Fig. 1, a programmable array logic unit B8 is
includecl within the unit 60 The unit 88 receives each
address on address bus 17 and responsively, in
accordance with ~omP predetermined algorithm and/or
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encoding, provides an encoded output on the data bus 18.
The output on bus 18 is a system identifier. The system
identifier is stored in the authorization data field of
a virgin flex-disc to thereaf.er enable the system to
read from the disc.
_ sc Drive Assembly - Fig. 2
In Fig. 2, a schematic representation of the flex-disc
drive assembly whieh forms part of the flex-disc device
25 of Fig. 1 is shown. The flex-disc 26, indicated by
broken line, is contained within a protective jacket 27.
The disc 26 is free to move within the jacket 27. The
jacket 27 ~nd the disc 26 are inserted together in the
direction of arrow 24 into the drive assembly of Fig. 2.
In order to insert the ja~ket 27 and disc 26 into the
assembly o~ Fig. 2, the gate 30 must be raised~ in the
direction of arrow 21, around the pivot 20 in order to
provide clearance for insertion or retraction of the
disc 26 and jacket 27.
The disc assembly of Fig. 2 includes detection
apparatus, in the form of a switch 31, for sensing if a
flex-disc has been newly engaged in the system~ When
gate 30 is raised, the switch 31 provides a program
protection signal PP on line 44. ~he PP signal
indicates that the gate 30 has been opened and,
therefore, an unauthorized disc may have been inserted
into the flex-disc device 25. The program protection
signal initiates an interrogation to determine whether
or not the inserted di~c is authori~ed.
When the yate 30 is raised, the linkage 32 moves and
causes member 39 to be retracted upwardly through opera-
tion of assembly 41. The upward movement o~ membex 39
when the gate 30 i5 open retracts the tip 42 from the
FORTN2/FPA
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center indicator 16 of the disc 26. The tip 42 is
rotably engaged to the member 39. When tip 42 is
engaged in the indicator 16, it mates wi-th a drive
member at the end of fhe driveshaft 15 of motordrive 29.
The motordrive 29, through the shaft 15 and the tip 42,
clamps the disc 26 and drives it in a clockwise
direction~ A magnetic read-write head 11 reads and
writes data from and to disc 2S. Head 11 is moved back
and forth by the head drive assembly 28. The head 11 is
positioned over an opening in the jacket 27 and,
therefore, has access directly to the surface of disc
26.
A hole 10 is located in the jacket 27 at some
pr~selected radial position for exposing a timing track
for disc 26. Referring to Fig~ 3, the timing indicator
35 is shown in the timing track at a radial position
which will align with the hole 10 in Fig. 2. The
indicator 35 is conventionally a hole but can be any
other type of indicator.
The jack~t 27 has two parts, one above and one below the
disc 26 in Fig. 2. The hole 10 extends through both the
top and bottom parts of the jacket, so that when the
indicator 35 is aligned with the hole 10, a light beam
radiates all the way through iacket 27 and indicator 35
without being stopped.
In Fig. 2, an optical detector, including a light source
34 and a light detector 33, is positioned in alignmPn~
with the hole 10. The detector 33 operates to sense any
indicator, such as the timing indicator 35, in the disc
26 when the indicator is registered at the optical light
axis 8 of the detector 33. The timing mark 35 will have
a once-per~revolution registration with th~ window 10
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Z5
and axis 8 and will be sensed once-per-revolution by the
indicator detector 33. The timing mark 35 is employed,
in a conventional manner for synchronizing the writing
and reading of d~ta to and from the magnetic disc 260
Since both indicators 35 and 36 do not simultaneously
appear in opening 10, the master disc cannot be readily
detected. Therefore, in onP embodiment, the disc jacket
27 has notches 94 and 95 to indicate that the disc is a
master. The ~ ~s 94 is the standard notch for
indicating a read-only disc.
Master Disc - Fig. 3
In accordance with the present system, and referring to
Fig. 3 J a second indicator 36 is located in the timing
track at the same radial distance as the indicator 35.
Indicator 36 in the example shown is a hole. However,
any type of indicator can be ~mployed. Accordingly,
when the disc 26 of Fig. 3 is lo~ded into the drive
assembly of Fig 2, both indicators 35 and 36 will
register once-per-revolution with the opening 10 and
axis 8.
The indicator detector 3:3 senses the presence of the
indicators 35 and 36 and responsively provides an output
signal pulse for each indicator once-per-revolution.
Referring to Fig. 3, the angular displacement, D, of the
indicator 36 relative ~o the indicator 35 determ~nes the
time displacemsnt between the signal detected for
indicator 35 and the signal detected for indicator 36 by
detector 33. The displacement ~D" is selected to be a
predetermined value for indicating that diæc 26 is a
master. If the indicator 36 is located at some other
location other than displacement D or is not present at
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1 f~ ~
all, then the disc ~6 will not be recognize~ as a
master,
Detector Output ~ 0 4
In Fig. 4~ a waveform xepresenting the output nf the
detector 33 is shownO The tl, t3, t5 and t7 pulses are
representatlve of the pulses that occur as a result of
the indicator 35 being detected by detector 33. The
pulses t2, t4~ t6, and t8 are representative of the
pulses that occur as a result of the detection of
indicator 36 by ~he detector 33~ The ~iming, t(D),
between the pulses tl and t2 is directly proportional to
the angular spacing D between the indicators 35 and 36.
In ~he example descrihed, the .;.ndicator 36 is located
within one quarter of a revolution, that is, ~D" is less
than 90 degxees.
Master Detector - F g. 5
In Fig. 5, a master detector i~ shown which includes the
optical detector 330 The waveform of Fig. 4 is repre-
sentative of the signal on line 59. Line 59 from
detec~or 33 connects as one input to the NAND gate 51.
The other input to cJate 51 is from the ~ output of a
~lip-10p 50. The output rom gate 51 is the
RESET si~nal which connects to the reset ~R) input of a
counter 45. Counter 45 is clocked by the Cl.K/X signal
to continually count from its reset count through to its
full count and then is automatically reset ~o continue
counting.
The parallel output from counter 45 connects as one in-
put to a comparator 47. Comparator 47 is connected at
its other input to receive a value rom a register 46.
Comparator ~7 compares the contents of xegis~er 46 with
the count in counter 454 The count in register 46 is
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~ 3
selected to represent the displacement, "D", of the
indlcat~r 36 from the indicato.r 35. ~he signal
resulting from indicator 35 operates to reset counter 45
and ~he clocking of coun~er 45 is such that, for a
master dis-, the count in coun~cer 45 will equal the
count in register 46 when the indicator 36 is detected
by de~ector 33.
Flip-flop 50 is clocked by the CLX signal to store the
output of comparator 47. In order to ensure that a mis-
resistration does not occur between the counts in
register 46 and counter 45, the clockillg signal ~o
counter 45 is divided by 4 in a conventional divide by 4
circuit 53. In this way, it is assured that if compara-
tor 47 provides a logical one ou~put indicating a com
parison between the counts and counter 45 and 46, it
will be stored in the flip-flop 50~
When the comparison is sensed and clocked into the flip-
flop 50, the NAND gate 51 is disabled, and therefore,
any pulse sensed on line 59 from the de~ector 33 will
not reset the counter 4~. If flip-flop 50 has not b~en
clocked to store a logical one on its Q output and a
logical ~ on its Q output, the Q output will be a logi-
cal 1 thus enabling NAND gate 51. When gate 51 is
enabled, any pulse on line 59 resets the counter 45.
The presence of a comparison from comparator 47, stored
in flip-flop 50~ and a pulse on line 59 is detected by
the NAND gate 54 to clock the flip-flop 55. Flip-flop
55 has a logical 1 connected on his D input and stores a
1 on its Q output when clocked~ The 1 stored in flip-
flop 55 i5 transferred to the flip-flop 56 by a ~ransi-
tion on the output of AND gate 49, Gate 49 receives its
inputs from the detector 33 and a decoder 48.
EORTN2/FPA
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f~
Decoder 48 is set to recognize a count in counter 45
which represents one complete revolution of the disc 26.
If counter 45 i5 reset to a 0 count by the pulse 35
operating through NAND gate 51, then decGder 48, if not
reset, will reach a count represented by a full revolu-
~ion of disc 26 to provide a logical 1 tQ AND gate 49.
The simultaneous occurrence of the count from decoder 48
and a pulse on line 59 from detector 33 will clock the
contents of flip-flop 55 to the flip-flop 56 to provide
the ~ASTER signal on line 58 as a logical 1. At the
same time that the MASTER signal is clocked into flip-
flop 5S, flip-flop 55 is reset by the vutput from
gate 49.
Flip-flvp 56 is reset by the output irom gate 57. Gate
57 provides an output if at the time the NAND gate 51
provides a logical 0 output to reset counter 45, gate 49
does not indicate that an vutput rom decoder 48 has
occurred.
The operation for the master detection circuit of Fig~ 5
is as follows for a condition where the disc 26 of Fig.
3 is a master disc. When the pulse tl of Fig. 4,
resulting ~rom indicator 35 of disc 25, causes a signa]
on line 59, the output from flip-flop 5() to gate 51 is a
logical 1. Accordingly, t~.e output from gate 51 is
asserted, as a logical 0, to reset the counter 45.
Counter ~5 thereafter continues to count the clock
pulsesO Register 46 is s~ored ~ith a count representing
the position OI the master ir.dicator 36. When master
indicator 36 is positioned to be de~ected by detector 33
and generates the t2 pulse of Fig. 4 7 comparator 47 is
satisfied to provide a logical l ~o ~he flip-flop 50
causing the Q output of flip-flop 50 to be a logical 0.
T~e logical 0 into NAND gate 51 prevents the t2 pulse on
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line 59 from asserting any output from NAND gate 51, and
therefore, counter 45 is not reset by the operation of
the t2 pulse.
The t2 pulse, howevPr, is input to the NAND gate 54
along with the logical l from flip-flop 50 to assert the
output of gate 54 ~s a logical 0 clocking a l into
flip-flop 55O The I is stored in flip-flop 55 until
coun~er 45 has advanced to the full cycle count detected
by detector 48. The full cycle count from detector 48
together with the t3 pulse, generated by the second
revolution of disc 26 and the alignrnent of indicator 35
with the detector 33, clocks the l from flip-flop 55
into flip flop 56. At this time, the MASTER signal on
line 58 si~nifies that disc 26 is a master. Flip-flop
56 is not reset by gatP 57 as long as a master disc ~6
is within the drive assembly of Fig. 2.
The operation o~ the Fig. 5 circuit when the disc 26 is
not a master disc is as follows. At a time when the tl
pulse from indicator 35 occur5, flip-flop 50 is again
clo_k~d to have a 1 on its Q output so that the output
from gate 51 is asserted to reset the counter 45O
Assuming that the indicator 36 is either not present or
is pr~sent at a location other ~han at the displacement
"D", comparator 47 will provide, if at all, an output,
to the flip-flop 50 at a ~ime which does not correspond
to a pulse on line 59. Accordingly, the NAND gate 54
is never asserted to gate a l on the Q output of
flip-~lop 55.
Under the condition that there is a ~econd timing
indicator 36 located, however, at other than the
displacement ~D", the operation Df the Fig. 5 circuit is
as follows. Each of the pulses tl, t2~ t3~ . ~ ., t~ on
FORTN2/FPA
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line 59 will cause the gate 51 to be satisfied to assert
~he RESET signal to reset the counter 45. Accordingly,
counter 45 will not reach the full cycle count and hence
decoder 48 will not assert an input to the AND gate 49.
Accordingly, there will be no CYCLE SYNC signal on line
60. The line 60 signal remains a logical 0, which
together with each output asserted from NAN~ gate 51,
resets flip-flop 56 to ensure that the MASTER signal on
line 58 is not asserted. If the absence of a CYCLE SYNC
signal once-per-revolution indicates that an illegit-
imate master disc is in the system.
Under the cQndition where the disc 26 only has a single
timing indicator 35, the operation of the Fig. 5 circuit
is as follows. Each time the tl, t3, t5, and t7 signals
appear on line 59, gate 51 is satisfied to assert the
RESET signal to reset counter 45. The t2, t4, t6, and
58 pulses are not present since counter 45 is only r~set
once per cycle, decoder 48 provides an output at the
same time as ~he signals are asserted fxom line 59 from
detector 33O Therefore, the AND gate 49 becomes satis-
fied once per cycle to assert the CYCLE SYNC signal on
line 60.
At the time that the count in counter 45 matches the
master count in register 46, flip-flop 50 will be
clocked to ~tore a logical 1. However, since there is
no corresponding pulse on line 59, when flip-flop 50 is
clocked, NAND gate 51 is no~ satisfied, nor is NAND ga~e
54 satisfied. Accordingly, the output from comparator
47 in the absence of a timing pulse on line S9 corres-
pondin~3 to the master indicator 36, prevents counter 45
from being resef and prevents flip-flop 55 from being
clocked to store a 1~ The CYCLE SYNC signal on line 60
under this c~ndition continuously resets the flip-flops
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55 and 56. The assertion of a CYCLE SYNC signal on line
when no MASTER signal is asserted on line 58,
indicates that the d.isc 26 may be an authorized copy of
a master.
The decoder 48 is set to have a count which represents
the number of incremental locations that exist when disc
26 makes one complete revolution. In one example,
decoder 48 is set to a count of 252 and counter 45 is an
B-bit binary counter. The divide-by-X circuit 53 has
the quantity "X" s~lected such that 252 clocking inputs
will be provided to counter 45 for each single revolu-
tion of the disc 26. In the example where the displace-
ment nD" is approximately 6Q degrees, and decoder 48 is
set to 252, then register 46 would store a count of 42.
In general, the sizes of the timing indicators 35 and 36
are selected to be greater than the dimension
represented by a single count of counter 45.
Accordingly, the actual diameter of indicator 36 would
be selected such ~hat its location i5 a~ a position
represented by count 41, count 42, and count 43 of
counter 45. Since the clock rate of flip-flop 50 is
X-times greater than the clock rate of counter 45,
f~ip-flop 50 will not miss detecting the master
indicator 36. Of course, the size of the timing
indicator 35 and 36, the number of coun~s represented in
a full cycle (represented by the number decoded by
decoder 48~ and the location of the master indicator 36
relative to the timing indicator 35 ~the contents of
regiscer 46) are all variables which can be detQrmined
as a function of the clocX r~te CLK and the angular
velocity of the disc 25.
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~ ~C~ '3
Authorization Circuit - Fi~. 6
In Fig. 6 t further details o an authorization circuit
are shown. The authorization circuit of Fig. 6 is part
of the bus unit 5-0 of Fig. 1. The ~us unit 5-0 of FigO
1 includes a fle~-disc device 25 and all of the control
eircuitry r.ecessary ~o interface the flex-disc device 25
with the bus ~2. Such control circuitry is standard and
includes a number of conventional itemsO Referring to
Fi~. 6, the ~us unit 5-0 includes a data register 72 in
which data is transferred to and from the disc device
73. The disc device includes the drive assembly of Fig.
20 Register 73 receives data from the disc 26 through
the buffer 87 and multiplexers 70 and 71. Data is
stored in the data resister 72 when register 72 is
enabled by the load data register ~LDDR) signal from a
control and sequencer 65.
The location at which data is read from or stored at in
the disc 26 is determined by the address regis~er 69 of
FigO 6. Address rt'gister 69 is enabled to store an
address by the load address register (LDAR) signal from
the control and sequencer 65~ The address stored in
address register 69 is derived either from the CLBA
address bus 17 which is one part of the CLB bus 22 of
Fig. 1. The high-order address ~its from bus 17 connect
to the decoder 66 for indicat:ing when the address space
of bus unit 5 0 has been addressed. The lo~-order bits
from bus 17 connect as an input ~o ~he multiplexer 68
for loading into the address register 69. The other
input to the multiplexer ~8 is from the code address
generato~ 67. The code address generator ~7 stores the
addresses ~f ~he system identifier field and of the
program name field lccations on the disc 26.
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The address generator is a read-only memory, counter or
other de~ice which outputs add~esses in sequence. The
generator is reset to the startlng address when the
reset siqnal from OR gate 86 is asserted~ Generator 87
is stepped to a new address by assertion of the AS
signal from control sequenc2r 65.
The multlplexer 68 selec~s the address from the code
address generator 67 when the initialized (INIT3 signal
is asserted from the flip-flop B2. The CLBD bus 18
provides data to and from the bus unit 5-0. In Fig. 6,
the bus provides one input to the multiplexer 70 which
in turn provides an input to the multiplexer 71 which in
turn provides an input to the data regist~r 72.
Output data over the bus 18 comes from the buffer 87
wh~ch receives data output from the data register 72.
The multiplexer 70 receives a second input for data from
the disc 26 in the disc device 73~ 9ata is selected
from bus 18 for input to the multiplexer 71 and data
register 72 when the write ~W) signal from the control
sequencer 65 is assertedO When the W signal is not
asserted, multiplexer 70 selects data from the disc
device 73 on bus 610
Data on bus 18 is also inpu-t to the system identifier
register 74 and the program authorization register 92.
Register 74 stores the data ~rom bus 18 when e~abled by
the output from AND gate 89 which receives the INIT and
VIR signals. A system ide~tifier stored in register 74
is sele~te~ by multiplexer 71 for storage in the data
register 72 and for writing onto the disc 26. The
selection by multiplexer 71 occurs when ~he virgin disc
indicating signal, VIR/ from 1ip-flop 78 is asserted.
When VIR is not asserted, mul~iplex~r 71 ~elects ~he
FORTN2/FPA
A-38093/DEL -17-
~2~05/~7
output from multiplexer 70 for storage in data register
72. The system identifier from register 74 is also
selected by multiplexer 76 as one input to the
comparator 64 when the test virgin signall TEST VIR, is
not asserted on the Q output of flip-flop 80. When TEST
VIR is asserted, then the virgin I~ from the ~egister 75
is selected by multiplexer 76 as one input to the
comparator 64. The other input to the comparator 64 is
the OUtp~lt. from the data register 72.
The function of comparator 64 is to compare the co~tents
of data register 72 with a virgin ID from register 75 at
a time when the TEST VIR signal has ~een asserted, and
at other times to cc~mpare the contents of the data
register 72 with the system identifier from register 74.
When the contents compare, the output from comparator 64
is asserted to enable the AMD gates 84 and 85.
In Fig. 6, the OR gate 86 receives the PP signal on line
44 from the gate sensor 31 ot Fig. 2 and is shown
schematically as part of the disc device 73 of FigO 6~
The OR gate 86 also receives a system clear signal,
SYCLR, which is asserted for example whenever the power
to the system of FigO 1 is turned on. The SYCLR signal
is also provided at any other time when the status of
the registers and other storage devices may be in doubt.
Whenever OR gate 86 is satisfied and its output is
asserted, the authorization flip-flop 81 is reset to
provide a 0 on its Q output and a 1 on its Q outputO
If, after operation of the Fig. 6 circuit, the disc
asserted in the assemhly of Fig. 2 is an authorized
disc, the DISC AUT~ signal will enable AND gate 91. If
the program ~tored on disc 26 is authorized for tne
system, then the outpu~ from register 92 will satisfy
FORTN2/FPA
A`38093!D:EL ~ lB-
8~/~5/~7
Lf~
AND gate ~1. The asserted output from gate 91 will
enable flip-flop 81 to store a logical l on its Q output
and a 0 on its Q output.
Whenever flip-flop 81 has been reset, for example, when
the gate 30 of Fig. 2 has been opened to provide the PP
signal on line 44, the AND gate 62 is enabled by a
logical 1 from the Q outpu~ from flip-flop 81. Whenever
the decoder 66 senses that the bus unit 5-0 (see Fig. 1)
is addressed after AND gate 62 has been enabled,
flip-flop a2 is clocked to sLore a logical 1 on its Q
output and thereby assert the INIT signal. The
assertion of the INIT signal functions to cause the
circuit of Fig. 6 to determine whether or not the disc
26 is an authorized disc. The INIT signal is provided
as an interrupt signal to the processor unit 2 of Fig. 1
over line 38u
Also, when the INIT signal is asserted, multiplexer 68
selects the code address from the generator 67 for
storage in the address register 69. The INIT signal is
also input to the control and sequencer 65 for
initiating the output signals from sequencer 65 which
cause the authorization checking functions to be per-
formed by the Fig. 6 apparatus. The INIT siynal is also
input to the AND gate 83 which also receiv~s as its
other input the MASTER line from the master detector 43
of Fig. 5. If the authorization sequence is initiated
by the flip-flop 82 asserting INIT~ and the disc 26 is a
master disc as indicated by the assertion of MASTER,
gate 83 is satisfied to clock a logical 1 to the Q out-
put of flip-flop 80. The Q output of flip-flop 80 when
asserted provides the TEST VIR signal which causes the
disc 26 to be tested to see if it is a virgin master
disc.
FORTN2/FPA
A-380~3/DEL
~2/05~7
t,~
The asserted TEST VIR signal enables the AND gate 84.
The other input t~ gate 84 is the output of comparator
64. The asserted TEST VIR slgna~ causes the multiplexer
7S to provide the virgin ID from register 75 as one in-
put to comparator 64. If the contents of data register
72 are the same as the virgin ID, then the output ~rom
comparator 64 will satisfy AND gate 84 causing the VIR
signal to be asserted on the Q output of flip flop 78.
When VIR is asserted indicating that the master disc in
the assem~ly of Fig. 2 is a virgin, multiplexer 71 en-
ables the system identifier from register 74 to be
stored in the data register 7~ for writing the system
identifier onto the d~sc 26.
The system identifier has been previously loaded into
the register 74 as a result of the interrupt caused to
processor unit 2 when the INIT signal was asserted on
line 38. At the time that the system identifier is
stored in the data register 72 by ~nergization of the
enable signal LDDR from sequencer 65, the flip-flop 77
is clocked to store the TEST VIR signal. At the same
time, the assertion of the LDDR signal resets the virgin
flip-~lop 78.
With the virgin ID stored in register 72, a write cycle
is caused by the assertion of the W signal from the
sequencer 65. The virgin ID is written onto the disc 26
at the address specified by the ~ddress reg~ster 69.
Thereafter, since the VIR signal is non~assert~d, multi-
plexer 71 selects the ~utput from multipl~xer 70 as the
input to the data re~ister 72. The control ~equencer
causes a read cycle by assertion of ~he R line which
causes ~he system identifier to be read ~rom the disc
device 73 and stored in the data register 72
FORTN2/FPA
A~3~0a3/DFL -~
82/35/27
When the flip-flop 77 was clockecl by the LDDR signal, it
asseIted its Q output to reset the flip-~flop B0 thereby
causing the TEST VIR signal to be non-asserted. The
multiplexer 76 therefore provides the syst~m identifier
from register 74 is one input to comparator 6~ along
with the system identifier from data register 72
previously read from the disc 26. When comparator 64
asserts its output, AND gate 85 has been enabled when
flip-flop 80 was reset, so that flip-flop 79 is clocked
to asser~ the disc authorize signal DISC AU~rH. The DISC
~UTH signal clocks the flip~flop 81 and asser~s the ~UTH
signal. The asserted AUTH signal resets the flip-flop
82 negating the INIT ~ignal while resetting flip-flops
77 and 79. With INIT negated, the interrupt on line 38
is removed and the Fig. 6 circuit thereby indicates that
the disc 26 is authorized to be accessed by the CLB bus
22. With the INIT signal negated, the multiplexer 68
connects the address bus 17 directly to the address
register 69 and bus 18 connects to or from the data
register 72.
In Fig~ 6, the control se~uencer 65 is a standard
sequential logic device ~hich operates in a eonventional
way to provide a number of sequential signals. Those
signals include the LDAR sianal for enabling the address
register 69, the LDDR signal for enabling the ~ata
register 72, the W signal for con~anding a write
operation of the contents of data register 72 onto the
disc 26, an R signal for providing a read operation for
reading the contents ~f disc 2S into the data register
72, and an AS signal for incrementing the address
generator 67. These signals ar~ provided in a
conv~ntional manner for reading and writing data when
~he INIT signal has not been asserted. However, when
the INII signal ls asserted, the control sequencer 65
FORTN2,'FPA
A 38093/DEL -?l=
~2/05/27
f~ ~
provides a sequPnce of outputs for implementin~ a
pro~ram protection mechanism. which are explained in
detail in connection with the following TAsLE 1:
TABLE 1
LDAR = (INIT * T1)
* [Load AD Normal] * INIT
R - (TEST VIR * INIT * T2 )
+ (TEST VIR * VIR * INIT * T5 )
+ (VI R * T6 * INIT)
lRead Normal] * INIT
W = IVIR ~ INIT * LDDR * T4 )
+ [Write Normal~ * INIT]
LDDR = (VIR * INIT * T3 )
+ (R * INIT) * ~T2 ~ T5 * T6)
lLoad DA Normal ] * INIT
AS = Tl + T2 -~ T3 + T4 * T5 + T6
Ft)RTN 2 / F PA
A-38093/DEL 22-
82/05/~7
In TABLE 1, th2 asterisk syn~ol ~" represents a logical
AND and the plu~ symbol "~ represents a logical OR. In
TABLE l, the last line of each of the equations except
for AS represents the normal operation when the
initiation signal INIT has not been asserted. All of
the other lines represent the operation of the sequencer
when INIT has been asserted.
Disc Auth~rization Operation
The GperatiOn of the Fig. S circuit is described when
gate 30 has been opened and a master disc 26 has ~een
placed into the disc assembly of Fig. 2. When the gate
30 is open, the PP signal is received by the OR gate 86
to reset flip-flop 81. Flip-flop 81 enables AND gate 62
when the system of Fig. l addresses the bus unit 5-0,
the decoder 66 causes AND gate 62 to be satisfied
causing flip-flop 82 and asserting the INIT signal.
With INIT asserted, the LDAR signal, as indicated in
TABLE l, is initiated at Tl loading the address register
with ~he contents of the code address generator 67. The
address in generator 67 is the address of the field at
which the system identifier i5 stored on the disc 26.
The INIT signal causes an interrupt to the processor
unit 2 which in turn causes the system identifier to be
loaded into the generator 74 of Fig. 6 which is enabled
to receive the s~stem identifier because INIT is
asserted.
The INIT signal and MASTER signals a~e asserted to
satisEy gate 83, thereby causing the assertion of TEST
VIR. The TEST VIR signal together with the INIT signal
asserted, as indicated in TABLE l, causes the R signal
to be asserted at T2, thereby reading the contents of
disc 26 of the address specified by register 69. The
information read from disc 26 is stored into the data
E'OR~N2fFPA
A-3~093/DEL -23-
~2/t)5,'~7
register 7? through multiplexers 70 and 71. The
assertion of the R signal at T2 in the presence of the
INIT signal, as indicated in TABLE 1, causes the LDDR
signal to be asserted at T2 to enable the data register
72 to store the data from the disc 26. With TEST VIR
asserted, multiplexer 76 selects the virgin ID from
register 75 then compares it with the data in register
72. If the virgin ID from register 75 and the conten~s
of regi,ster 72 are the same, then the comparator 64 has
its output asserted to cause the ass~rtion of VIR from
flip-flop 780 If the contents of register 72 and 75 are
not the same, then comparator 64 does not have an
asserted output and the VIR signal will not he asserted.
In the example where the disc 26 is a virgin master,
then the system identifier from register 74 is loaded
i.nto the data register 72. Data register 72 is loaded
by the LDDR signal which, as shown in TABLE 1, is
asserted at T3 when both VIR and INIT signals are
asserted. When the LDDR si.gnal at T3 causes the system
identifier to be stored in the register 72, the write
signal W~ as seen in TABLE 1, is asserted at T4 to write
~he contents of data register 72 onto the disc ~6. The
loading of the register 72 with the system identifier,
by the assertion of the LDDR si.gnal at T3, negates the
VIR signal. Under these conditions, the R signal is
asserted at the T5 time ~o store the system identifier
read from disc 26 in the data register 72~ The LDDR
signal is asserted at T6 time to stor~ the data read
from the disc into register 72. ~.
At this time the contents of register 74 are ~ompared
with the system identifier contents of register 72 from
the disc and, in the absence of an error condition the~
should compare. ~ND gate 85 i~ satisfied asserting the
FO~ J~P~,
A-~u.,~'.'L -24-
~3 7 ' ~
DISC AUTH signal which in turn enables the AND gate 91.
If the program authorization register is also set, gate
91 will :be satisfied to assert ~he AUTH ~ignal from
flip-flop 81. The AUTH signal negates the INIT signal
and the clisc 26 is ready for normal accessing by the
system of Fig. 1.
In the example described where the disc was not a virgin
and VIR from flip flop 78 was never asserted, the system
identifier in register 74 is never loaded into the
register 72 and is not written onto the disc 26.
The operation of the Fig. 6 circuit when the master disc
is not a vlrgin is as follows. When comparator 64
determines that the contents of th~ data register 7~ are
not the same as the contents of the register 75, the VIR
signal is not asserted. The read operation at T2 which
places the data in register 72 resets the flip-flop 77
and negates the TEST VIR signal after the next C~K.
With VIR and TEST VIR negated~ thP mul~iplexer 76 is
switched to select the output frorn the system identifier
register 74 so that it is then compared with the
content~ of data register 72. If a comparison occurs,
gate 85 ~s enabled and flip-flop 79 is clocked to assert
the DISC AVT~ signal. If the program is also
authorized, the DISC AUTH signal satisfies AND gate 91
and that clocks flip-flop 81 to assert the AUTH signal
and negate the INIT signal. When INIT is negated, the
interrupt 38 i.5 removed and the bus unit 5-0 of Fig. 1
is available for general useO This operation will occur
for a non-virgin master disc. A non-virgin master disc
is one which is alr~ady been authorized for use in the
system of .Fig. 1.
FORTN2/FPA
A-38093/~L ~25-
82/0~/~7
The operation of the Fig. 6 circuit when the disc 26 is
not a master disc is as follows. If disc 26 is not a
master, the MASTER signal will be negated and hence the
output from ~ND gate 83 will not be asserted.
Accordingly, T~ST VIR and VIR will not be asserted.
Accordingly, a read oper~tion during ~he T5 time of
TABLE 1 will read the data from the address specified by
address register 69 The data from the addressed loca-
tion in the disc 26 is stored in the data register 72.
If the contents of register 72 from disc 26 are th~ same
as the contents of the system identifier register 74,
comparator 64 will asse~t its output and satisfy AND
gate 85 which is clocked through flip-flop 7~ to assert
~he DISC AUTH signal which, for an authorized program,
in turn asserts the AUTH signal and nagates the INIT
signal. Under this condition, with z. logical 1 output
from comparator 64, the disc 26 is an authorized copy of
an authorized master. If the contents of data register
72 ancl 74 are not the same, then the output from
comparator 64 will not be asserted and hence neither the
DISC AUTH or the AUTH signals will be asserted. Hence
the INIT signal will remain asserted and the interrupt
on line 38 will not be removed. The processor unit 2
will reco~nize when the interrupt on line 38 is not
removed within a sufficient period of time and will
issue a program protection exception identifying that
the disc engaged in the bus unit 5-0 is not authorized.
In the Fig. 1 system, the processor unit 2 functions to
detect the interrupt on line 38 in a conventional
manner The address of the bus unit 5-0 which causes
the interrupt on line 38 has been supplied by the
processor unit 2 on the bus 17~ When the programmable
array loyic unit 88 of Fig. 1 is ena~led by the VIR
signal, unit 88 responsively provides an output on the
FORTN2/FPA
A-38093/DEL -2fi~
~2/05/27
data bus 18~ The output on data bus 18 is transmittecl
to the :bus unit 5~0 and is stored in the system
identifier register 7~ by the output of AND gate 89 i.n
the m~nner previously desc7ibedO
In the example described, the array logic unit 88 is
addressed by a single address sequence~ Howeverl
multiple sequential addresses for addressing unit 88 can
be required before the proper output from unit 88 will
occur. ~rhe use of multiple sequential addresses greatly
enhances the protection provided against attempts at
breaking the prot~ction mechanism.
The programmable logic 88 provides the system identifier
whicn is used to determine whether or not the disc 26 is
an authorlzed disc. In the case of a virgin master
disc, the programmable array logic 88 prvvides ~he
system identifier which is stored on ~he disc to form a
non-vixgin master disc and thus authori~ that disc, and
any copie, thereof for use on the system of FigO 1. The
programmable array logic 88 can perform any function on
the input. a~dress on bus 17 to provide the system
identifier on the output ~us 180 In one example, the
output on bus 18 can be identical to the address on bus
17 and heoce the system iden~ifier is merel.y the address
of the programmable array logic 88
Authorized Pro~ram Operation
In Fig. l,, the non~volatile store 90 is connected to be
addressed by bus 17 to provide an outpu~ on data bus 18
The non-volatile store 90 is a devicP which is
addressab~.e by adclress b.Lts on bus 17 to store
informatic)n from bùs 13 ~r ~o read ou~ information to
bus lB depending upon the state of the VIR signal~ Whe~
VIR is asserted, stQre 18 wi~.l re(~e~v~ information from
FORTN?/FP~
A~38093tDEL -27
~2/05/27
f~
bus 18 and store that information at the addressed
location. When VIR is not asserted, store 90 only
operates :in the read mode and provides output data to
the bus 18. The non-volatile store 90 functions to
retain its infoxmation even if the power for the Fig. 1
system is turned off and then returned to on.
Store 90 is addressed for reading to determine whether
or not the program contained on the disc has been
authori~ed for the system of Fig. 1. In one exampl2,
th~ non volatile store 90 includes an 8-bit field of
program names wh~re up to 256 different programs can be
authorized for use with the Fig. 1 system. The
high-order address bits on bus 17 are decoded to select
the store 90 in a conventional manner and the low-order
8-bits o~ the ~ddress correspond to the possible program
names on the disc~ Store 90 is, therefore, an
authori~ed program store which stores an indication for
each program up to some maximum which is authorized.
When the INIT signal is sensed by the pxocessor 2 and
provided that the VIR signal is present, the processor
unit 2 first addresses the programmable array logic ~8
in Fig. 1 to access the system identifier. The system
identifier is stored in the register 74 of Fig. 6 as
previously described. Next, ~he processor 2 monitors
the VIR signal and, if the VIR signal is present, it
will update the non-volati~e store 90 at the appropriate
time. The appropriate time occurs after the T6 signal.
If the VIR signal ~5 been present, then 'che processor
unit 2 carries out a WRITE operation in the non-volatile
fitore 30. The low-order address bits are the program
name ~rom the disc 26. A logical one bit is stor~d into
~he non-volatile store at the program addrPss de~ermined
FORTN2/FPA
A-38093/DEL 28-
82/OS/~
,.
~a~3:~,d~
when the program nam~e is accessed from the data xegister
72 for a ~irgin master disc.
After a l~RITE operation for a virgin master disc (VIR
asserted) or directly for any non-virgin disc (VIR not
asserted), the store 9~ is read using ~he program name
for the l~w-order address. The single bit sf data, 1 or
0, is transmitted over bit 9 vf bus 18 and stored in the
program authorization register 92 to provide the PROG
~UTH signal. If the program is properly authorized for
the system, the register 9~ will store a logical 1 and
will thus satisfy the AND gate 91 provided the DISC AUTH
signal has been asserted by flip-flop 79 in Fig~ 6. If
either the disc i5 not authori~ed, that is the DISC AUTH
signal is not asserted, or the program is not
authorized, that is the PROG AUT~ signal from register
92 i~ nct asserted, then the gate 91 will not be
satisfied and the DP AUTH signal will not be asserted.
If either th~ di~c is not authorized or the program is
not autho;rized, flip~flop ~1 will not be clocked to a 1
to as~ert the AUTH signal. If the AUTH signal is not
asserted, t~en flip-flop B2 is not reset and the INIT
signal remains asserted as an interrupt signal to the
processor ~ on line 38. If the INIT signal is not
removed within a predetermined time, then processor 2
recognizes that ~ program protection exception has
occurred and will continue further processing without
permitting access ~o the di~c 26 for normal reading and
writing.
While ~h~ inv2ntion has been particularly ~hown and
descri~d ~i~h reference to the preferred embodiment
~hereof, it will be understood to ~hose skilled in the
art that changes in form and details may be m~de therein
FOR~2~FPA
k-38093/DEL 29-
82/05/27
without departing from thP ~pi~it and the scope of the
invention .
FORTN2 /FPA
A-38o93JDEL ~30
~2,~5~7
