Note: Descriptions are shown in the official language in which they were submitted.
Three-dimensional semiconductor device
The present invention relates to a semiconductor device
having a three-dimensional structure, and more particularly
to a three-dimensional semiconductor device that is well-
suited for attaining a high density of integration.
As is well known, most conventional semiconductor
devices employ elements, such as transistors, formed in the
surface region of a semiconductor substrate. E~en an LSI
with a high integration density is formed in the surface
region of a semiconductor substrate.
Since the numbers of such elements formed in surface
regions of semiconductor substrates has markedly increased
in recent years, it has now become difficult to increase
these numbers still further.
To solve this problem there has been proposed a
so-called three-dimensional semiconductor device in which
insulator films and single-crystal semiconductor films are
stacked alternately on a semiconductor substrate, a large
number of elements being formed in each of the semi-
conductor films.
For example, a three-dimensional semiconductor device
has been proposed having a structure wherein p-channel MOS
transistors are formed on a substrate side, stacked Si and
3 ~
insulator films are formed thereon using the well-known
SOI(Silicon On Insulator) technique, and n-channel MOS
transistors are formed utilizing the interfaces of the Si
and Si02 films~ This device employs a single gate as a
common gate for the upper and lower MOS transistors,
thereby making it possible to operate the p-channel and
n-channel MOS transistors simultaneously by the single
common gate. (Gibbons et al., IEEE, DEL-l, 117, 1980).
Since, however, such semiconductor devices with three-
dimensional structures are not long-established, a novel
structure must be found, in order to fabricate a device
that has a still higher density of integration and affords
new functions.
An object of the present invention is to solve the
problem of the prior art and provide a three-dimensional
semiconductor device that has a high density of integration
and affords new functions.
In order to accomplish the object, the invention
provides a three-dimensional semiconductor device compris-
ing at least one layer of insulator film and of single-
crystal semiconductor film stacked alternately and formed
on a semiconductor substrate, and at least one impurity-
doped region of low resistivity formed within each single-
crystal semiconductor film, whereby a plurality of MOS
transistors is formed utilizing said impurity-doped region
as a gate, source or drain region.
Figure 1 is a model diagram for explaining the
construction of the present invention; and
Figures 2a and 2b, Figures 3a and 3b, and Figures 4a
and 4b are respectively sectional views and circuit
diagrams showing different embodiments of the present
invention.
In Figure 1, numeral 50 designates a single-crystal
semiconductor substrate, numerals 61 to 64 designate
insulator films, numerals 71 to 73 designate single-
crystal semiconductor films, and numerals 101 to 115
designate p+ or n+ doped regions formed by well-known
processes such as ion implantation and ~hermal diffusion.
The regions 114 and 115 located in the uppermost layer may
be formed of a conductor such as A metal or of heavily-
doped polycrystalline silicon, not by doping a single-
crystal semiconductor with an impurity.
In this manner a plurality of MOS transistors are
formed in the planar direction and vertical direction of
the semiconductor substrate.
When the doped region 111 is used as a gate, the doped
regions 108 and 109 formed in the underlying semiconductor
layer 72 serve as drain and source regions, respectively,
so that one MOS transistor is construGted.
Likewise, when the doped region 11~ is used as a gate,
the doped regions 109 and 110 respectively serve as drain
and source regions to constitute a MOS transistor.
The doped regions 108, 109 and 110 referred to above,
however, can also be used as gates, rather than as source
or drain regions. In this case, the semiconductor layers
104, 105, 106 and 107 underlying those doped regions serve
as drain or source regions, respectively.
In addition, when the uppermost doped regions (which
may well be the conductive films) 114 and 115 are used as
gates, the doped regions 111 and 112 exemplified as the
gates in the above example and the doped region 113 serve
as drain or source regions.
Thus, among the plurality of doped regions, the
uppermost ones 114, 115 are used only as gates and the
lowermost ones 102, 103 only as source or drain regions,
whereas the intermediate ones 104, 105, ...... and 113 can
be used as both gates and source or drain regions.
The intermediate doped regions 104, 105, ...... and 113
can also function as gates, not only for the underlying
doped regions, but also for ~he overlying doped regions.
For example, the doped region 105 can be used as the
gate of a MOS transistor whose drain and source regions
are the underlying doped regions 101 and 102, respectively,
and it can also be used as the gate of a MOS transistor
whose drain and source regions are the overlying doped
regions 108 and 109, respectively, That is the doped
region 10S can be used as the common gate of both
transistors.
Accordingly, if the regions 108, 109 are p regions
and the regions 101, 102 are n+ regions, by way of
example, the p-channel MOS transistor and the n-channel MOS
transistor can be operated simultaneously by the common
gate region 105.
The doped regions 109 and 110 can also serve as a drain
and a source, acting with the two doped regions 112 and 106
as gates located above and below. Two MOS transistors
operated by ei~her of the gates 112 and 106 are thus
provided.
As thus far described, at least one layer of insulator
film and single-crystal semiconductor film are stacked
alternately and formed on a semiconductor substrate, and
at least one p or n+ doped region is formed within
the semiconductor substrate or within each semiconductor
film to form one or more MOS transistors out of a gate
electrode or electrodes provided in the uppermost layer
and the doped regions within the semiconductor film of the
underlying layer and also to form other MOS transistors
out of ~hese doped regions and the doped regions within
the semiconductor film of the still further underlying
layer. Regarding the two MOS transistors formed on the
upper layer side and the lower layer side, the source
-- 5 --
(drain) of one transistor can also serve as the gate
electrode of the other transistor, while the same can
simultaneously serve as the source (drain) of the other
transistor.
Embodiment 1:
Figure 2a shows a sectional structure of an embodiment
of the present invention, while Figure 2b is a circuit
diagram thereof. In these figures, the same reference
numerals denote the same parts.
This embodiment is an example wherein a two-stage
inverter circuit is formed using one impurity-doped region
as the source of one of two MOS transistors and
simultaneously as the gate of the other MOS transistor.
First, n+ impurity-doped regions 3, 4 and 6 are formed
in a semiconductor substrate 1, after which an insulator
film 2 is formed. Subsequently, amorphous or poly-
crysta~line Si is deposited on the whole surface, and the
deposited amorphous or polycrystalline Si layer is ~urned
into a single crystal or nearly a sinyle crystal by a well-
known method such as laser beam irradiation, electron beam
irradiation, or local heating with a rectilinear heater.
Thereafter, a gate oxide film 7 and gate electrodes 8 and 9
are formed, after which, using the electrodes 8 and 9 as a
mask, an n+ impurity is introduced into selected regions
to form n+ regions 3', 5 and 6'.
The device manufactured in this way forms a two-stage
inverter circuit in which four MOS transistors Tl - T4
are connected as shown in Figure 2b~
More specifically, the first transistor Tl is
composed of the gate electrode 9 and the source and drain
5 and 6', the second transistor T2 is composed of the
gate 8 and the source and drain 3' and 5, the third
transistor T3 is composed of the gate 6' and the source
and drain 4 and 6, and the fourth transistor T4 is
composed of the gate 5 and the source and drain 3 and 4.
Here, the n+ region 5 serves as the source of the first
transistor Tl and simultaneously as the gate of the
fourth transistor T~, while the n~ region 6' serves as
the drain of the first transistor Tl and simultaneously
as the gate of the third transistor T3. Further, in
this case, the impurity~doped layers completely isolated
by the insulator film 2 and the layers partly connected
coexist, which forms one feature of this embodiment. More
specifically, in the transistor T4, the gate 5 and the
source 4 are completely isolated by the insulator film.
As to the transistors T4 and T2, however, these two
transistors are connected by the n+ regions 3 and 3'.
In other words, the upper and lower transistors T2 and
T4 are connected by the n+ regions 3 and 3', which is
advantageous for constructing a three-dimensional device.
In this manner, according to the present embodiment, a
plurality of MOS transistors can be formed in the vertical
direction comparatively simply, and it has become possible
to form four MOS transistors within an area that has been
occupied by only two MOS transistors in the prior art.
Embodiment 2:
Figure 3a shows a sectional structure of another
embodiment of the present invention, while Figure 3b is a
circuit diagram thereof.
This embodiment is such that an OR circuit is
constructed using a single impurity doped region as the
common sources (drains) of two MOS transistors. The
manufacturing process of this embodiment is substantially
the same as in the case of Embodiment 1. Three MOS
transistors T5 - T7 are constructed on a semiconductor
substrate 10 by means of impurity-dcped regions 12, 13, 14
and 15, insulator films 11 and 16, and gate electrodes 17
and 18. The first transistor T5 is composed of the gate
18 and the source and drain 14 and 15, the second
r
transistor T6 is composed of the gate 17 and the source
and drain 12 and 14, and the third transistor T7 is
composed of the gate 13 and the source and drain 14 and
15. Here, the doped regions 14 and lS are the source and
drain of the first transistor T5 and simultaneously the
source and drain of the third transistor T7. Now,
employing the doped region 13 and the gate 1.8 of the first
MO5 transistor T5 as input terminals~ if an input voltage
enters either of them, an output is generated at the output
terminal (doped region~ 14. The present embodiment thus
becomes a NOR circuit. The logic circuit composed of these
three transistors is formed within an area occupied by only
two transistors in the prior art.
Embodiment 3:
Figures 4a and 4b are a sectional view and a circuit
diagram showing another embodiment of the present
invention, respectively.
This embodiment is extended to a structure that has a
larger number of layers than in Embodiments 1 and 2. It
extends the inverter circuit o~ two stayes shown in Figure
2a to an inverter circuit of three stages, the reference
numerals being essentially the same with those having
double primes duplicating those with single primes.
According to the present embodiment, six MOS transistors
can be formed within an area occupied by two MOS
transistors in the prior art.
While, in the foregoing embodiments, all the
impurity-doped layers have been n+ layers, similar
circuits can be formed when the impurity-doped layers are
p+ layers.
