Note: Descriptions are shown in the official language in which they were submitted.
65~
AUTOMATIC TEMPERATURE MEASURING CIRCUITRY
Introduction
This invention relates generally ~o ~irouitry for measuring
temperature and, more particularly, to bridge ci~cuitry utilizing
precision resistance thermometers for providing automatic measure-
ment of temperature.
BacXgroun~ of the Invention
Standard platinum resistance thermometers (SP~T) have been
used to measure temperature, the resistance of such elements being
related to temperature in accordance ~ith standard equations as
defined with reference to the International Practical Temperature
Scale (TPTS). Since such elements provide accurate measurements
of temperature as needed in many applications, there has existed
a further need for making rapid measurements of the resistances of
Isuch devices in an automatic fashion.
Automatic measurement of such resistances to the required
!degree of accuracy have previously been suggested by those in the
art utilizing direct current methods. However, the use of DC
circuitry is not practical in most applications requiring high
accuracy because of -the problems encountered with respect to
thermally generated emf's and detector noise levels. Accordingly,
attention has been directed toward the use of AC bridge circuits
whiGh would eliminate such problems.
Previously suggested AC bridge circuits (both manual and
!
automatic embodiments thereof) have generally used one of two
basic approaches. A first approach maintains essentially the same
current through the standard platinum resistance thermometer and
! through a reference resistor and then measures the ra~io of the
ivoltages thereacross. The voltage ratio measurements.are
'conventionally made by using adjustable ratio transformers. Such
~L2~56~
an approach has been described, for example, in the article by
Hill and Miller, Proc. Inst. Electr. Eng., Vol. 110, No. ~53.
(1963). Such article describes a double bridge configuration
analogous to Kelvin double bridge circuitry using two complete
adjustable voltage ratio transformers. An automatically oper-
ated version of such bridge circuit has also been made avail-
able by Au-tomatic Systems Laboratories, Ltd. of Leighton
Buzzard, England
A later version of an AC bridge circuit using a
three-stage ratio transformer in which two stages are driven by
unity-gain buffer amplifiers to provide the required input
impedance has been suggested in the article by Cutkosky, Jour.
Res. of Nat. Bur. Stds., Vol. 74C, ~os. 1 and 2, 15 (1970).
An automated version of such bridge circuit, controlled by an
appropriate micro-processor, was later described by Cutkosky
and used 15Hz. or 30 Hz. square wave excitation and a five-
stage transformer to achieve the required input impedance in
parallel with a reference resistor. The latter circuitry is
described in the article by Cutkosky, IEEE Trans. Instr.
Meas., Vol. lM-29, No. 4 (1980).
In the later Cutkcsky design the input impedance is
progressively increased from stage to stage by connecting each
stage in parallel with five equal resistors all connected in
series with each other and in series with the SPRT device. The
value of each resistor becomes progressively more critical from
the first to the fifth stage and the fifth stage resistor rep-
resents the required reference resistor.
Anot~er approach suggested by the ar-t adjusts the
relative magnitudes o-f the currents in order to maintain the
voltages across the reference resistor and the standard plati-
rq~
,r~r
--2--
~LZ~S~O
num resistance thermometer equal. Such approach became feas-
ible with the development of a DC current comparator which
could provide DC measurement of high precision. Such a DC
comparator has been described, for example, in the article b~
McMartin and Kusters, IEEE Trans. Inst. ~ Meas., lM-15, No. 4
(lg66) .
All of the previously suggested designs utili2e the
inherent stability and accuracy of ratio transformers and
require only a single reference resistor in order to achieve
performances substantially superior to purely resistive bridges
which normally require a multiplicity of critical resistance
values and resistance ratios and which are sensitive to thermal
coefficients and thermal emf's. In order to achieve automated
operation for the bridge balancing process, such designs
required numerous electromechanical relays. Because the
switching circuits were carrying significant currents, they
could not tolerate the use of solid state switches, such as
field effect transistors (FET's) which have finite resistances
in their "ON" states.
Brief Summary of the Invention
In accordance with the invention a basic bridge cir-
cuit utilizes constant current reference circuitry for
providing a constant reference current through a precision
reference resistance and through a standard platinum resistance
thermometer (SPRT) element. The vol-tage across the SPRT ele-
ment is supplied to a fixed-gain amplifier circuit -the output
of which is in turn supplied to a digital-to-analog (D/A)
measurement circuitry. the D/A circuit permits an effective
determination of the ratio of the output from the fixed-gain
amplifier circuit and a reference voltage across a ~nown refer-
i~
~2~S6~i~
ence resistance in the constant current reference circuit. The
resistance of the standard platinum resistance thermometer can
then be determined in terms of the value of the fixed-gain of
the fixed-gain amplifier circuit, the value of the reference
resistance, and the value of such voltage ratio.
Such circuitry, as described in more detail below,
provides for a completely automated measurement of the SPRT
resistance ~ith very high accuracy, which resistance can be
readily converted using appropriate micro-processor circuitry,
for example, to a temperature reading w~ich has an ex~remely
low error. The overall circuitry is designed so that sui-table
solid state switches and transformers of relatively simple
construction can be used, thereby providing relatively high-
speed operation having relatively low noise and high reliabil-
ity.
Thus, in accordance with a broad aspect of the inven-
tion, there is provided an AC temperature measurement system
comprising: a temperature resistance element having a resist-
ance value which varies with temperature; a reference resist-
ance element having a predetermined fixed value and connectedin series with said temperature resistance element; means for
supplying a substantially constant AC current through said
temperature resistance element and said reference resistance
element; AC feedb~ck amplifier circuit means responsive to the
AC voltage across said temperature resistance element for
amplifying said AC voltage by a fixed gain to produce an ampli-
fied AC voltage output; means for providing an AC reference
voltage across said reference resistance element; means for
effectively determining the value of the ratio of sald AC volt-
age output to said AC reference voltage; means for determining
--4--
~Z~565~1
the resistance value of said temperature resistance element as
a function of said reference resis-tance value, said fixed gain,
and the ratio of said AC voltage output to said AC reference
voltage; and means responsive to said temperature resistance
value for determining the temperature represented thereby.
Description of the Invention
The invention can be described in more detail with
the help of the accompanying drawings wherein
Figure 1 depicts a block-diagram of an embodiment of
the invention;
Figure 2 depicts a more specific partial block and
partial schematic diagram of the embodiment of Figure l;
Figure 3 depicts a more specific partial block and
partial schematic diagram of a portion of the embodiment of
Figure l;
Figure 4 depicts a timing diagram helpful in explain-
ing the operation of Figure 3;
Figure 5 aepicts the interconnection of the reference
circuit of Figure 1:
Figure 6 depicts a partial block and partial schemat-
ic diagram showing mcre particularly the D/A converter of
Figures 1 and 2;
Figure 7 depicts in diagrammatic form the switches
used in the D/A converter of Figure 6; and
Figure 8 depicts a partial block and partial schemat-
ic diagram showing the automatic quadrature balance circuit of
Figure 3.
The si~plified block diagram of Figure 1 can be used
to illustrate the principles of operation of the circuitry of
the invention. As can be seen therein, AC source 10 supplies
--5--
:~Z~S65~
an AC voltage through a primary winding llA of a first stage of
a transformer 11, the secondary winding llB of which provides a
drive voltage ED to a reference current circuit 12 which in
turn supplies a constant current IREF to a standard plat-
inum resistance thermometer (SPRT) element 14 having a resist~
ance RT which is proportional to the temperature.
The voltage ~T across SPRT elemen-t 14 is supplied
to a fixed-gain ~C Eeedback amplifier circuit 15 (identified as
having a fixed-gain GF) which produces an outpu-t ~ol-tage
Eb. Such voltage is supplied to D/A measurement circuit 16
which is arranged so that when a plurality of switches therein
are suitably set (as discussed in more detail below), the volt-
age Ea therefrom can be made substantially equal to the volt-
age Eb.
The reference circuit 12 includes a reference
resistance 13 through which the current IREF flows, the
voltage across such reference resistance being designated as
EREF. The voltage ET across SPRT element 1~ can be
defined by the current therethrough and the resistance thereof
as
ET = EREF RT
RREF
Since the voltage Eb is related to the voltage ET
by the gain GF of fixed-gain amplifier 15, the resistance of
SPRT element 1~ can be expressed as follows:
RT - Eb RREF
EREF GF
Since the resistance of reference resistor 13 and the
gain of amplifier 15 are known and predetermined, if the ratio
6-
56S~
of the voltages Eb/EREF can be determined, the resist-
ance of the thermometer element can also be determined.
If the voltage Ea is set equal to the voltage Eb
by the controlled operation of the D/A measurement circuit via
the detection/integration circuitry 17 and control logic 18 (as
discussed below), the resistance of SPRT element 14 can be
expressed as
RT = Ea RREF
EREF GF
It is found that, if the switches in D/A measurement
circuit 16 are set by control logic 18 for such condition, such
switches in ef~ect represent a binary number the decimal equiv-
alent of which is proportional to the value of the ratio
Ea/EREF. Accordingly, the resistance of the SPRT
element 14 can be calculated (using suitable computational
logic such as available through the use of a microprocessor)
from the known values of RREF and GF and from the value
of the ratio Ea/EREF suitably determined from the
settings of the switches in the D/A measurement circuit 16.
Using appropriate look-up tables, or suitably devise algorithms
known to the art for example, the microprocessor can thereupon
determine the temperature in accordance with the known Inter-
national Practical Temperature Scale which defines the
relationship between the SPRT resistance RT and temperature.
A more specific con~iguration of an overall resist-
ance thermometer circuit is shown in Figure 2 in which AC
source 10 is a suitable sine wave oscillator 20 which supplies
the primary winding llA of the first stage of transformer 11
with a sine wave signal at a suitably selected frequency which
in the particular embodiment being described herein, for exam-
~ 6a -
ple, is 384Hz. The secondary winding llB of transormer 11
provides the input drive voltage ED for the reference current
circuit 12 which includes reference resistor 13 and a standard
platinum resistance thermometer 14 as shown. The reference
winding llC of the second stage of
6b -
~2~S6~;V
Lr~ rorll~r 11 and a high gain AC feedback amplifier 18 are connected as
shown so that the current IREF through SPRT 14 is c3nstant and provides a
voltage ET thereacross~ l'he voltage ET is supplied to fixed-gain ~C feed-
kack amplifier circuit 15. Such circuitry ;n~ an input trAncif~rmPr 22,
op-amp 23 and output LLAn~ir(~rl'~r 25. A feedback winding 26 of output trans-
former 25 provides the output voltage ED of circuit 15. The overall circuit
has high -Q and is sharply tuned to provide a relatively high gain such that
Eb--Gf ET. The circuit should have a peak amplitude at the operating fre-
quency of the system (e.g., 384 ~z) and the overall phase shift in-troduced
by the trAn~f~rmPrs and op-amp should be ~u~L~lLially less than 180 at
fL~u~l~ies at which the closed loop gain is unity.
'~he D/A mea~uL~,~lL circuit 16 comprises a first two-stage trans-
former having stages i~nt;f;~ as Tla and Tlb in Figure 2 followed by a
second two-stage i,~ ~",~, having stages ;~nt;f;~ as T2a and T2b in
Figure 2. me settings of v~ri~hl~ winding llD of stage Tlk and of v~r;~hl~
winding llE of stage T2b as de~rm;n~ by control logic 18 produces the de-
sired voltage Ea. When (Ea-Eb) is effectively reduced to zero, such voltages
are equal as desired.
As can ke seen in Figure 2, the rela~;r~n~;p of Ea to ERF can be
determ;n~d in ~(~()r(l~ri(~ with the number of turns on wnn~l;ngs llC, llD and
llE as follows:
Ea =(Na ~ Nbk~
E~EF NREF
where Na are the turns on windirlg llD of Tlb, Nb are the turns on winding 11E
of T2b, NREF are the turns on winding llC of Tlb and k is the stepdown ratio
of T to T
~5~S~
The nu~ker of turns Na and Nb are de~Prm;nPd by the settings of a
plurality of FET switches (~ cn~Pd in more detail kelow for a specific
~mtcdime~t of the D/A circuit 16) represented in Figure 2 by settings Sa and
Sb Such settings are controlled by control logic 18 which utilizes a suc-
cessive approximation tec~nique until the value of Ea is equal to Eb in a
first operation w~ich pr.ovides switch settings representing the most signifi-
cant bits (MSB) of the binary number, fQllr~ by a second operation which
provides the least sign;f;c~nt bits (LSB), as discussed below.
A suitable -technique u~ ;ng a ~c~sxive approximation for pro-
viding the desirea operation to produce the settings for switches Sa and Sb
has been rlP~rr;hPd in detail in my rn~Pn~ing ~n~ n application, Serial
No. 437,490, entitled "Systems for Providing Digital Representations of
Analog Values," filed S~t~.~r 24, 1983. m e overall circuitry for such
operation is gPnPr~lly ~ uced in its general form in Figure 3 and, as
explained in the aforesaid r~r~nrl;ng application, has two distinct modes
of operation.
m e purpose of such circuitry during the first mcde of operation
is to provide to a ~rCpc~ive approximation register (SAR), which controls
the settings of D/A s~itch.es, an indication as to whether the output of the
D/A cullv~lLeL is y~at~l or less than the output of the bridy-e, i.e., is
Ea greater or less than Eb. Cul~se~u~llLl~, during this m~de the input
switch Sc and the mcde control switches Sla U~uyh Sld are in the position
shown. The difference Ee between ~ and Ea will be in phase or 180 out
of phase ~Pr~n~in~ on whether Eb is yl~dLeL or less than Ea. Such "error"
signal is amplified in a preamplifier 30, detected in the phase sensitive de
tector 31 and the reulting ~C signal is then applied to a relatively fast
--8--
~2~5~5~
"finite" time integrator 32 the output thereof being supplied to a C~l~d_dLUl
OP-AMP 33. me reset s~itch Sd of the integrator circuit is mamentarily
closed to reset the inL~yLdL~l at the 7.~eg;nn;ng of each clock pulse to the
successive approximation register. The time c~llsL~lL of the illL~y~dLoL is
selected (e~g.r lO0 r~croseconds) and the clock frequency i~s one-half the
bridge excitation fr~quency, The output o~ the c~mp;7rator is applied to
the data input of the SAR thus det~7~m;ning the sett~ng of the swltches in the
D/A circuit (shown in nore detail in Figure 6) and, hence, drives the output
of the D/A circuit towards equality with the bridge output. Such setting
represents the most signif;cant bits of the binary nu~er, the r7~im;71
er~uivalent of which is ~ lLional to the desired ratio E
The above ~de of operation occurs during the time interval Tl
as shown in the timing diagram of Fiy-ure 4. During Tl the inputs to the
band pass amplifier 34 and the low pass Bessel filter 35 of Figure 3 are
grounded to avoid overload.
During the second mode of operation which occurs during intervals
T2 through T5 of Figure 4, the analog output represented by the r~;r7
error signal (Ee) rr~m~7;n;ng after the first mode of operation has been
completed has been ~vllveLLed to a binary output using a dual slope integra-
tor 36.
At the ,~g;nn;ng o time interval T2 the mode switches Sla throughS1d are set to position 2. In such position the r~;rll1r71 error signal is
amplified by ~he prea7nplifier and the band pass amplifier 34 in cascade,
and SYI~L~ S 1~Læ L~L 31 is connec-ted to the outpu-t of the band pass
amplifier. Interval T2
_g
~Z~5651~
is used to allow the band pass amplifier, the synchronous dete-
ctor 31 and the Bessel filter 35 to stabilize. During the
intervals Tl and T2 the dual slope integrator 36 is maintained
at zero ou-tput by opening switch Se and closing reset switch
Sf. At the end of T2 the output of the Bessel filter is a
steady DC voltage proportional to Ee.
At the beginning of T3 switc'nes Se and Sf are
reversed resulting in the output of the dual slope integrator
providing a ramp output signal at a rate and in a direction
depending on the magnitude and phase of the error signal, as
shown in FIG. 4. At the end of T3, switch Se opens and Sc
is set by the control logic to either position 2 or position 3,
depending on the polaricity of the output of the dual slope
integrator. This results in a low lev~l reference AC signal
or minus Er whose magnitude is equal to four times the
magnitude represented by the least significant bit output of
the D/A circuit. This results in a relatively large output of
opposite polarity from the Bessel filter which is allowed to
reach steady state output during time interval T4. At the end
~0 of T4 the switch Se is closed resulting in dual slope inte-
grator providing an output which ramps back towards zero vol--
tage. The time interval Ts is proportional to the residual
error signal and is measured from the end of T4 to the time of
zero crossing as detected by the comparator OP-AM~ 33.
A clock output of a selected frequency (e.g.,
9~304Hz~ is generated by means of an appropriate clock circuit
(such a circuit may utilize a phase-lock loop frequency multi-
plier locked to the 387Hz. bridge e~citation signal, for exam-
ple). Such clock signal is gated to the input of a suitable
binary counter (not shown, during Ts thereby resulting in a
B -lo-
~z~s~
count which is proportional to such time interval. Since
changes in gain of any of the circuits described in Figure 3
affect both Ee and Er equally, they have no real effect on
the final result.
Specific circuitry for the preamplifier 30, the band
pass amplifier 34, the phase sensitive detector 31 and the low
pass Bessel filter 35, as well as the finite time integrator 32
and the dual slope integrator 3~ is shown in the aforesaid
copending application, Serial No. 437,490, filed concurrently
llerewith, and need not be described in greatex detail here7
Referring back to the reference current circuit of
Figure 2, the AC feedback amplifier 18 has a very high open
loop gain (e.g., in a particular embodiment an open loop gain
of 2.5x107) at the operating frequency of the circuit (384Hz.)
and has an amplitude and phase response with frequency which
permit it to operate in a closed loop with 100% feedback with
excellent stability. A suitable reference current IREF
o~ lmA, for example,can be obtained by making EREF equal
to 10 volts (rms) and RREF equal to 10,000 ohms. When
the SPRT is at its maximum value of 125 ohms, for example, the
output of AC feedback amplifier 18 will be 0.125 volts and the
input will be Sx 10-9 volts. Consequently, the open circuit
voltage between the voltage terminal Vl of the reference resis-
tor and ground will differ from the open circuit voltage
be-tween V~ and V2 across RREF by only one part in
5xlO-1. qlhus the refer~nce vol-tage EREF clearly repre-
sents an accurata version of the voltage across the reference
resistance.
The reEerence resistor can be, for example, a 10,000
ohms oil filled metal film on glass type resistor made by
Vishay Corporation of Malvern, Pennsylvania. Such a reference
. ~
_.~
. r~d --11--
S65~)
resistance is temperature controlled to within +0.003C.
Figure 5 shows in more detail how the reference cur-
rent circuit is interconnected. The coaxial connections used
as shown therein considerably reduce errors due to inductive
effects and noise pickup from all external sources. Also, the
method of interconnection was selected so that the capacitance
of the coaxial leads does not affect the operating results of
the circuit since such capacitance is in parallel with a very
low impedance source such as the output of AC feedback
amplifier 18, and is also in parallel with the input of
amplifier 18 which has virtually zero input, and is in parallel
with RT whose resistance is so low that the capacitance of
its coaxial leads does not cause serious quadrature effects~
Dielectric loss in such leads (20 foot length) results in a
shunt resistance o~ approximately 109 ohms with a resulting
error of 0.1~5 ppm for a 25 ohm thermometer. The quadrature
signal resulting from the lead capacitance can be automatically
balanced by a suitable quadrature balance circuit 37 in FIG. 3,
as discussed below.
Accordingly, the reference current circuit will cause
a reference current IREF to flow through the SPRT which is
very accurately given by the ratio of EREF/RREF.
The reference voltage circuit consists of the second
stage transformer winding llC in pa~allel with voltage terminal
Vl of the reference resistor and ground. Since this results in
a small current flowing in Vl, the reference voltage can be
defined as the voltage between the reference junction J and
ground (see FIG. 5). It can be shown that the output voltage
En across any winding Wrl is given by
-12-
~2~S6~
En = EREF n (l+e)
WREF
where WREF is the same as winding lls and e is the frac-
tional ratio error. The fractional ratio can be expressed as
follows:
4R~l ~ RllB~ ~ Z + R~l + RllB
~RREF J ~ Z + RQl ~ RllB + R~2 + RllC J
where R~l and R~2 are lead resistances, RllB and RllC are
winding resistances as shown in FIG. 5. Z is the excitation
impedance of transformer stage Tlb tFIG. 2). For exemp-
lary values of R~l + RllB = 0.75 ohms, R~2 + RllC =
10 loO ohm, and for Z = 2500 ohms resistive (effectively the worst
case) the fractional ratio error e is 2.998 x 10-8. Since this
fractional ratio error is extremely small and is, therefore,
negligible, the aforesaid equation can be rewritten as
follows:
En = EREF Wn
WREF
Thus -the voltage E (i. e. the voltage across winding
llD for any particular setting Sa - FIG. 2) iS equal to the
reference voltage EREF times the turns ratio
Wn/WREF of the winding llC to the reference winding
llBl.
A D/A measurement circuit 15 is shown in FIG. 6 as
comprlsing a two-stage transformer (Tla and Tlb)
having, in the particular version described, six output
windinys Sl through S6 of 32, 16, 8, 4, 2 and 1 turns forming
six bits. ~ second two-stage transformer has two input
windings Wl and W~, ea~ having 128 turns, driven by single
turn output windings on the first two-stage transformer.
-13-
~S6~
Consequently, the output voltage on winding W3 of 64 turns on
the second transformer is one-half the output on winding W4 of
the first two-stage transformer, thus continuing the binary
weighted ratios on the 7 windings of the second two-stage
transformer to form a total o~ 13 binary stages. The states o
switches Sl through 513 in FIG. 6 represent the binar~ value of
the sum oE the 13 voltages across such windings. Thus, the D/A
converters are current summing devices.
Each of the switches can be, for example, implemented
by a pair of field effect transistors (FETs) and as shown in
FIG. 7 each of -the s~itches S~ - S13 can be equivalently ~ormed
of such FET pair. The F~T of each pair is turned O~ or OFF
directly by its associated control line from control logic 18
while the other is driven to the opposite state by inverting
the control line logic as shown in FIG. 7. Appropriate
transistors of the VMOS type can be utilized such as those sold
under the model designation IVN 5001AND made and sold by
Intersil Corporation of Cupertino California.
Thus, in FIG. 6 the switches are appropriately con-
trolled so as to provide a summed voltage Ea across theswitches Sl - S13 which is equal to the bridge output voltage
Eb. The decimal equivalent of the binary number in such
condition then is proportional to the ratio of the D/A ou-tput
voltage Ea to the reference voltage EREF as desired.
~ 5 discussed above, the overall digitization process
is controlled by conventional logic and timing circui-ts. Other
logic operations are controlled by a microprocessor which can
be used to set up the bridge Eor a selected mode of operation,
to start the digitization process, to read and process the data
when the digitization is complete. Processed data can be dis-
played or transmitted to external devices via optional inter-
.
y~
:-~ -14-
~LZ6~56~
faces within the skill of the art. Microprocessors as known
can be controlled by manual inputs to a front panel keypad, for
example, or optionally controlled by external devices through
appropriate interfaces.
Thus, in a particular embodiment the initial succes-
sive approximation measurement provides 13 most significant
bi-ts while the second measurement (dual slope integration)
provide~ 13 least significant bits so as to produce an overall
26-bit bridge output which can be converted -to the resistance
in accordance with the following equation:
RT = RREF ~
5 x 230
where ~REF is the reference resistance and N is the 26-bit
bridge output expressed in decimal form.
Conversion of the resistance to temperature is accom-
plished by the standard IPTS-68 equations for ~PRT operation.
A microprocessor can perform the calculation of resistance to
temperature while the bridge is digitizing.
A quadrature component in the error signal Ee can
cause errors despite the fact that the phase sensitive detector
31 as shown in FIG. 3 theoretically has zero response to quad-
rature. For example, iE such quadrature component is large
enough it can cause an overload in the band pass amplifier or
detector which results in non-linear operation with erroneous
response -to small in-phase signals. For such purpose an auto-
matic quadrature balancing circuit 37 as shown in FIG. 3 can be
used. A particular embodiment of such a circuit is shown in
more detail in FIG. ~ and represents a negative feedback loop
which forces the quadrature component of the input voltage EIN
to zero at -the output without modifying the in-phase com-
ponent.
~c ~ -15-
~2~6~
The input voltage is supplied to the positive input
of an OP-AMP 40 utilizing a tuned circuit 41 which provides a
broadly tuned amplifier which results in an input to a linear
analog multiplier 42. The other input to the multiplier is a
sine wave voltage which is in exact quadrature with the bridge
input voltage which is obtained as a quadrature reference input
from the bridge reference signal.
The output of mul-tiplier 42 will contain a DC com-
ponent ~hich is exactly proportional to the quadrature com-
ponent at the other input to multiplier 42. Such DC componentcauses the integrator circuit 43 to change. The output of the
integrator is an input to a second multiplier 44 (substan-tially
identical to multiplier 42) the other input of which is also
the quadrature sine wave signal. The output of multiplier 44
will be a quadrature voltage proportional to its input. The
negative feed-back current through resistor 45 will exactly
cancel the quadrature
- 15a -
.~.,':'~.
~z~s~s~
current flowing in the input resistor 46 thus reducing the
quadrature component at the output signal EoUT to zero. Such
a circuit can be utilized in FIG. 3 should a quadrature component
be present to cause errors. . 1.
-16-
. , . ~
