Note: Descriptions are shown in the official language in which they were submitted.
1 50,281
MOTOR CONTROL APPARATUS WITH T~UE RMS
NON SINUSOIDAL NEGATIVE SEQUENCE STATOR
CURRENT P~OTECTION MODE
BACKGROU~D OF THE INVENTION
Field of the Invention:
The subject matter of this invention is related
generally to motor controllers and is related more speci-
fically to microprocessor-controlled motor controllers.
Description of the Prior Art:
Motor controllers or motor starters as they are
sometimes called are well known in the art. Generally,
they comprise a switch or ganged switches which are oper-
able to open or close to provide or interrupt current tothe stator windings, for example, of an electric motor.
The opening and closing process is controlled by appro-
priately arranged relay coils and relay contacts in what
is well known in the prior art as a "relay ladder" arranged
in a logical order to properly sequence the starting
and/or stoppiny of the motor.
With the advent of the microprocessor it was
found that part, if not all of the relay logic arrange-
ment, could be replaced by a properly programmed micro-
processor. Such arrangements are shown and described in apaper entitled 'IA Quantative Analysis of Grouped Si~gle-
Phase Induction Motors" published on page 125 of the IEEE
Transactions on Industry Applications, Vol. lA-17 l~o. 2,
March/April 1981 by J. R. Dunki-Jacobs and Robert H. Kerr;
a paper entitled "Thermal Tracking-A Rational Approach to
~$
)'7~ 9
2 50,281
Motor Protection" by D. R. Boothman, E. C. Elgar, R. ~.
Rehder and R. J. Wooddall identified as IEEE Transactions
Paper 274029-5 recommended for presentation at the IEEE
PES Winter Meeting, New York, N. Y., January 27-February
1, 1974; a paper entitled "Microprocessor-Based Universal
Motor Rrotection System" appearing in the IEEE Trans-
actions on Industry Applications, Vol. lA-17 No. 1, January/
February 1981 by E. B. Turner and H. Michael Willey and in
- a descriptive bulletin (41-560(E)) entitled MOTOGARDTM for
motor protection by the Westinghouse Canada Switchgear and
Control Division issued January 1980. A reading of all of
the above will show that certain factors are of importance
when discussing motor starters or motor controllers. One
of the important subjects associated with the Canadian
Westinghouse motor controller, for example, is the utiliza-
tion of what are called the negative and positive sequence
components of the stator winding current during the start-
up phase of the motor to reflect the rotor heating charac-
teristic which, if too high, would lead to a cessation of
the motor starting sequence. None of the aforementioned,
however, provides a way for handling non-sinusoidal stator
currents (non-linear) nor do they utilize the true RMS
value of the stator current. Both of these are important
as many times the stator winding current is non-linear and
the true RMS value of the stator current is more reflec-
tive of the actual heating characteristic associated with
that current.
It would be advantageous, therefore, if micro-
processor-controlled motor starter apparatus could be
found in which non-linear, that is, non-sinusoidal currents
could be safely and reliably utilized during the motor
start-up process. It would be further advantageous if the
true RMS value of the stator current were utilized by the
microprocessor motor controller for determining when and
if the motor starting process should be aborted or con-
tinued.
19
3 50,281
SUMMARY OF THE INVENTION
In accordance with the invention motor control
apparatus is taught which includes a means for energizing
the motor and which further includes a safeguard means
which is interconnected with the motor and with the means
for supplying the current for protecting the motor while
it is being started by interrupting the supply of energy
to the motor when the true RMS value of the negative
se~uence component of the current flowing in the stator
winding exceeds a predetermined value. Alternately, the
aforementioned protection of the motor will occur if the
negative sequence component of a non-linear current flow-
ing in the stator winding exceeds a predetermined value.
50,186; 50,187; 50,200;
4 50,280; 50,281
BRIEF ~ESCRîPTION OF THE DRAWINGS
For a better understanding of the invention,
reference may be had to the preferred embodiment thereof
shown in the accompanying drawings in~.~hich:
S Figure 1 shows a front view of the cabinet of a
microprocessor controlled motor controller;
Fig. 2 shows a circult diagram partiaily in
schematic form and partiall~ in block diagram orm for the
motor control apparatus of Fig. l;
Fig. 3 shows the motor control apparatus of Fig.
1 with the front doors open and with the contactors in
place;
Fig. 4 shows a view similar to Fig. 1 but
slightly offset and with t~e contactors removed;
Fig. 5 shows a representation of the front
control panel for the motor controller of Fig. 1;
~igs. 6A through 6C show a schematic diagram of
the elemonss depicted on th~ front panel of Fig. 5. Some
of the elements are in block diagram or functional repre-
~0 sentation form;
Fig. 7 shows a grapn on which the spesd-tor~le
cur~e -or a mo'or is ~epicted;
Fig. 8 snows a vector diagram or^ the un~vm-
metrical motor currents for an el3ctrical motor;
Fig. 9 shows a simplified thermal equivalen~
circle IOr th- _otor o. a motor;
Fig. 10 snows an analog repr2sentation of the
~i-cu~ts o^ ~ig. 9;
~is. 11 shGws an es!~i~;aient trar.s_er -^unction
represen~a~ior .~or th3 analoa -ep-osen~a~ior of ~ig. 10;
~ ig. 12 shows a reDresen~a_ion or a vector
calculacion o s ~.~.ecrical cu~r3nt componerts for a motor;
Eigs. 13k through 13C ShOiJ ins~antaneous three-
pnase cur.~nts ror a ~otor ~ith a?prooria~e sampling
3~ lnter-~al~ for u_ili7ation ir. a ~icrcoroc3ssor;
Eigs. i~ ~hrougn lD sl.cw a sircuit diagra~l
partiall-~ in sc:-emasic -orm, par~ial'~ n blcck d_agram
~2~7~
50,186; 50,187; 50,200
50,280; 50,281
form and partially in circuit fllnction form for the "RTD
unit" 28 of Eig. 2;
Fig. 15 shows the appropriate lay-out arrange-
ment of E'igs. 14A through 14D;
; Figs. 16A through 16~ show the schematic diagram
partially in circuit diagram '~orm, partially in functional
block form and partially in block diagram form for the
control unit 25 of Fig. 2; and
Fig. 17 shows the apprGprlate lay-out arrange-
ment o Figs. 16A th-ough 16~.
DESCRIPTIOM OF T~E PREFERRED EMBODIMENT
Referring now to the drawings and Figs.
through 6, respectively, a motor controller assembly 10 is
shown. In particular, motor controller assembly 10 may
comprise a cabinet 11 having a hinged door 12 on the front
thereof, a contactor assembly 14 is disposed behind door
12 and has a control handle 16 which is accessible from
the front of the cabinet 11. A second hinged door 1~ is
provided having disposed hereon a start button 20 with an
associated lamp and a stop button 22 with an associated
lamp. In the preferred embodiment of the invention, the
start ~utton 20 is red and the stop button 22 is blacX
Disposed above the previously mentloned start and stop
buttons is a modular front pane} 2~_ which is convenientl
attached to the bac7.~ OI door 18 and protrudes there-
through. ModuIar panel 24 is shown in greater detail ir
Fig. 5 and will be described in greater detail with re-
spect to Fig. 5 nereinafter.
Reerring more speci~ cally ~o Figs. 2, 3 and 4,
~he arrangement of the various control assembly oortions
is shown wi~h the doors 12 and 18 swung open. The con-
tactor assembly la may be rolled into or out of the cab-
inet 11 by way of conv~nient whesls and rails for servic-
ing, replacement or other usefl~l purposes. The contactor
assemDly 14 in ths preferred e~odiment of the invsntion
is interconnected ~ith a three-phase electrical system
(not shown!. Cor~actors Ml, M2 and M3 are interconnec~ed
~2~ 9
50,186; 50,1~37; 50,200;
6 50,280; 50,281
with ap~ro~riate lines in the three-phase electrical
system for oper.ing and closing in ganged relationship
according to appropriate control functions. A multi-wire
flat ribbon cable 28 interconnects front panel 2a with
control unit 26 which is disposed on the upper right-hand
portion of the inner side wall of the cabinet 11. A
resistor temperature detecting (R~D) unit 29 abuts the
control unit 26. RTD unit 29 is interconnected elec-
trically with control unit 26 by way of a three~wire cable
31 (as is best shown in Fig. 4). The RTD unit 29 inter-
connects with a motor MOT (not shown) by way a cable 34.
Various motor field winding regions and bearin~ regions
are monitored by resistance temperature detectors at the
motor and the signals are fed back through wires in cable
34 to the RT~ unit 29 for processing. The control unit 26
coopsr3tes with the contactor assembly 14 to cause the
contactors Ml, M2 and M3 to open or c10s2 in response to
electrical energy supplied to a main coil M by way of
lines or leads in a cable 40. In the preferred embodiment
of the inven~ion, contactor coil M is energized or desner-
gized in accordance wi~h the opening and closing of a
relay contact ~ which is disposed in series with the coil
M and with a source of power which is basically provided
by a bridge ne~-~or'~ 3DG as is best shown in Fig. 2. The
control unit 26 o~erat-s to close a relay contact MK which
in turn drives a relay co l m which is the coil ~hich
controls the previously-mentioned relav contact mM. The
energization of the coil M ^auses the contactors Ml, M2
and M3 to close. Eurther~ore, a feedbac~ relay contact Ma
is provided fo alertln~ the cont~ol unit 26 to the sta~us
of the main line contactors Ml, ~2 and ~3. Current t-ans-
formers 30 are interconnected with the electrical lines
Ll, L2 and L3 of ths previously-mentioned electrical
system for providinq information by way of cable 32 to the
control unit 25. This information is related to the
sta'us o, the slectrical c~rrsnts in the lines Ll, L2 and
L3.
L9
50,186; 50,187; 50,200
7 50,280; 50,281
Referring now specifically to Fig. 4, the inner
portion of the cabinet ll is shown. It will be noted that
the removable contactor assembly 14 of Fig. 3 has been
removed from ca~inet 11. Cabinet 11 shown in the disposi-
tion of Fig. 4 gives a clear view of the physical arrange-
ment of panel 24, control unit 26 and a resistance temper-
ature detector unit 29. Disposed in the upper inside rear
portion of cabinet 11 is a shielded terminal assembly 33
in which the high voltage lines Ll, L2 and L3 are inter-
connectable with appropriate stabs in the roll-out con-
tactor assembly 14. Likewise, in the lower inside rear
portion of the cabinet 11 is shown a contact assembly 35
having stabs 35a therein which are interconnectable with
appropriate connectors in the lower portion of the roll-
out contactor assembly 14. Assembly 35 is interconnectedwith the motor MOT which the controller assembly 10 con-
trols.
Referring now more specifically to Fig. 2, a
diagrammatic representa~ion o' the controller assembly 10
and its associated apparatus is depicted. It will be
noted that the three-phase irput power is provided ~y way
of the electrical lines Ll, L2 and L3 to the three-phase
motor MOT by way of the serially-connected contactors Ml,
M2 and M3. The disconnect points or connector asse.~bliss
33 and 35 ars re~resentativelv snown in Fig. 2. It will
be noted that current transformers 30 monitor electrical
currerts in _he lines Ll, L2 and L3 provlding an inaica-
tion thereof by way o cable 32 to the control unit 26
Furthermoxe, a ground fault transformer GFX also providas
information bt~ way of a cable 32 input to ~hs sontroller
îor ground faul_ 2rotection. Schemati_ally shown
interlinking the motor MOT and the ~TD unit 29 is the
cable 34 in whicn in the preferred embodiment of the
invention, ten sets o~ llnes lnterconnect resistance
temperature detectors in the field regions and bsaring
regions of the motor rqOT to the appropriate input ierminal
~oard 29a ~Eig. a) of -he RTD unit 29. The interconnec-
lZ~7~19 50,186; 50,187i 50,200;
8 50,280; 50,28~
tion of the RTD unit 29 with the control unit 26 by wzy of
three wire cable 31 is also shown in Fig. 2. The control
unit 26 receives llO volt, 60 ~z input power by way of
transformer 36 (also shown in Fig. 3) which i~ connected
across one phase of the lnput power lines. The high side
of the transformer secondary is utilized to be intercon-
nected with one side of various inputs, relay contacts and
switches which are connected to the control unit 26 for
appropriate control functions. A high voltage, three
phase transformer 38 is provided for interconnecting the
three phase lines with the central control unit 26 by way
of cable 42. Shown to the right of the control unit 25
are output relays which are utilized for supplying appro-
priate output information to other control stations aux-
iliary eaui~ment or the like. It will be noted that one
of the inpu' contacts Ior the ccntrcl ur_t ~6 ls d2s~ g-
nated as rcr.~.ally open rala-~ -on~act .~la ar.d is shown on
the le~t G' ~he con~rol uni o. ..130 shown to the left
of cort~ol unit 26 and cor~ected in parallal circuit
relationsnlp with the last-mentior.ed relay contact Ma are
three other relay contacts Ra, Fa and Sa. ~hese represent
the functions rever3e, for~ard and start, respectively.
Although ~ot utilized in the Dr2Isrred e~bodimont of the
invention, these relay contacts may be utilized in other
embodiments of the invention. ~or example, three other
sets of three-pnase contactor asse~blies, such as 1~,
shown in Fig. 3, may 'oe utilized in conjurctlo~ wi~ ths
cont2c~0- ~sse~ y 1~' _o ~erIorm other functions and all
four ~ay oe corsro_ied a~d monisored ~y the same control
unit 25. There may be a motor 1eversing -on~ac~or assGm-
bly, the status Oî which is determined by she control urit
~6 through monitoring the relay contact ~a, a motor for-
ward contactor assembly, that status of whlch is monitored
by the control unil 25 b~ way of relay contact Fa and a
start contactor, the status of which is monitored by the
control unit 25 by way o^ con ro.l. relay SA. ~he start
contac~or ~ay be util-7ed to ~.pose low voltage corditlons
9 50,186; 50,187; 50,200;
9 50,280; 50,281
on motor windings during start-up. Likewise, as is shown
on the lower right of Fig. 2, output contactor drive coil
interconnected with control uni~ relay contacts RK, EK and
SK, respectively, may be provided for causing the appro-
priate opening and closing actions of the contactor assem-
blies associated therewith. The interconnection of a
contactor drive asssmbly such as is shown with respect to
main contactor coil M and its energizing relay contact
coil m may be likewise provided with respect to output
relay contacts RX, EK and SK, respectively. In Fig. 2,
the arrangement of start and stop pushbuttons 20 and 22
with respect to the control unit 26 and the appropriate
power s~pply is shown. It will be noted that to the left
of the control unit 26, other switches and relay contacts
are shown interconnected in circuit relationship with the
control unit 26. Ranging from top to bottom, the fol-
lowing inputs may be found with regard to controller unit
26 of Fig. 2. At the top is shown the RT~ unit 29 which
provides input information by way of cable 31 to the
20 control unit 2~. 3elow that are shown two inputs for 120
volt, 60 Hz power. Below that is shown an emergency stop
button designated E-stop. ~elow -nat is a combination of
the start button 20 connected in series circuit relation-
ship -~ith the stop button 22, both o which are inputted
to a start fo~ard ST/FWD input terminal. Below that is
interconnected the reverse pushbutton REV. 3elow that is
a fast pushbutton E.3ST and a slow pushbutton SLOW. Below
that ar~ three ralay contacts, all of which are normally
open. The firs. is a pre-stop relay contact designated
PRE-STP. Below that is a pre-start normally open rel?y
contact designated PRE-ST and below that is a field loss
normally open relay contact designated ELD LOS. Below
that is a three contact arrangement PO, SC and XTR desig-
nated FLD K's. As mentioned previously, the four
normally-opened contactor status relays may be provided
for the main cont~ctor, ~he reversa contactor, the forward
contactor and the start contactor designatsd Ma, ~a, Fa
,
;~2~ 19
50,186; 50,187; 50,200;
50,280; 50,281
and Sa, respectively. These contacts may be intercon-
nected with the control unit 26 at designations C2, C4, C3
and Cl, respectively, for main, reverse, ~orward and start
functions~ respectively. The designations arbitrarily
relate to coils which may be numerically rearranged pro-
vided consistent arrangements are mad~ with respect to
appropriate out~uts and control functions. On the lowest
portion of control unit 26 is shown the three-wire cable
42 which is interconnected with high voltage transformer
38 for supplying line voltages VCB and VAB, as inputs to
the control unit 26. At the bottom of control unit 26 is
the emergency stop relay ESTOP REL. Shown to the upper
right are another set of inputs for the control unit 26.
Specifically, cable 32 delivers to the control unit 26
information concerning line currents IA, IB, IC and ground
fault current IG. The line currents are provided by way
of current transformers 30 and the ground fault current
information is provided by way of ground fault transformer
GFX. All of the aforementioned constitute inputs for the
control unit 26. It may be monitored information as in
the case OI line currents or control information as in the
case of the start and stop buttons. Ganerally, however,
the information flows from outside of the controller to
the controller. That is, it is a one-way flow of informa-
tion. ~owever, also shown on the right of control unit 26are output ralay contacts which generally provide the
opposite function from that previously discussed. That
is, information flows from the control unit 26 to an
outside device or system. The first of these represents a
relay arrangement including one normally oT~ened relay and
one normally closed relay ~hich is designated PRE-START.
The n~xt is designated PRE-STOP. The next is designated
ALA~M. The next is designated TRI?-RELAY. The nexi is
designated TIME~, and the last two in that set of contacts
are designated AUX1 and AUXZ. Final~y, below that are the
four normally o~ened relav contact arrangement for driving
the contact~rs of the motor control asse.~bly lO. In this
~L2~37~1~
- 50,186; 50,1~7; 50,200;
11 50,280; 50,281
case, they are specifically designated MK, RK, FK and SK
for the main contactor, the reverse contactor, the forward
contactor and the starting contactor, respectively. As
was the case ~ith respect to the similar input arrange-
ments, the latter represent arbitrarily chosen coil desig-
nations C2, C4, C3 and Cl, respectively. In the particu-
lar arrangement shown, with respect to Fig. ~, only main
contactors Ml, M2 and M3 are utilized for the three-phase
system. There is a third device represented by the front
pa~el 24 which is interconnected with the control unit 26
by way of the cable 28. In the case of front panel 24,
information may flow both ways, that is from the panel ~4
to the control unit 26 and from the control unit 26 to th~
front panel 24.
Referring at this time specifically to Figs. 6A,
6B, 6C, laD, 16A, 16B, 16E and 16F, a more deta'led des-
cription of the interconnection between the aIorementioned
input and output devices and the electronic portions of
the control unit 26 is provided. As a general statement,
input information is pro-~ided by way of appropria~e buf-
fers to electronically programmable read-only memories or
to volatile random access memories or to analog sig~al
conditioning devices for analog processing and then even
tual processing in analo~-to-di~ital converters.
Referring now specifically to Fig. 16A, many of
~he previously-described irputs for ~he control unit 26 of
Eig. 2 are designated once again. Eor example, coil input
C2 (designat-d C2 (START) in Fig. 2) is provided to an
isolat ng buf er 3Fl. The isolating buffer includes an
input resistor interconnected with the cathode of a diode
Dl and the anode of a light-emitting diode LE~l. For
purposes of simplicity of illustration, most of the re-
sistive elements shown in the drawings and described with
respect thereto will be designated ~ for purposes of
convenience and simplicity. A photo-sensitive transistor
~TX is interconnec~ed with a +5 volt power supply by way
of a limiting resis.or ar.d has a capacitive element CX
12~ 9
- 50,186; 50,187; 50,200
12 50,280; 50,281
connected thereacross. The collector output of the
photo-transistor PTX is interconnected with an inverting
amplifier Al, and from there is connected to the PAO input
of an electrically programmable read-only memory (EPROM)
EP4. The electrically programmable read-only memory, EP4
is well known in the art and is described in the I~EL~
manual dated September, 1978, designated MCS-85T~ User's
Manual page 5a3 through page S52 in a chapter desia,nated
8755A16,384.bit EPROM with I/O. The latter is incorpor-
ated by reference herein for simplicity and co~venience.When the input signal C2 is high, the light-emitting diode
LEDl is energized, thus providing light to the base of the
photo-transistor PTX, turning that transistor on, thus
dropping the voltaga on the input to the inverting ampli-
fier Al to low value, thus causina the output of theaforementioned amplifier 81 to go high. This is indicated
as sianal MAI and is provided as a single bit input to the
EPROM EP4. How the control unit 26 utilizes this bit of
information will be described hereinaîter with respect to
a fur~her description of the operation of the control unit
26. In a like ashion, input signals C4, C3, Cl, ST/EWD,
REV, SP~RE, FAST, SLOW, FLD LOS, FLD, PRE-ST, PRE-STP,
AUXl, and AUX2, are provided to inputs BF2 through BE15,
respectively, where bufers BF2 through BE15 are essen-
tially the same as buffer BFl described previously. Theoutput signals from the buffers 3F2 through BF15, respec-
tively, are designated RAI, FAI, SAI, ST/FWDl, REVl,
ST/EWD2, FAST, SLOWl, EL, FIELD, PRE-STl, PRE-STPl, and
AUXS (2). ~he latter sianals are ~rovided to inputs PAl
through ?A5, PA7, PBO throuah PB5 of EPROM EP4 and inputs
PAl and PA~ oî EPROM EP3, respectively. EPROM EP3 is
essentially the same as EPROM EP4. he in~ut for terminal
PA6 of EP~OM EP4 is designated ESO and will be described
hereinafter Li'~ewise, the inputs PB6 and PB7 of PROM
EP4 constitute the S.R03E and DATA inputs from the R~D 29
of Eig. 14D and will also be described in greater detail
hereinafter .
7~9 50,186; 50,187; 50,200
13 . 50,280; 50,281
Referring now specifically to Fig. 16B, the
interrelation of the previously-described outputs shown to
the right of control unit 26 in Fig. 2 with respect to
their associated buffers and an electrical programmable
read-only memory EP2 is shown. Coils C2, C3 and C4 are
driven by identical coil drivers CDl, CD2 and CD3, re-
spectively. Coil driver CDl, for example comprises a
field effects transistor FEX connected at the base thereo~
to the output terminal PAO of the electrically program-
mable read-only memory EP2. That output is designated MA.
The collector in the ield efects transistor EXX is
connected to one side of relay coil COi, the other side of
which is connected to a 12 volt pow~r supply +12 VEX. A
standard diode D2 is connected across the coil for pro-
tection. Relay REL, which is driven by coil COi repre-
sents the output relay MK shown in Fig. 2. Coil driver
CD4 is essentially the same as coil drivers CDl through
CD3 except ~hat a complementary normally closed relay REL
is also incorporated. The lat~e_ relay is not shown in
the diagram of Fig. 2, but is provided herewith as an
indication of the -~ersatiiity of the system. When the
ield effects transis~or FEX is turned on, energy is
provided to the coil COi, of su~ficient magritude to close
the relay contact REL, of course, with respect to the coil
driver CD4, relay REL is closed and REL is opened. Coil
drivers CDl througr CD4 are connected to terminals PAO,
PA4, PA2 and PA6 of the electrically programmable read-
only memory EP2 and have their inputs designated as MA,
FA, RA and SA, resDectively. Also shown in Fig. 16B as
functional blocks are output relays ORl through OR7. Each
of the output relays ORl through OR7 has the same config-
uration as the coil driver CD4 described pre~iously. The
outputs of the output relays ORl through OR7 are as ol-
lows. PRE-STA~T, PRE-STO , ALARM, TRIP RELAY, TI~ER,
AUXl, and AUX2, res~ectively. The inputs thereof are
connected to terminals PBO through P37 of the programmaole
- 50,186; 50,187; 50,200;
14 50,280; 50,281
read-only memory EP2, in the following order, respective-
ly: PBO, PBl, PB2, PB3, PB5, PB6 and PB7. Also shown in
Fig. 16B is an electrically programmable read-only ~emory
EPl which is, at this time, provided as a spare, that is,
it performs no function, but is available for expa~ding
the output capacity of the control unit 26. The devices
l~ EPl and EP2 are essentially the same 2S devices ~P3 and
EP4 described with respect to F g. 76~ Terminal PB4 of
the electrically programmable read-only memory EP2 pro-
vides an output E which is utilizable in the emergencystop section EMG STOP of the control unit 26 which will be
described in greater detail with respect to Fig. 16~.
Referring once again to Fig. 16A, it can be
shown that the E-STOP input is provided to a buffer BF16
which is identical to buffers BFl and BF15 described
previously. This signal is provided to a second inverting
amplifier A2 and from the output thereof to the emergency
stop EMG STOP sactlon of the control unit 26 as will be
shown and described hereinaîter with respect to Fig. 16D.
The latter signal is designated E-STOP.
Referring now to Fig. 16E, analog input portions
for the currents ~, IB, IC and IG carried by cable 32 to
the control unit 26 is described. Each of the currents is
provided to an ir.put transformer and from there to a
processor. For purposes of sim~licity of illustration,
processor PROl will be described in detail, it being
understood that processors PR02 and PR03 are identical
with processor PROl. The arrangement of the input trans-
former ITl is obvious and no further discussion will be
made thereabout. The processor PROl comprises resistors
Rl and R2 connected together at one end thereof. The
other end of resistor R2 is connected to one side of a
capacitive element Cl, the other end o reslstive element
Rl is connected to the other slde o~ the capacitive ele-
ment Cl and to ground. The junction bet-~een the resistive
elem2nt R2 and capacitive element Cl is connected to a
resistive element Ra and ~o one ir.put terminal of a fol-
7~1~
50,186; 50,187; 50,20015 50,280; 50,281
lower YL1. The other side of the resistive element R4 is
connected to one side of a resistive element R5 and to the
negative input terminal of an inverting amplifier A~. The
positive terminal of the latter-mentioned amplifier is
grounded. The other terminal of the follower FL1 is
connected by way of resistive element R6 to ground and to
the anode of a diode D3, the cathode of which is connected
to the output of the follower FL1, to the anode of a diode
D4 and to one side of a resistive element R12. The output
of the inverting amplifier A3 is connected to ~he other
side o~ the resistive element ~5 and to one side of a
resistive element Rl4. The cathode of a diode D4 is
connected to the anode ol the diode D3 ard to one side of
a resistive element R13. The other side of resistive
element R12 is connected to the cathode of a diode D5 and
to one side of a resisti-~e element R11, the other side of
which is connected to an input terminal of a comparator
CO1 and to one side of a resistive element R10. ~he other
side of the resistive element R10 is connected to the
anode of the diode DS and to ground. The other input
terminal of the comparator CO1 is connected to one side of
a resistive element R9 and to one side of a resistive
element R8. The other side o~ the resistive element R9 is
grounded, and the other side of the resistive element ~8
is connected to one side of a resistive element R7, to the
output of the comparator CO1, to the multiplaxin~ input
terminal of a multiple~er ~Xl and to the input terminal of
a data flip-flop DFF1. Control terminals S~ for the data
flip-flop DFF1 and the multiplexer MY.l are connected to
sample ar.d hold line. One input of the multiDlexer ~X1 is
connected to the other side of resistive element R13 and
the other input of the multiplexer MX1 is connected to the
other side of the resistive element R14. Both the data
flip-flop, DF~1 and the multiplexer MX1 are grounaed at
appropriate terminals. The data output of the multiplexer
MXl is connected to one side of capacitive element CP and
to one input terminal of a -ange control amplifisr A4
50,186; 50,187; 50,200;
16 50,~80; 50,281
The other input terminal of the range control amplifier A4
is connected to a common junction between resistive ele-
ments R15 and R16. The other side of the resistive ele-
ment R15 is connected back to the output of the ranging
amplifier A4. The othsr side of the resistive element R16
is connected to the collector of a field effect transistor
FEX2, the emitter in which is grounded. The base of the
field effects transformer FEX2 is connected to a grounded
resistor R17 and to the progra~mable controller EP5 at
input terminal P.A5 thereof. The output SGN of the data
flip-flop DFFl is connected to the PA0 terminal of the
device EP5. The output of the ranging amplifier A4 is
connected to one input of a multiplexer MX2 as shown in
Fig. 16G. The corresponding ranging amplifier outputs of
the processors PRO2 and PRO3 for currents IB and IC,
respectively, are connected to input terminals of multi-
plexers MX3 and MX4, respectively, of Fig. 16G. Likewise,
the SG~ output signal from the data ilip-flops EFFl of
processors PRO2 and PRO3 are connected to termin~s PAl
and PA2 of the programmable read-only memory device EP5,
respectively. A sample and hold signal is provided to
each o the pro~essors PRO2 and PRO3 at SH. Referring
once again to input transformer ITl and processor PR01,
when the instan.aneous current IA is providsd to the input
transform2r ITl, it is educed in value to a workable
level and then provided to the processor PR01 where the
resistor Rl converts the current to a voltage which is
proportional to the current. The combination of the
element R2-Cl provides a noise filter. The signal is then
provided concurrently to the inverting amplifier A3 and to
the follower ELl. The outputs of the ~ollower ~nd the
inverting ampliier are the same signal, but 180 out of
phase. ~oth the signals are provided by way of resistors
R13 and R14 respectively to the inputs of the multiplexer
MXl where they are available or sampling. The out~ut of
the follower is also provided to the comparator C01. The
outpu~ of the comparator C01 is a digital signal which is
13~ 9
50,186; 50,187; 50,200;
17 50,280; 50,281
indicative of whether the output of the follower FLl is
positive or negative with respect to the output of the
inverter amplifier. This two-state output signal rom the
comparator CO1 is provided as an input to the data flip-
flop DFF1. If the output of the follower FL1 is posi~ive,
indicative of positive input current IA, the output o~ the
comparator CO1 will be zero because the value of the
voltage between the resistors R8 and R9 is deliberately
made very close to zero. If the output of the comparator
CO1 is low. The output of the data flip flop DFFl will
also be low or close to zero, which is indicati-~e of a
positive current IA. On the other hand, if the current IA
is in the negative part of its cycle, the output of the
follower FLl will be negative, and correspondingly, the
output of the comparator CO1 will be high making the
output of the data ~lip-flop high. A high or di~ital one
at the output of the data follower DFFl is indicative of a
negative input current IA. The data flip-flop DEF1 and
the multiplexer ~X1 are sampled simultaneously by way of
the sample and hold input signal at SH. 30th outputs are
sampled simultaneously. The data flip-flop gives ths sign
of the input current while the ~ultiplexer output gives
the magnitude thereof at the time of sampling. The output
of the multiplexer ~1 is fixed or held for a short period
o time by the cooperative action OI the capacitor CP and
the input impedance of the a~.Dlifier A4. Furthermore, the
other in~ut terminal of the amplifier .~ is interconnected
with resi~tive elemer._s ~15 and R1~ as well as the field
effects ~ransistor FEX2 in such a ~ashion that ~he gain of
the latter-mentioned amplifier can be either ti~es one or
times-fou . If the signal on tke base of the fi~ld ef-
fects t-an3istor FFX2 is low, the gain of the amplifier A4
will be times-four. If, on the cther hand, the signal on
the base of the transistor FEX2 is high, the galn of the
amplifier A4 will be times-one. In essence, the micro~
procsssor (not yet descrlbed) senses the overall magnitude
of the output of the am~lifier A~ at a very earl~ stase
lZ~ 9
50,186; 50,187; 50,200
18 50,~80; 50,281
during the sample and hold cycle and readjusts the gain of
that amplifier A4 by way of an output signal fro~ the
programmable read-only memory EP5 to be either times-four
or times-one depending upon appropriate ranging condi-
tions. The output of the comparator COl is fed to themultiplexing control terminal o~ the multiplexer MXl~ so
that the input at resistive element R13 is read when the
current IA is positive and the input at resistive ele~ent
R14 is read when the current is negative. This provides
only positive output currents at the data output DA of the
multiplexer MXl as a function of the output of the compar-
ator C01. This si~nal is provided as a level to the
previously-described analog to digital converters of Fig
16G. It is relatively easy to see, therefore, that the
outputs of the processors PRO2 and PRO3 for currents IB
and IC, respectively, can be controlled and operated upon
correspondingly. During a predetarmined sampling cycle,
all of the outputs IA, IB and IC from the ranging ampli-
fiers A4 of the processors PROl, PRO2 and PR03 are sup
plied to the mul~iplexers MX2, MX3 and MX4, respectively,
of the A to D circuits, ADl, AD2 and A33, respectively, of
Fig. 16G. This is done at a one-half cycle rate for the
input currents IA, IB, IC so ihat the magnitude of the
positive half cycles and the magnitude for the negative
half cycles are read and introduc2d into the A to D con-
~erters in sequence. With regard to ~he current IG, that
is, ground fault current, it will be noted that an input
transformer IT4 similar to input .ransfor~er ITl is pro-
vided. Furthermore, a peak detector PD utilizing many of
the circuit elements and arrangements described with
respect to the processor PROl is provlded. In this case,
ranging and polarity detection is not necessary. Conse-
quently, a simpliied circuit is utilizsd. The resistive
element Rl which changes current to voltage is utili~ed as
well as the noise suppressing network R2-Cl, the follower
~Ll operates in a mannsr similar to f~llower FLl of pro-
cessor PR01. The capacitive element CP' is utilized to
12~7~1L9
50,186; 50,187; 50,200;
l9 50,280; 50,281
hold the peak of the output signal from the follower FLl.
This signal is prGvided to the lower input terminal of the
~ultiplexer MX4 as shown in Fig. 16G.
Referring now more specifically to Fig. 16F, an
analog voltage detecting and processing network is shown.
In particular, the voltages VCB and VAB are provided by
way oî cable ~2 as is best shown in Fig. 2 to the control
unit 26. The voltage VCB is provided to the input ter-
minals of a voltage tra~sformer network VT1 and the vol-
tage VAB is provided by way of appropriate input terminalsto an identical voltage transormer network VT2. The
voltage transformer networks VTl and VT2 provide center
tap voltages to the processors PR04 and PR05, respective-
ly. With respect to processor PR04, like-identified
portions thereof are similar to li~e-identified portions
descri~ed with respect to the processor PRO1. The opera-
tion is essentially the same as that described with re-
spect to processor PRO1. Noise suppressing circuits NS2
and NS3 are provided where the~ weren't provided with
respect to processor PROl. Furthermore, where is no need
fo. the resistive element R1 which changes current to
voltages as the voltage is already present. .~lso, the
follo~er FL1 is not necessar-~ because the center tap
arrange.~ent of the voltage transIor~er VTl, for example,
provides appropriately orienied voltages to the multi-
plexer MX1. In addition, no ranging is necessary or
desirable in this case and consequentl~, the amplifier A4'
which cooperates with the capacitive ele~ent CP to hold
the signal provided at the data output of the multiplexer
has no _anging control. Once again, the sign of the
polarit~ of the input voltage signal is provided at the
sign output SGN o the processor PR04 while the data
output or magnitude output i9 provided as a level at the
output terminal DA oî processor PROa. Voltage transformer
35 VT2 cooperates with processor PR05 in an identical manner.
Referring once again to Figs. 15E, 16F and 16G
in con~unction, it can be seen that the sign value for the
~Z~7~ 50,186; 50,187; 50,200;
50,280; 50,281
currents IA, IB, IC, the voltages VCB and VAB are provided
to terminals PA0 through PA4 of the electrical program-
mable raad-only memory EP5. The magnitude of the voltage
VCB is provided as the second lnput for the multiplexer
S MX3 and the magnitude of the voltage VAB is provided as
the second input for the multiplexer MX2. It can be seen
that four different reading cycles must be made to gather
all of the necessary information for a complete analog-
to-digital conversion of one ful1 wave of input current
and voltage. In the first reading, all of the positive
input currents IA, IB and IC are provided to the A to D
converters MX2-MX4. In the second reading the associated
positive voltages VAB and VCB, as well as the ground fault
current level IG is provided to the A to D converters
MX2-~X4. In the third reading, all the negative values of
current IA, IB and IC are provided to the A to D con-
verters ~x2-r~x4, and in the last reading, the correspond-
ing values of negative voltage VAB, VCB and the level OI
the ground fault current IG is provided to the A to D
converters ~X2-~X_.
Referring now to Figs. 6~, 5B, 6C, 16E, 16F and
16H as well as Fig. 5, the interrelationship o the front
panel 24 and various elements within the control unit 26
are depicted and described. Switch SWl is connec~ed at
one side thereof IO ground and at the other side thereof
to an appropriate line in caDle 28 and one side of a
resistive eleme~t R, the other side o which is connected
to a five volt power supply. The latter-mentioned wire in
cable 28 is interconrec~ed with terminal PB7 of the elec-
gt~ilcally programmable read-only memory ~P5. When switch
~* is open, the lattar-~entione~ wire has a five volt
value thereon relative to ground which constitutes a
digital one. When switch SW1 is closed, the latter-
mentioned wire is essentially grouaded constitut-ng a
digital zero. Thersfore, a digital one or a digital zsro
exists on ~erminal PB7 deDending upon whether switch SW1
is opened or closed. The electrically programmable _~ad-
12~7~ 50,186; 50,187; 50,200
21 50,280i 50,281
only memory EP5 then cooperates with the microprocessorand other portions of the control unit 26 to utiLize this
information for purposes and in a way which will be des-
cribed hereinafter. Switches SW2 through SW7 are inter-
5 connected by way of wires in cable 28 with terminals PB5,PBl, PB_, PB3, PB2 and PB0 of device EP5. It is to be
noted that switch SW7 is a slngle pole, double throw
switch which can be placed in either the RUN position or
the program position PROGRAM. With respect to Fi~. 5, th~
following legends are indicated in white on the actual
embodiment of the invention "CYCLE", "STEP", "RUN",
"VALUES A'1 "VALUES B" and "VALUES C". On the other hand,
the following legends are printed i~ blue on the actual
embodiments: "T~IP", "ALARM", "TIME", "PROGRAM", "STEP",
"SELECT'I, and "ADJUST". Furthermore, the "FUNCTION"
legend, the "T~IP" legend, the "ALARM" legend, and the
"RESET" legend are also printed in white. If the key-
operated two-position access switch SW7, "RUN", !'PROGRAM"
is placed in the RUN position, the actual reading of
electrical parameters such as voltage, current, etc. can
be displayed for review. ~owever, the setpoints cannot be
changed unless the aorementioned key switch SW7 is moved
into the PROGR~M position. If an "..LARM" or "TRIP" condi-
tion occurs while switch S~7 is ln the run mode, the
review functions are electrically preempted and the dis-
play (FU~ICTION) shows that an A~A~ or a TRIP has occurred
and furthermore, the alarm lamp ~6 flashes. If th- key
swi'_ch SW7 is in the -~'ROGR~M mcde, the motor canrot be
started. On ~he other hand, if tre motor is running, and
the key switch is placed in the PROG~M mode, ~he program-
ming as described hereinaCter will nave no affec~ until
stop condition occurs. The "STEP" push-button will change
the function displayed in the appropriate read-out or
display and hold it until the "STEP" push-but~on is oper-
ated again. As the appropriate function appears in the"FUNCTION" rsadout, values will also appear in combina-
tions of the "A", "B", and "C" readou-s and will remain
~2~
- 50,186; 50,1~7; 50,200;
22 50,280; 50,281
therein until the "STEP" pushbutton is operated again. If
switch SW7 is in the RUN mode, the numerical values shown
in th~ "A", "B" and "C" readouts are actual readings of
the function in question. If, at the same time, the
"S~TPOINT" button SW2 is actuated, the values displayed
for any function in the displays "A", "B", "C" will be the
"TRIP", "ALARM" and "TIME" values previously entered by an
operator. If the "CYCLE" pushbutton SW5 is energized,
whatever is displayed in the "FUNCTION" read-out and the
values "A", "B", "C" will iterate through the entire menu
of possible functions for either monitored values if the
"SETPOINT" switch SW2 has not been actuated or will show
the preset values "TRIP", "ALARM'~, "TIME" if the setpoints
which SW2 has been actuated. If the switch SW7 is placed
in the PROGRAM mode, then utilization of switch SW5 will
cause a selection of values in either the "TRIP" readout,
"AL~ eadout, or "TIME" readout or adjustment by
appropriate manipulation of the up switch SW3 or the down
switch SW6. Utilization of the up switch SW3 will cause
the appropriately displayed value in either "TRIP",
"AL~M", or "TIME" to change by a predetermined increment
in an upward direction. Conversely, utilization of the
down switch SW6 under the same conditlons will cause the
same function to change downwardly by a predetermined
2S amount. Therefore, it can be seen that the "ADJUST" push-
buttons up and down can change the program previously
entered into control unit 26. The "RESET" pushbutton must
be opera~ed to reset the unit and .urn off the "TRIP"
light 9. The ".~LARM" light 46, on the other nand, ex-
tinguishes iî a _unction value drops below an alarm level.It can be seen, therefore, that the f~ont panel 2A pro-
vides two distinct Cunctions, one of programming and one
of monitoring. When the key switch SW7 is in the P~UN
mode, basically a monitoring unction ~akes place. ~ow-
ever, if the key switch is thrown into the P~OGR~M mode,
~hen a programming function can take place by utilizing~he adjust pushbuttons SW3 for "U~" and SW6 for "DO~J".
7019
- 50,186; 50,187; 50,200;
23 50,280; 50,281
5pecific reference to Figs. 6A, 6B and 16~ will
show how the various lights and readouts are interrelated
wlth a volatile random access memory device VR2. Various
input/output terminals of the rar.dom access memory VR2 are
connected with readout or illuminating portions on the
front panel 24. For example, terminals PA0 through PA6 on
device VR2 are interconnected with terminals D0 through D6
on each of the seven read-out devices R01 through R07 of
the front panel 24. Once the information is sequentially
stored in each one of these readout devices, it is dis-
played continuously. The storing of information in the
r adout devices is accomplished by sequentially selecting
a chip snable CE terminal for any one of devices R01
through R07 and then digitally actuating terminals Al and
A0 of the same devices to pick one of the four lamps
therein for loading. Consequently, loading of the lamp
systems is in series, but the readouts appear to display
in parallel. The chip enable terminals are selected by
way of terminals PBO through P36 of the device VR2.
Furthermore, data is loaded into the devices R01 through
R07 when the terminal PA7 is actuated in the device VR2.
This is a white terminal and is designated W. With re-
spect to the LED readouts g4-52, it will be noted that
there are five such readouts. LED readouts a4, a6~ 48, 50
and 52 are connected by way o a resistor R to a five volt
power supply at one end thereof and to a lamp driving
circuit LD at the other end thereo_. .~ppropria.e current
limitins resistors R are connected by wzy of cable 28 to
appropriata terminals on the random access memory VR2.
LED ag is interconnected with output terminal PCg. LED a6
is inte~connec'sd with output terminal PC3. LED a8 is
interconnected with output terminal PC2. LED 50 is int~r-
connected with output termlnal PC1 and LED 52 is in~er-
connected with output terminal PC0. The random ac~ess
memory VR2 is OI the type disclosed in the previcusly-
mentioned INTEL User's ~ar.ual on pages 517-530 and is of
the particular kind designated "8155". Conseauentl~l, 'hat
~ 50,186; 50,187; 50,200;
24 50,280; 50,281
portion of the INTEL Booklat, as previously described, is
incorporated herein by reference.
The actual functions in the menu of functions to
be monitored by the front panel 2~ is listed hereinafter
in Table I. With the "A", "B" and "C" values aligned in
appropriate column~.
TABLE I
METERING
A 3 C
10 Line Voltage X X X
Motor Current - A X X X
Motor Current - % X X X
Ground Current - A X
Winding Temperature - C X
lS Motor Brg. Temperature - C X X
Load Brg. Temperature - C X X
Kilowatts X
Kilovars X
Power Factor - % X
20 Frequency X
Kilowatt Hours X
Run Time X
Operations - Count X
1~7~319
50,186; 50,187; 50,200;
50,280; 50,281
TABLE II
PROGRAMM~.3LE SETPOINTS OR VALUES
TRIP ALARM TIME/'IALUE
Winding Temperatura X X
5 Motor Brg. Temperature X X
Load Brg. Temperature X X
Ground Fault X X X
Inst. Overcurrent X
Locked Rotor Cur X X
10 Long Accelerate X X
Jam ~X X
Underload - Start X
Underload - Run X X
Ultimate Trip X
15 Overvoltage X X
Undervoltage X X
Timer 1 X
Timer 2 X
Timer 3 X
20 Incmplt. Sequence X
A~ti-Backspin
Anti-Recycle X
Start Counts~Hrs. X X
Time Under Volt X
25 Open/Ur~al. Phase X X
Full Load Cur-A X
C. T. Ratio X
P. T. Ratio X
Start-r Class X X
Fur~nar PY~mination o ths control unit 26
especially wi~h regard to Fig. 16C, D, G and H will reveal
further details OI the construction and operation of the
central processing unit 26. ~or -nstance, there is pro-
vided a microprocessor MP which, in a preferred embodimert
of the invention is of the t~pe ~esignated in the pre-
viously-described Intel~ MCS-85~ User's Manual on pages
5-1 th~ough 5-16 thereo~, the latter is incorporated by
re~erence herein or convenience and clarity. The t~r-
minals .~DO through ~37 represent address and data transer
4C o~ points which a~e eight bits wlde. The~y are commonly
designated by the symbol A. It will be noted that t~ese
terminals are in_erconnected with like terminals on the
elec~rically prosrammable read-onl~ memories EPl through
E~5, the volatile r~rdom ac-ess memories ~Rl and ~ and
iZ~7(~19
- 50,186; 50,187; 50,200;
26 50,280; 50,281
three A to D converters ADl, AD2 and AD3 at terminals DBO
through DB7, respectively. These terminals are utilized
to address locations in the variously-mentioned devices
and to transfar data back and forth batween the devices.
It is to be noted that terminals A8, A9 and A10 jointly
designated as "B" are interconnected with the five pre-
viously-described electrically programmable read-only
memories EPl through EP5 for further addressing of these
devices. Terminals IO/M, ALE, and RST OUT are designated
by the reference signal C and they also interconnect at
like locations on the five previously-described electric-
ally programmable read-only memories plus similar loca-
tions on the volatile random access memories VRl and VR2.
The terminals designated RD and WR are collectively desig-
nated ~ and they are routed to the aforementioned elac-
trically programmable read-only memories and the volatile
random access memories. The terminal3 designated All
through Alg are routed to a pair of address decoders DEl
and DE2, respectively. Terminals All, A12 and A13 of the
microprccessor MT are interconn~cted wi'_h terminals AO, Al
and A2 of both oî the decoders DEl and DE2 while the
terminals Al-~ and A15 of the microprocessor MT are con-
nected o terminals E2 and El oî decoder DEl and E3 and
El, respectively, o~ decoder DE2. The output terminals O
through 7 of decoder DEl are designated CSO through CS5
PORT 30-1 and PO~T 30-2, respectiJely, and they are routed
to devices E~2, EP4, EP5, EPl, ~r~l, VR2, ~Dl and AD2,
respectiveiy, îor selecting any one of those devices for
unctional utilization by t:~e microprocessor MP. The
output Lerminals O and 1 o decoder DE2 ars designated
PORT ~0-3 and CE2, respectiv21y, ^or routing to device AD3
and device ~3 (signal CE2), respec~ively. The micro-
processor has interconnected at terminais Xl and X2 a 60
m~z crystal for prov ding a 3 m~z output at the CLKOUT
terminal thereof. There ar_ three terminals shown to the
leît of the micro?rocessor ~ designa~ed RST, RESET and
TRAP. .~11 of ~he functions o ~he microprocessor MP a e
)7l~L9
- 50,186; 50,187; 50,200;
27 50,2~0; 50,281
described in the previously-mentioned Intel~ Manual as
previously described. Three A to D converters designated
AD1, AD2 and AD3, respectively, are shown. Each of these
devices is interconnected with a multiplexer MX2, MX3 and
S MX4, respectively, at the VIN+ input terminals of the
respective A to D devices. The multiplexers are inter-
connected as was described previously and the multiplex
selection is controlled by the PC3 output terminal of the
volatile random access memory VRl of Fig. 16H. Similarly,
the sample and hold signal so well utilized with respect
to the devices of Fig. 16E at the input terminals SH of
the same devices is generated at the output terminal PC4
of the memory VR1 of Fig. 16H. The top input terminals of
the multiplexers MX2, MX3 and ~Xa are levels IA, IB and
IC, respectively, as was described previously. The bottom
input .erminals of the same mentioned multiplexers are
voltages VAB, VAC and ground fault current IG, respective-
ly. In the manner previously described, these latter
signals are sant 'o the appropriate A to D converters
where levels representati-~7e thereoî are converted at the
terminals DB0 ~hrough DB7 in e~ch case to digital vaiues
for subseauent routing to the microprocessor MP and other
appropriate memory locations the-eaîter -~ith appropriate
processing in the irterim. The various A to D converters
ADl through .~D3 are selected by the previously-described
signals PORT 30~ ORT 30-2, and PORT 40-3, respectively,
and b~ the read-write signals d~signated D with respect to
the multiplexer MP in Fig. loC. The A to D converters
therefore provide tke valuabl2 -u..ction of converting the
analog si~rals sAown entering tke cont.ol unlt 25 of Fig.
2 (the current signals I~, IB, IC and IG, ar~ the voltage
signals VCB and VAB) into digital values for appropriata
utilization. It will be recalled with respect to device
VR2 that it is interconnected ~ith appropriate front panel
locations on ~igs. 6A and 6B. The non-volat-le read-onl~
memorv NVR is connec~ed at ou~put terminals D0 through D7
to terminals PAO through P7 of devica VRl. Li~ewise,
19
50,186; 50,187; 50,200;
~8 50,280; ~0,~81
terminals AOl through A5 of device NVR are connected to
terminals PBl through PB5 of device VRl. Finally, ter-
minals Cl, C2 and CLK of the device NVR are interconnected
with terminals PB6, PB7 and PCO of VRl. The terminals PCl
and PC2 of VRl are connected to the terminals AO and Al in
the devices ROl through R07 in Fig. 6B for selecting which
of the four indicating lamps are to be loaded with data in
each case in those latter devices. The terminal desig-
nated T/OUT~ in device VRl is ir.terconnected with terminal
T/IN in device VR2 and with the previously-described input
terminal RST 7.5 of the microprocessor MP~ The signal
T/OUT/ of device VRl generates a pulse to the aforemen~
tioned terminal T/IN and to ~he terminal RST 7 . 5 of the
microprocessor MP for initiating a 5.56 ms cycle in the
microprocessor.
The 3 megahertz clocX output signal CLK OUT from
the device MP is routed to the clock input terminals of
the electrically programmable r-ad-only memories EPl
through EP5 and to a divids by 8 co~nter designated DV
where lt is provided to tne clocX input terminals of the A
to D devices .~Dl throush AD3 'or causing those devices to
sample input data from the previously-described multi-
plexers ~2 through M~a at a slower rate. Generally, thQ
rate is such that all of the appropriate parameters are
sampled and digi~ized three ti~es p2r cycle within a '2
line cycle time ^rame. The latt-r-~entioned divida ~y
eight signal is also provided .o the terminal T~IN of the
device VRl for utili7ation. ~ere it is utilized at the
previousl~-desc_i~ed ~,e minals PC3 and pca for determining
sample and hold rate and multiplexer rate for the devices
of Fig. 16F and the multiolexers o~ ~ig. 16G.
Referring orce agair to Fig. 163, the ~OWER ON
RESET, DE,~ ~AN and EMERGENC~ STOP, the output terminal of
the NAl~ gate ~Al as connected to the RSTl input terminal
of the 'lip flop EFl and to the RST2 input terminal of the
flip flo~ FF2. The Ql out?ut termiral of ~he fliD flop
FFl is designated ~SO. It is con..ec-ed to the ~A6 input
19
- 50,186; 50,187; 50,200;
29 50,280; 50,281
terminal of the electrical~y programmable read-only memory
device EP4 of Fig. 16A. The output terminal Q2 of the
flip flop FF2 is connected to the field effects trans-
former EEX3. A relay coil COES is connected at one end
thereof to an appropriate point on the field effects
transformer FEX3 and at the other end thereof to a 12 volt
power supply 12 VEX. The latter relay coil is protected
by a suitable diode ar.d drives the emergency stop relay,
E-STOP REL, also shown in Fig. 2. The signal E is con-
nected to one input terminal of the NAND gate NAl and thesignal E-STOP is connected to the other input terminal
thereof. The signal RESET is connected to one input
terminal of the NAND gate NA2 and the signal TRIP-RESET is
connected to the other input terminal thereof. The signal
E comes from the PB~ terminal of the electrically program-
mable read-only memory E 2 of Fig. 16B. ~he signal E-STOP
comes from the output amplifier A2 of Fig. 16A. All of
the inputs E, E-STOP, RESET, and TRIP-RESET when changed
from a digital high to a digital low which is indicative
of a need to energize E-STOP RE~, will cause a digital one
to appear on the output ter~inals of either of the N~D
gates MAl or NA2. Either or both of these slgnals will
cause the Q2 output terminal or the flip flop FF2 to go
high, thus ^ausing the 'ield ef~ects transistor FEX3 to go
low, thus energizing the coil COES, thus -ppropriately
closing the E-STOP REL contact. Fur_hermore, the presence
of a signal that goes from zero to high on the output of
NAND gate NA2 ~-ill cause the Ql out?ut of the flip rlap
FFl to go high, thus causing output signal ESO to be high.
Conversaly, in the presence of a high on the output of a
NAND gate NAl will cause the reset tern.inal RSTl of the
flip flop FFl to go high thus causir~ the output Ql to go
low, thus causing the signal ESO ~o go low.
As is also shown in Fig. 16D, a POWE~ ON RESET
^ircuit and a DE~ ~N circuit are available for use by
the microprocessor ~P. The RES~T sigr.zl is provided to
the RrSET input of Ihe microprocessor and to tha CSl input
12~7~19
- - 50,186; 50,187; 50,200;
50,280; 50,281
terminal of the non-volatile read-only memor~ ~VR of Fig.
16H. The RESET signal is designed to be produced when
either the 12 volt power supply or the 5 volt power supply
which is utilized for empowering ~any oî the elements of
central processor unit 26 are low. A comparator C03 has
both the 5 volt and 12 volt po~er sup~ly connected thereto
through the diodes D7 and D8 to provide operation from
either of the power supplies. A precision 2.5 Zener diode
PSZ is connected to the negative input of the comparator
C03. The positive input of the comparator C03 has a 2.7
voltage reference established thereat which is derived
from the 5 volt power supply. If the 5 volt power supply
falls below 4.56 volts, which is an indication of a prob-
lem in the power supply, the output of the comparator C03
pulls the I input of the next comparator C04 low. There
is a 15 ms ti~e constant associated with this change of
state. ~he time constant is a function of a capacitor
~PS1 and RPSl working as a charging network. Furtkermore,
comparator C04 compares the latter-mentioned signal with
the 2.5 -~olt reference signal once again. If the 5 volt
power supply is low, the ou.~ut o the comparator COA will
go low from a high impedance state to produce the afore-
mentioned RESET signal. This RESET signal is used to
initiate several responses. The signal is used tc chip
select inputs or. ~ to prevent writing or reading from
this component du-ins the reset phase. The RESET is used
ln the emergency stop relaying circuit EM~ STOP and the
RESET signal is sent to the microprocessor MP to set the
internal program counter thereof to zero to start the
program from the beginning as will De dsscribed herein
after. The RESET signal is also used to generate what is
called a DE~D ~Y signal to provide input to the TRAP
input oî the microprocessor MP. To accomplish this, the
RESET signal is applied to the positive inp~t of a com-
parator COS to produce a low signal at the output thereofduring a RESET condition. The la_ter output is wire OR-ed
with the output from a comparator C05. ~is somparator
~L2~0i1S~
- 50,186; 50,187; 50,200
31 50,280; 50,2~31
compar~s the sample and hold signal which was described
previously with the 2.5 voltage reference. The sample and
hold ~ignal is ideally a pulse which is produced every
5.56 ms. This pulse is used for sampling o~ data and is a
good indication whether the microprocessor is working
intelligently or not. The a~sence of this signal in-
dicates that the microprocessor is likely not to be work-
ing intelligently. The output of comparator C06 has a
time constant of approximately 20 ms associated with it
which is a function of the capacitance of capacitive
element CDl and interconnected resistance. This latter
output is compared to the 2.5 volt signal at the rompar-
ator C07. This output is wire OR-ed with the output of
comparator coa which compares ~he outpu~ signal from C06
with an eight volt reference. In the final stage of the
DEAD MAN, the output of the comparator CO9 will be low if
there has been a loss of intelligence. If there is no
loss of intelligence in the microprocesscr MP, the voltage
at the negative input of comparator CO9 will be mors
~0 positive tnan t~e voltage at the ?osltive input thereof
and the output of CO9 ~ill be zero. ~his means that the
output o the comparator CO9 will become a free-running or
astable multi-vibra~or as a function of the capacitive
element CP3 and the resistance ~Dl. If ~he input to the
negative terminal of comparator CO9 is less positive than
the voltage at the posltive terminal thereof, the out?uts
oî the comparator CO9 will stay at a high impedance. This
allows capacitive element CDl to charge and increase the
voltage at the negative inpul terminal to make it mors
positive thar 'hg ?ositive input terminal and thus ca~se
the compara~or CO9 to trigger. The time needed for cap-
aci~ive element CDl to charge and discharge determines the
freauency of the mul~ivibrator. It is a?proximately eyual
to t-~o times ~he resistance ~Dl times the capacitance OI
CDl. The time is ideally 94 ms in the preferrsd embodi~
ment of the inven~ion. This latter signal is recognized
on the T~}.P input of the microprocessor MP ~y its rising
- 50,186; 50,187; 50,200;
32 50,280; 50,281
edge an~ high level. There is a 50% duty cycle with this
signal which means that tha microprocessor has approxi-
mately 50 ms to correct its errors during each duty cycle.
Referring now to Eigs. 14A through 14B, the
resistance temperature detector circuit or resistance
temperature detector (RTD) unit 29 of Fig. 2 is shown. It
is to be noted that the resistor temperature detector
devices are remotely located at the regions of the bear-
ings and field windings for example of the motor MOT. ~n
exemplar~ ~esistance temperature device RTDD is shown inthe upper left of Fig. 14A. It comprises a three-terminal
network which is interconnected with three appropriate
terminals in the unit 29 by way of cable 34. The ou~put
from the resistance temperature device unit 29 is inter-
connected with the control unit 26 by way of the cabla 31shown in the upper right of Fig. l~D. Its interconnection
with the control unit 26 is also shown in Fig. 16A. The
STROBE pulse is essentially a clock pulse which updates or
actuates the electrically prog.ammable read-only memory
Epa for acceptance of serial data on the DATA line shown
in Eig. 16A at in~ut terminal ~B7 of the latter-mentioned
device E~''. Tnere is p~ovided, as is best shown in Fig.
laB a power circuit designated ?SRT. The power circuit
PS~T is fed by way Gf transformer Xl with 120 volts AC.
The secondary of transformer Xl is center tap grounded to
provide bo~h posi_ive and negative power supply voltages.
A series or four diodes DiO is interconnected as shown in
Eig. 14~ to pro-~ide a set of output terminals which are
positive and a set of out~ut termir.als which are negative.
Connected ~o ~he u?permost in tke latter-mentioned diodes
is a vol~age regulator unit VP.l which utilizes a Zener
diode ZR~l and two capacitive elements CDl and CD2 to
provide a +5 volt output level wi~h respect t~ ground. An
unregulated positive output voltage ~V is cor.nected be-
tween the aforementioned diode and he volta~e regulatorVRl. In a liXe mar.ner, connected to the botto~ost dioda
is a com~lemer.tary negative unregulated voltage terminal
- 50,186; 50,187; 50,200;
33 50,280; 50,281
-V. Correspondingly, a reg~lated -5 volt power supply
terminal is interconnected with the negative unregulated
terminal -V by way of a transistor QDl and resistive
elements RDl, RD2 and capacitive elements CD3 and CD4.
S Finally, a resistive element RD3 is interconnected with
the anode of a Zener diode ZRD3, the cathode of which is
connected to ground. The arrangement of the resistive
element RD3 and the Zener diode element ZRD3 with respect
to the negative unregulated power suppiy terminal -V i~
such as to ~roduce a voltage -VPROT which is uti].i~ed in
other portions of the RTD unit 29. ml he regulated power
supply voltage, ~5 volts, ard the unregulated voltage -V,
two noise suppression networks NSRl and NSR2 utilizing
resistors and capacitors interconnected with the negative
and positive input terminals of an amplifier ARl ar~
utilized to create a cloc~ circuit. The output of the
amplifier ARl is cor,nected to one end of a resistive
element RDl and to one end of a capacitive element CD5.
The capacitivs element is fed back ~o the positive input
terminal of the am~lifier ~.Rl b-J way of a resistor. The
oth2r side of ths -esistive elsment RDA~ is connected to
the regulated +5 power supply. The output of the ampli-
fier ARl is known as the CL~CK signal and operates at 120
Hz in the ~reIerred em~odiment oî the invention. Refer-
2S ring speci^ically, once again to Fig. l~A, an input cir-
cuit for the reslstor temperatu-s detective devices RTDD
is s~o~n. The latter-mentioned circuit comprises one
input t6rmlnal which is connected to the iunction between
a resistive element RD8 and other resistive slement RDg
and a ca~acitive element CD~. The other side of the
resistiv6 element RD8 is connected to the negative voltage
~VPROT by way of a diode, is conr.ected to ground by way of
diode and is connected to ths ~ollector of a transistor
Q33, th~ anode of whlch is connsctsd to a capacitive
element CD7 and a resistive ele.ment RD7. The other side
of the resistive element ~D7 s connected to the negative
volt~ge -V. The other side of the capac tive element is
~ 50,185; 50,187; 50,200
34 50,280; 50,281
connected to the base of the aforementioned transistor QD3
and to the collector of a transistor QD2 and to the minus
voltage supply (-V) through a diode and a resistive ele-
ment RD6. Resistive elements RD5 and CD6 are connected
together and at the common junction thereof to the emitter
of the aforementioned transistor QD2. The other side of
the capacitive element CD6 is connected to the base of the
transistor QD2 and to ground. The other side of the
resistive element RD9 is conr.ec~ed to the negative input
terminal of an amplifier AR2, to one side of the resistive
element RDll and to one side of a resistor element RD12,
the other side of which is connected bacX to the output of
the ampliier AR2. Resistive element RDll is connected to
the wiper of a potentiometer RD13, one side of which is
grounded and the other side c which is connected to a
voltage reference signal VRE~. A resistive element RD10
is connect2d to the positive input of ~he amplifier AR2.
Capacitive element CD10 is cor~ected to the latter-
mentioned positive input and capacitive element CD9 is
connected to the other side of ~he resistive element R~10
and to a second input terminal from the resistance de-
tector devices RTDD. A third input terminal from the
resistance devices RTDD is connected to ground or system
common. The output of the ampliier AR2 is designated
2~ ~7RTDO. The outputs oî similar input circuits INC2 through
INC10 are designated VRTDl through VRTD9, respectively
These are supplied as parallel inputs to multiplsx2rs
Mi~RTDl and MXRTD2. The latter-mentioned multiplexers may
be of the t~e known in the art as "CD4051". Signals
VXTDO through ~IRTD7 are conr.ected to input ter~ninals 13,
14, 15, 12, 1, 5~ 2 and 4, respec~ively, of the multi-
olexer MNRTDl. The signals VRTD8 and VRTD9 are connected
to the input terminals 13 and 14 of multiplexer MXRTD2
~ he outputs o the latter-mentioned multiplexers are
designated INH, A, B, C, and the signals thereat are
called A33, ABO, A31 and r.B2, respectively. Eurthermore,
there is a serial data output terminals CONO/I upon which
12~7~9
~ 50,186; 50,187; 50,200
50,280; 50,281
the serial data signal S DATA 0 can be found. The multi-
plexers MXRTDl and MXRTD2 take the parallel input data
from the signals VRTDO through VRTD9 and convert the~ to
serial output signals for utili~ation at the input ter-
minal INHI of an A to D converter .~D4 which may ~e o thetype known in the art as the "ICL7109".
There is also provided as shown in Fig. 14B a
voltage reference circuit VRRT which is connected as input
to the latter-mentioned transistor QD2. The circuit
employing the latter-mentioned transistor QD2 is a con-
stant current-producing circuit in which the current IK is
provided. A portion of this constant current is utilized
by the transistor QD4 to establish a reference to be
utilized in conjunction with an amplifier AR3 and resis-
tive device~ RD13 through RD17. One of the voltage output
signals is designated VREF and another voltage output
signal is designated ADREF. The ~atter signal is supplied
to the previously-mentioned A to D converter AD4 for
empowering the same.
Table I shows the relationship between the re-
sistive elements RD9, RDll, RD12 and RD13 and certainly
commercially-available 2TD ty~es.
RTD TYPE
RESISTOR COPPER PLATINUM NICKEL
RD9 6.19K 27.4~ 43.2K
RDll 6.19K 33.2K 75K
RD13 200K 2K lK
RD12 301K 133X 100K
By utilizing the appropriate values for the resistors in
guestion, either the copper, platinum or nickel RTD types
can be utilized.
Referring specifically to Fig. 14C and 14D,
there is shown the previously-described A to D converter
AD4. Its serial data input is designated I~l as des-
cribed pr~viously. Its outputs are designated 33 throughB12, respectively. Termir.als B3 through B10 are connected
with a da_a input device DATl of th.s kind known in the ar
12~7~9
- 50,186; 50,187; 50,200
36 50,280; 50,281
as the "CD O1~". Below that is a second similar device
designated DATA 2 in which the lines B11 and B12 are
interconnected and which are also connected to output
signals PBO and PB1 from parity checker devices PC1 and
PC2 which will be described later hereinafter. Input PB1
is to the fourth input terminal (4) of the latter-
mentioned device and input PBO is to the fifth input
terminal (5) of the latter-mentioned device. Connected to
input terminals 13, 14, 15 and 1 of the latter-~entioned
devices are signals AB0, AB1, AB2 and AB3, which will be
described more fully hereinafter. There is provided a
timing device TMG which has outputs Q2, Q3, Q4 and Q5,
respectively, which is essentially a counter oî the type
known as "CD4024". The CLK input of this latter device i5
connected to the CLOCX output of the previously-described
amplifier ARl. The frequencies ?roduced at the outputs
Q2, Q3, Q4 and Q5 are utilized to Drovide clock inputs for
r~m~i ni ng portions of the circuit. There is provided a
second counter designated "MC14510" and identified as
COUNT 1 which has its CLK input connected to the afore-
mentioned Q5 terminal o^ the timer TMG by way of an in-
verter AR . There is also provided an RTDS select device
which can pick anv of the ten of the resistance terminal
devices for display or sample. This device is a BED
encoded switch having output terminals 8 a 2 1 which are
interconnected with the Pl through P~ inputs of the count-
er COUNT 1 and with the A through D inputs of an RTD lamp
driver RTLD. The lamp driver may be of the kind Xnown as
"MC14511". It provides outputs at terminals A through G
thereof to ~ read-out device RTRO so that the resistance
terminal device chosen on the selecto_ RTDS will be dis-
played on the read-out dsvice RTRO and will provide inputs
to the counter COUNT 1. A switch SRT, when in the closed
position, enables 'he selection of a specific RTD device
3~ If the switch S~T is in the oper. position, binary outputs
Q1 through Q4 or the counter iterate automatically from
one to ten for setting up appropriate addresses. The
120~9 50,186; 50, 187; 50,200;
37 50,280; 50,281
latter-mentioned address lines ABO through AB3 are inter-
connected as input line to the second parity checker PC2
at the inputs D5 through D8 thereof and at the second data
output device DAT2 at the aforementioned input terminals
13, 14, 15 and 1, respectively, thereof. Further, the two
multiplexers MXRTDl and MXRTD2 receive the latter-
mentioned data as mentioned previously at their input
terminals A, B, C and INH, thereof. The most significant
output digits rom the A to D converter AD_ are found on
terminals B10, 11 and 12. These are supplied to a read-
out device RODI which illuminate as a function of the
digital values on these latter three terminals.
In operation, the aforementioned current source
provided by transistor QD2 that is current IK, is approxi-
ma~ely 5 milliamps. It flows through the resistive ele-
ment RMO by way of transistor QR3 and resistive device RD8
to the return or ground circuit. The device of Figs. l A
through 14D constitute what is best described as a paral-
lel to serial transmission circuit. Once every 260 ms, a
new sequential RTD output is selected by the counter COUNT
1. That output is digitized by the A to D converter .~D~
and the digitized data plus "even" parity in'ormation and
the RTD address code is stored in parallel to serial shift
registers DAT 1 and DAT 2 as described previously. During
the A to D conversion o~ the next RTD output, the previous
sixteen bits of RTD output information is serially trans-
mitted at a rate o. 120 bits per second. The date is sent
in the following se~ence: AB3, .3B~, ABl, ABO, PBl, PBO,
B1~, Bll, B10, B9, B8, B7, B6, 35, B and B3. All data is
sent most significant bit ~irst. The previously ~escribsd
encoded switch ~TDS, the readout RTDO and the switch SRT
are utilized to override the automatic sampling of the RTD
outputs mainly for test purposes. Known resistors can be
applied to a selscted RTD input which will cause bit
transitions of t~e A to D conv~rters thres most signifi-
cant bits. The status o these bits can be in~icated by
the three L_Ds o~ the --ad-out device ~ODI, thus circui'
operation and calibration can be veri-led.
- ~Z~ 9 50,186; 50,1~7; 50,200;
38 50,280; 50,281
It will be noted that in the upper portion of
Eigs. 14C and l~D, there are a collection OI AND gates,
NA~ gates, inverters and dxivers. All of the above are
interconnected with the timing device TMG or the CLOCK
pulse or the A to D converter AD4 or the data output Q8 on
device DAT2. As was mentioned previously, outputs Q2
through Q5 are frequency divided pulsed outputs which are
related to the CLOCK input signal. If the CLOCK pulse is
at a rate of 120 Hz, Q2 will be at 30 Hz, Q3 will be at lS
Hz. Q4 will be at 7.5 Hz and 05 will be at 3.75 Hz. The
CLOCK pulse is provided as an output to the strobe driver
STDR for transmission to the control unit 26. The NAND
gate RN2 will pass the CLOCR pulse unless it is disabled~
In a like manner, the NAND gates ~N5 and RN4 pass the data
from the tenminal Q8 of the data flip flop DAT2 unless
either or both of the latter-mentioned NAND gates RN5 or
RN4 are also disabled. Furthermore, the output of the
NAND gate ~N4 may be disabled if the output of the NAND
gate RN3 is zero. The outpu- of the NAND gate RN3 will be
0 if both of its inputs are one. It can be seen that one
of its inputs is tied back to T5 volt power supply and
therefore is forced to be one, so when the other input of
device ~N3 is one, the ou~put _hereof is zero, thus dis-
abling the data transmitting N~D gate RN4. It can be
seen that the Q5 output terminal of the timer TMG is
provided as an input to both of the latter-mentioned NAND
gates ~N2 and RN3 for enabling and disabling purposes.
The presence of the inverter RI2 means that the disabling
which occurs with respect to the NA~D gate RN2 is 180
phase shiIted f~om the disabling which is associated with
the NA~ gare ~N3. This is because a particular mode of
cooperation between the various NAND gates RN2, ~N3 and
the other devices which they control. The net effect is
~hat at a souare wave rate of 3.75 Hz, both the CLOCK
pulse ~STROBE) and the data outputs (DATA~ are prevented
from being transmitted oy way of cable 31 to the control
unit 25. It can be seen that this very same Q5 signal is
:12~7~
~ 50,186; 50,187; 50,200;
39 50,280; 50,281
provided by way of the sample line to the serial/parallel
inputs SER/PAR of the data transmission devices DATl and
DAT2. When the SAMPLE signal is a digital one, then data
i5 shifted out of the data device DAT1 into the data
device DAT2 and follows the DAT2s data out of the terminal
Q8 into the data line DATA of cable 31 by way of NAND
gates ~15, RN4 and under the control of a NAND gate RN3.
When a serial output is desired, the SAMPLE signal will be
one and the device RN3 will be such that the output of
device RN4 will not be disabled. Of course at this time,
NAND gate RN2 is also in a non-disabled disposition so
that the strobe information leaves concurrently from the
STROBE output of the strobe's driver STDR. When the
output Q5 is zero, the output of the AND gat~ RA4 or the
SAMPLE signal is zero thus causing the devices DATl and
DAT2 to be in the parallel input mode so that data is
shifted in to ~hese devices from the A to D converter AD4.
It can be seen that the devices o Figs. 14C and 14D
alternate between a serial data output mode and a parallel
data input mode as a function o' the frequency 3.75 Hz
signal found on the 05 outpu- terminal of the timing
device TMG. It is to be understood that all of the other
controls are synchronized with 'his frequency or some
multiple thereof. Note that data transmission N~ND gate
RN5 can be disabled rom the output of NAND gate RN6.
Furthermore, data transmission NAND gate ~N4 can be dis-
abled from the output of NAND gate RN7. NAND gate RN6 is
interconnected with the POL output of the A to D co~verter
AD4. Likewise, an input terminal of an NA~D gate RN7 is
cornected with the OR output of the A to D converter .~D4.
The POL output of the A to D converter AD4 indicates that
the sum total of the digital data being shifted out is
negative or positive (thus POL). The OR output indicates
that the sum total of the digital data being transîerred
out of the A to D converter at any instant of time is
either ~ithin range or over-range (thus OR). If the data
is found to be negative or over-range or both by the A to
19
50,186; 50,187; 50,200;
50,280; 50,281
D converter, the data is presumed to be invalid and the
data transmission will be prevented by the interaction of
the NAND gates RN5 through RN7. These conditions may
occur, for example, if the RTDD device has failed. It
will be noted that the three kinds of information which
are shifted out of the data devices DATl and DAT2 have to
do with the value of the temperature in the motor windings
or bearings as a function of the ~TD device, parity and an
address. The address information AB0 through AB3 tells
which particular RTD device is being sampled and the data
information B3 through B10 is a digital representation of
the actual value of the temperature. The parity informa-
tion is such that the inputs to the device DATl can be
even or odd parity. While the parallel inputs to the
device DAT2 must be odd parity. The parity information is
sent along cable 31 along with the address and data infor-
mation so that when the microprocessor MP of Fig. 16C
ma~es its own calculation on parity, it can compare it
with the parity information provided to see if they are
the same. If they are not the same, then the micropro-
cessor ma~l decide that the data is defective because of an
error in transmission due to noise or otherwise.
Referring now to Figs. 7 ~hrough 13, the util-
ization of positive and negative sequence currents with
respect to tke apparatus oî _he present invention is
explained. It is .o be realized that a three-phase elec-
trical motor produces a rotating magnetic field across its
air gap by '~he combination of time and space displacement
of the motor currents and stator field windings, respec-
tively. If the motor currents are equal in amplitude and120 displ~ced and if the distribution of the ~hree-phase
windings in ~h9 stator slots is proper, the resulting
rotating magnetic field has a sinusoidal wave shape and
affixed rotational speed and direction. The rotational
field is coupled to the rotor windings or bars in the case
of a squirrel cage motor which r~sults in induced rotor
currents which produce a field which bucks the field
7~9`
~ 50,186; 50,187; 50,200
41 50,~80; 50,281
generated by the stator. The force produced by the reac-
tion of the air gap flux and the rotor currents is in a
direction which tends to make the rotor spin in the same
direction as the rotating field, but at a speed which is
typically 3 to 5% slower. The resulting spead tor~ue
curve for a motor as shown in Fig. 7, the negative speed
range corresponds to a dynamic braking situation which
exists -i~ the field is spending in a direction opposite
from that CI the rotating field. If the three line vol-
tages of the motor are not balanced, the resulting motorcurrents also wiL1 not be balanced. A convenient and
mathematical technique for analyzlng such a situation is
based on the use of symmetrical components. The unsvm-
metrical motor currents shown in Fig. 8 is based on the
use of symmetrical components. The unsymmetrical motor
currents shown in Fig. 8 as vectors IA, IB, I~ are repre-
sented by three sets of symmetrical vectors called posi-
tive, negative and zero sequence components. Equations
1, 2 and 3 below show a vector addition.
-A = Io + Il + I2 (1~
IB Io + a Il + aI2 (2)
C Io + aIl + a I2 (3
The positive and zero sequence of components vectors are
assumed to rotat- in the same direction as the original
2S vectors while the negative sequence components rotate in
the opposite directior.. The e~fect oî even a small nega-
tive sequence component on rotor temperature can be sig-
nificant as this produces a dynamic braking torque on the
rotor corresponding to a large induced 120 Hz rotor cur-
rent, while positive sequence components is -equir2d to
12~ 19
50,186; 50,187; 50,200
42 50,280; 50,281
supply both the motor output toraue or load torque and at
torque to balance the braking torque. The motor control-
ler assembly 10 of Fig. 1, for example, should ideally
provide rotor overtemperature protection by prediction.
This prediction should be based on measurable quantities,
such as stator currents and stator ~inding temperatures.
The measurement of stator current amplitudes is not suf-
ficient for motor protection calculations. Both amplitude
phase and wave shape must be utilized. ~urther, the motor
current information mus~ be used with stator temperature
information in combination if the rotor temperature is to
be limited. The present motor controller protects the
rotor of the ~chine that protects based on the combined
effects produced by the symmetrical component values of
the stator currents and the value of the winding tempera-
tures. Both sinusoidal and non-sinusoidal motor currents
can be accommodated. A simplified thermal equivalent
circuit is shown in Fig. 9 for the motor under protection
Where temperatures are represented by voltages, thermal
mass by capacitance, thermal resistance by electrical
resistance, and heat flow by current flow. The value i is
proportional to the amount of rotor heating produced by
the current flow in the roior. Equation 4 below governs
rotor temperature:
i = I2 = I12 ~ K I22 ~4
In this case, i equals the total rotor hea~ing value of
the stator currents. Il is e ual to the R~S value of the
~ositive sequence value OI stator current. I2 is ecual to
R~S vaLue of he negative se~ence value of stator current
and K e~uals the motor constant which is approximately 6,
which is generally equal to the locked rotor current over
the full load current. The rotor can be heated by heat
flow through resistive device RSR from the stator or by
heating produced by the rotor current rerresented by i
The model equation whicn governs the rotor temperature is
given by:
i;2~7![:~L9
50,186; 50,187; 50,200;
43 50,280; 50,281
CR dtR = i + SR R (5)
The latter equation can be expressed as shown in equations
6 and 7.
dIR _ _ ~ T5 _ TR or, (6)
dIR I12 + K I22 TS - TR
which involves the constants CR and CRRSR. The second
term in both equations 5 and 7 represents a time constant
value which relates to rotor cooling by means o heat
conduction to the stator. This can be determ~ined experi-
mentally and is normally assumed to range from lS to 30seconds for a large motor. The value of CR is related to
locked rotor current (ILR), stall time (TS), and m~ximllm
rotor bar te~perature (TR ) which is about 44aoc for an
aluminum squirrel cage motor. If the initlal rotor tem-
perature is ass~med to be 40C and ~he heat loss from the
rotor to the stator is neglected, the following approxi-
mations are true as shown in equa~ions 8, 9 and lO.
At ~ CR (8)
T ~ -40C r 2
TS CR
I 2 T (10)
The preceding, including the value of 2SR appIies to
12~7~9
50,186; 50,~87; 50,200
g4 50,280; 50,281
locked rotor conditions. The model given by Fig. g is
thus used to protect the rotor of a large machine during
starting. Once the machine is spinning, cooling air flows
through the air gap thus greatly modifying the thermal
equivalent circuit. At this ti~e, the need ~or motor
protection shifts from the rotor to the stator. Simple
overtemperature protection can b~ provided by stator
isolation temperature measurements given by the RTD
measurements associated with the RTD unit of 2~ and the
description associated with Figs. 14A through D. An
analog computer representation of Fig. 9 is given in Fig.
10. The equivalent transfer function representative of
the analog arrangement of Fig. 10 is shown in Fig. 11.
The protection scheme can be implemented by means of a
sample data control theory based on Z transforms or by
maans of a central differential equation derived from
eguation 7. The foregoing is depicted in equations 11, 12
and 13.
- , 2 -
Il = 1/3 [Ia + aIb a Ic] (11)
202 1/3 ~'a + a Ib + a T ] ( 12)
Io 1/3 [Ia b c~ (13)
The effect of this is shown ir. ~lg. 12 which essentially
represents a vector calculation of symmetrical components
The analog circuit solutions to eauations 11, 12 and 13
require 120 phase shifting networks which assumes sinu-
soidal currents. ~he digital rspresentation, however, is
valid for non-sinusoidal currents. In addition to sinu-
soidal currents and utilizes electrical current sampling
techniques with the phase snif~ing achieved by summing
samples taken at 0, 120 and 2~0 intervals. This is best
represented by observir.g ~ig. 13, Table III and eG~ations
14, 15 and 16.
7~3~l9
~ 50,186; 50,187; 50,200;
50,280; 50,281
TABLE III
( -A iB i
Ao~--ib~ ~o~--~ Co ~ lo 20
120 ~iA iB iC ~ io i1 i2
1~0 120 ~ 120 120 120 120
240 ~ A2go ~2ao C240 i2aO i12~0 i2240
370iA370 B370 C370 370 1370 370
i1 = 1/3 LiAo B120 + C2 0] (14)
i2 = 1/3 riAo B240 C120l (15)
oO ~ Ao 30 o] (16)
10 lo, i20 and io represent the instantane-
ous values or ~he positive, negative and zero sequence
currents respectively at 0. As is shown in Table I, the
eouations represents diagonal and horizontal summing of
the values iA/ i~ and ic present in the Table. If the
cur~ent is assu~ed to be cons~ant for the second cvcle,
then 13500 = ioO and equation 17 appllss:
il = 1/3 [iA + i~ iC ] (17)
120 120 2ao 0
The vaiues of i1, i2 and io can thus be calculated at 0,
120 and 2 0 by knowing the values of Table 1.
~2~7~1g
50,186; 50,1~7; 50,200;
a6 50,280; 50,281
The protective relationship requires knowledge
of the RMS value squared of the positive and negative
sequence currents, I12 and I22 rather than the instantane-
ous values. Thus, equations 18 or 19 are representative.
I2 = 1 ~ i21 dt (1~)
I 2 ~ 1 ~ i2 ~19)
N=1 N
Thus, if the samples are taken each 120, only
three values of IA, IB and $C will be using the calcula-
tion of equation 19 and the result could be very inaccur-
ate. To avoid this, the sample as ta~en during the secondcycle of the power line monitor by the current transform-
ers 30, or example, are taken at slightly later times
than durir.g the first cycle. As an example, a delay of
10 each time can be utilized. ~n this case, a total of
36 samples of the currents are obtained for each cycle. A
totaL of 36 cycies in the power line is in general re-
auired to obta_n all the data. However, because of the
similarity of the three currents, I~ and Ic, a total
of only 12 cycles is actually lequired. The value of I12
can thus be calculated every 12 cycles (.2 seconds at 60
Hz.) of the power line and is given by equations 20, 21,
22 ard 23.
11 2
I 2 = 7 ~ 2 (20)
1 3 X=0 N=0 N-120+K-10
11 2
I2 = 36 ~ 0 ~=o 2 N-120~K-10 (21)
~2~7~9
50,186; 50,187; 50,200;
47 50,280; 50,281
11 2
Io2 = 36 ~ 0 ~=0 N-120+K~10 (22)
where Il2
N-120+K-10
(23)
.3 3 ~-120+K-10 BN.120+K-10 iCN-120 K 10~
It is of interest that the value I~2 is zero
even for non-sinusoidal currents, if the three-phase
current has the same wave shape and are displaced in time
by 120. Further the value of I12 is the value of the RMS
phase current s~ared and thus the protection is based on
the true RMS motor current calculations. This is very
important as the protection arrangement does not rely on
sinusoidal motor currents. Experience has shown that if
it is not oossible to sample the currents IA, IB, and IC
simultaneously, it is import2nt tnat the sequence in which
the currents are sa~.pled should be staggered by ABC, BCA,
CA~ to minimize alse calculations of a negative sequence
current. The oregoing is therefore utilized in the
control unit 25.
OPERATION OF T~iE COMTROL -u~IT 26
The microprocessor unit MP initializes itself
and examines s~itch inputs such as are shown to the left
of the unit 26 of Fig 2. It looks at the programmable
read-only-memories s~l throush EP5 and reads any tables
which are stor-d thereir., it oeing noted that the latter
programmable memories provide memory capability for the
microprocessor MP. It also initializes the random access
memories VRl and VR2. It also defines whether a port such
as typically shown to the right o random ac_ess memories
VRl, V22 or the electrically programmaole read-only-
memories EPl through ~P5, for example, are to be in ~he
input mode or ou.put mode, lt being understood that data
~Z~'7C~19
50,186; 50,187; 50,200
48 50,280; 50,281
can flow both ways. Furthermore, there is an interrupt
signal on the RST input of the microprocessor that is to
be read every 5.56 milliseconds. To allow that to be read
by the processor an internal mask has to be reset. This
is done during initialization. The volatile RAM VRl
provides at the output T/OUT/ a signal which allows the
microprocessor to operate on the above-indicated 5.5S ms
cycle. This timer is what causes the overall routine of
the microprocessor to be interrupted three times a line
voltage cycle so that the aIorementioned implementation
described with respect to Figs. 7-13 can take place. The
tables defined prev~ously which are stored in the elec-
trically progra~mable read-only-memory EPl through EP5
Contained data associated with Table II herein. This data
was placed there by utilizing the Xey switch SW7 in the
PROGRAM mode and the various operations described pre-
viously with respect to Eig. 6C, for example. As soon as
the key switch SW7 is turned to PROGRAM, the micropro-
cessor is set up to interpret the pushbuttons SW6 and SW3
in such as ~ay that a EUNCTION can be selected and a TRIP,
ALARM, or TIME value, for exam?le, can be incremented or
decremented. This inIormation is fed to the microuro-
cessor r~ by way of the port designated ~BO through PB7 on
the device EP5. This inormation is processed by _he
microprocessor and then sent to the non-volatile read-
only-memory NVR and the vola~lle random access memories
VRl and VR2, for example, 'oy way of cables A. Note that
the volatile random access memories VRl and VR2 perform
two functions, one of which is input a~d output and the
other oî which is memory. So one oî the things to con-
sider is that set~oir.ts ~hich had previously been stored
in the non-volatile memor~ .~R can be read by the micro-
processor MP. At this point in the operation the motor
contactors Ml, M2 and M3 have not been closed, so the
microprocessor MP, although performing some initializa-
tion, is sssentially walting for an input to indicate that
a start of the motor seousncing unction, as ii typicâlly
-" ~Z~7~g 50,186; 50,187; ~0,200;
`49 50,280; 50,281
known in the motor art, should occur. Meanwhile, all of
the inputs and outputs of the control device 26 are con-
stantly being monitored mainly to determine if their
status has changed or should be changed. This is done in
sequence, not in parallel, although it occurs so quickly
it looks as if its being done in parallel. The main
sequencing occurs by utilizing the chip enable CE on each
of the devices described previously. Of course as was
mentioned previously, effective programming can be accom-
plished at this time. One of the values that can beprogrammed is STARTER CLASS. One of the tables permanent-
ly stored in one of the electrically programmable read-
only-memories EP1 through EP5 is related to various
classes of motors (see Table II). By going into a pro-
gramming mode and utilizing the switches SW6 and SW3 thistable can be incremented or decremented to the next class
or kind of motor. This allows the motor controller to be
changed literally from~~~a~~-motor sontroiier for ~onè~ typé ` of
motor o~eration to a motor controller of another type
-- .. . . -- ~ . ..
o~eration. Furthermore, the previously described motor
class table has associated therewith other tables (not
shown) which are automatically referred to once the ap-
propriate motor class is selected. This provides the
controller assembly 10 with a great deal of flexibility.
This is done by utilizing the key switch SW7 in the
PROGR~M mode and stepping through ~he appropriate func-
tions until the words "starter class" appear in the
FUNCTION readout of the panel 24. It will be noted that
the AL~M and TIME readouts will have contained therein at
this time a numerical rspresentation of the starter class
that the c~ntroller assembly 10 is designed to accommo~
date. That can ~e chansed by utilizing the switches SW6
and 5W3 to increment or decrement to other stored starter
classes. These classes in turn are referred to in other
parts of the memory for any new kinds of functions wh_sh
are associated wlth that starter class. As an example,
motor style or class 11202 is an across-tne-line starter
~21D7~i9
50,186; 50,187; 50,200
50,280; 50,281
which only has one contact associated with it. A motor
class such as la202 may have three or four contacts as-
sociated with it, so with each of these code numbers a
different sequencing may be utilized by the microprocessor
MP for effective starting and control of the motor. Once
it has been established that there is a ligitimate start
request, the microprocessor looks at the starter class
number which has been programmed in and is available, and
based ~pon that number the microprocessor will then go to
a specific motor start sequence. At this point of time,
if any of the specific re~uirements îor a startup is not
met, the start will be aborted, and the words "IMPROPER
START" will come up on the FUNCTION display, or the word
"EMERGENCY STOP" will be displayed in the FUNCTION dis-
play. One of the things that is also ~one at this time isthe phase of the voltages are sensed to assure that the
particuiar motor class selectad is utilized in the proper
phase relationship. A test is done on ~he input voltage
at this time to assure that phase A does in fact precede
phase B whïch does in fact precede phase C, and starting
is inhlbited until the proper sequences of phases is
achieved. This phase information is inferred from the
signals VCB and VA3 sho~r. in Fig. 2. Once a valid start
command is present, prestart conditions are actuated, and
ths prestar~ relay is closed if some peripheral equipment
needs to be actuated. The reason _or this is that ~or
some classes of motors it may be necessary to start per-
ipheral ecuipment like a conveyor belt or a pump as an
example. The ~Rr-START output will activate this per-
ipheral equipment. The microprocessors will make surethat the prestart condition has besn met by the closing of
the prestart relay PRE-â~ to the left in Eig. 2. This
indicates that tne re~ote equipment is operating and at
this point power can be applied to the ~otor. If the
prestart condition is not met within a csr~ain period of
time, an I~PROPER âTART message is provided at tne
F7~iCTION output oî Fig. 5. After the pres-art sequence is
~ai'7~)~9
50,186; 50,187; 50,200;
51 50,280; 50,281
successfully completed, power is applied to the motor
according to the motor style that has been programmed.
Relays are closed in a certain sequence, depending upon
the d~m~n~ of the motor style. At this time a software
timer begins to run. If appropriate motor conditions are
not met in this period of time, then tha microprocessor
stops the operation. A typical example occurs in a re~c-
tor start motor. The reactor is left in the line for a
certain amount o time to reduce the voltage as the motor
is started so that the motor does not draw excessive
current. As it mo~es up to speed, the reactor is pulled
out of the line and the full line voltage is applied. At
the expiration of the startirg time, the start conditions
are aborted as dictated by the particular program motor
style and the controller enters the run mode for the
motor. This may or may not entail changing relays which
are applyir.g powsr to the motor. ~ote, however, that
during all of this the microprocessor still monitors motor
protective functions. The s~atus of all inputs are moni-
tored, even ihe display inputs. During startup it ispossible to take data from the pushbuttons, but the micro-
processor will not respond to it, for example, if the step
switch SW~ is actuated there will be no response. Note
that an emergency stop can be institu~ed at any time and
in fact bypasses the microprocessor. This can be done by
the utilization OI an externaL contact closure, such as
E-STOP shown to the left in ~ig. ~. ~owever, the micro-
processor is alerted to this by the ESO oU~DUt shown in
Fig. 16D. This ESO ou~put is provided to the electrically
programmable rsad-only-memory E~, and th~n the micro-
prQcessor. So even though the microprocessor is bypassed
in an emergency stop situation, it is still alerted to the
fact than an emergency stop is taking place and can act
accordingly. ESO means "emergency stop output". The
microprocessor can then ta~e action independently of the
emergency stop relay E-STOP REL just by using its own
internal program. .~s was mentionsd, ~fte~ the micro-
- ~Z~7~19 50,186; 50,18~; 50,200;
52 50,280; 50,281
processor has reached the end of the starting operation,
it now goes into the load or run mode. This occurs after
the expiration of the previously described timing incre-
ment. At this point the motor and microprocessor can act
without any significant changes for months, if need be,
without interaction with an operator. Furthermore, it
will go through a three times ~er cycle current-voltage
monitoring technique as described previously with respect
to Figs. 16E, t6~, 16G, for example. The current points
associated with Fig. 13, for example, are calculated over
a 12-cycle period. Three samples are taken per cycle over
12 cycles. This gives 36 samples. At the end of the
twelfth cycle the microprocessor will begin to look at the
data that has bee~ accumulated over the 12 cycles and
processings of that data taXe place for determining nega-
tive sequence current, etc. Some operations do not oper-
ate on a 12-cycle basis, however. One is ins~antaneous
overcurrent. If instantaneous overcurrent is sensed by
the microprocessor by way of its communication with the
current tr~nsformers of Eig. 16~ as routed through device
EP5, the microprocessor will operate on a l-cycle basis,
and if necessary, a trip 'unction will be executed.
Furthermore, the RTD devices provide inputs to the control
unit by way of cable 31 and these devices are monitored.
Typically, this is done on a 6-second time frame. This
information gets into the control unit by way of program-
mable read-only-memory EP4 and it is utllized in conjunc-
tion with stato current data, as described previously.
At this point, the controllsr is in a position to react to
a stop rsquest. This stop reauest may be begun by actuat-
ing pushbutton 22, for exampls, as is shown in r ig. 2 .
The microprocessor operates to detarmine that the request
is legitimata and then goes into a stop sequence, which is
also determined by motor clas, number as described pre-
viously. This would be a normal controllsd stop. P~estop
relays are closed where necessary, for example tG stop a
conveyor belt or to issue an alarm that the motor is going
~2~19 50,186; 50,187; 50,200;
53 50,280; 50,281
to stop, and at an appropriate time the main contactors,
for example, Ml, M2 and M3 are opened. If certain reports
are not fed back to the microprocessor concerning a stop
condition, such as might be Iound at the pre-stop PRE-STP
input of Fig. 2, then an improper stop message may be
displayed in the FUNCTION portion of the front panel 24.
Note than an emergency stop, that is a very ~ast stop
which may even be close to a panic stop, can occur even
during a normal stop routine. Everything is dropped out
very quicXly. The typical I2T currsnt situation upon
which many circuit protective devices operate is related
to the inputs IA, IB and IC and to the ~TD inputs as are
determined on a 12-cycle and 6-second basis, respectively.
Information from both the RTD units and the stator cur-
rents IA, IB and IC are placed into a software accumulatorwhere the total net effect of all currents are taken into
account. It is possible that a condition could e~ist
where the I T by itself is not enough to initiate some
sort of action. But if loo'~ed at in conjunction with
other heat sources, as measured by the RTD's, inferences
about the heat in the rotor are such as to re~uire shut
down. Nota that rotor current is not measured directly;
it is inferred by the utilization OI negative se~uence
components, etc., as determined in the stator windirgs.
Note also that .he micro?rocesscr can act on a t~pical
ground fault trip situation. ~otor jam underload and open
phase unbalance can also be handled by the microprocessor.
These things are typically looXed at in sequence, but
typicaily only looXed at once duri~g the 12-cycle period.
Typically, every operation that has to be performed is
done within the '2-cycle period. Some of the things will
be done m~ny times within ~hs 12-cycle period and other
things will be done only once during the 12-cycle period.
~resume tnat the 12-cycle psriod is o~er. The next thing
~hat the microprocessor would do, and it does not have
much time to do ~his before the next 12-cycle period
starts, ~s i_o 3ee if a~y o. the displays n.ust be re-
~Z~7~g
50,186; 50,187; 50,200;5~ 50,280; 50,281
freshed. Pushbutton situations are monitored, etc. Note
that the microprocessor operates in a controlled fashion,
monitorin~ inputs and outputs, refreshing displays, rest-
ing if need be on a continuous basis, but is interrupted
S once every 5.5~ seconds or completing a new sampling
techniaue associated with the currents IA, IB and IC, etc.
During the 5.5 millisecond time frame, about 4 to 4
milliseconds are utilized in calculating overcurrents,
sampling inputs and the like. So only 1 to 2 milliseconds
are available for going through other functions that are
again periodically interrupted. Note that the DEAD MAN
circuit described pxeviously looks for the 5.56 cycle
input signal. If it doas not receive one of these during
an appropriate time frame, the DEAD MA~T presumes that the
microprocessor is not acting intelligently and operates to
begin to reinitialize the microprocessor by way of the
TRAP input tnereof. ~ote that the metering associated
with the readouts on the front panel 2g is controlled by
the microprocessor, and this usually occurs by sa~mpling
various inputs and outputs and displaying those as re-
quired by the operator.
It can be seen there^ore that the micro-
processor-control'ed motor con~roller or controller assem-
bly is extremely versatile, saîe, small, and reliable for
many modes o motor control and protection. It provides ?.
programming feature or an operator. It provides readout
îeatures, is au~omatic in many respects, and further
utilizes certain techniques associated with negative
sequence cur-ents whether ~hey be sinusoidal or non-
sinusoidal or det~rmining motor overload conditions orexcessive heating ronditions.
