Note: Descriptions are shown in the official language in which they were submitted.
TITLE OF THE INVENTION
"Cryptographic System"
BACKGROUND OF THE INVEM~ION
The present invention relates to a cryptographic
system.
When scrambling digital information data, it is the
current practice to employ a random number generator which
generates a random pattern of binary l's and O's with which
the data are muddle summed. Current random number
generators are broadly classified into a first type in
which the random number is dependent exclusively on the
initial value and a second type in which the random number
is dependent on the scrambled data. The first type of
random number generators it susceptible to wire tapping
because the repetitive sequence of bit pattern is easily
discernible by eavesdroppers. The second type of prior art
scramblers comprises a shift register coupled to the output
of a muddle adder which combines input data with the
output of a cipher memory which stores a sequence of binary
digits as a key code and reads the stored bits in response
to an address code supplied from the shift register. The
descrambler used in conjunction with such scramblers also
comprises a shift register that supplies an address code
for addressing the same key pattern as in the scrambler
stored in a decipher memory the output of which is coupled
-- 2 --
to a muddle adder to be combined with the scrambled input
data. Should a bit error occur in the transmitted
sequence, decoded data will be disrupted and such
disruption will continue as long as the error bit is
shifted in the shift register. If the number of the shift
resister stages is substantial, the disruption will
continue for a long period of time even ire the disruption
is caused by a single bit error.
SUMMARY OF THE INVENTION
-
It is therefore an object of the invention to
provide a cryptographic system which prevents long-period
data disruptions while ensuring security against
eavesdroppers.
This object is obtained by combining the
non repetitive characteristic of feedback random number
generation and the repetitive characteristic of initial key
pattern generation to form a combined address code with
which stored bits of the key pattern are addressed for
muddle summation with information data bits
A cryptographic system of the present invention
comprises a data scrambler connected to one end of a medium
for transmission of scrambled binary digits through said
medium and a data descrambler connected to the other end of
the medium to receive the-transmitted binary digits. The
data scrambler comprises a first muddle adder having a
first input connected to be responsive to a sequence of
binary digits to be scrambled and a second input connected
to be responsive to a sequence of scrambling binary digits
for generating a sequence of scrambled binary digits for
application to the medium A first function generator
having a memory is provided four storing a predeterminable
sequence of binary digits in addressable storage locations
and reading the stored binary digits in response to an
address code represented by combined first and second
patterns of binary digits which are generated respectively
by a first pattern generator and a first shift register
which is connected to the output of the first muddle
adder. The output of the first function generator is the
scrambling binary digits applied to the first muddle
adder.
The data descrambler comprises a second oddly
adder having a first input connected to be responsive to
the received binary digits and a second input connected to
be responsive to a sequence of descrambling binary digits
for generating a sequence of descrambled binary digits. A
second function generator having a memory is included for
storing a predeterminable sequence of binary digits in
addressable storage locutions and reading the stored binary
digits in response to an address code represented by
combined random patterns of binary digits which are
generated respectively a second random pattern generator
and a second shift register which is connected to be
responsive to the received binary digits. The output of
the second function generator is the descrambling binary
digits applied to the second muddle adder.
In the event of a transmission error, a disruption
will occur in the bit stream in the second shift register.
However, the disruption persists as long as the error bit
exists in the second shift register which accounts for only
a portion of the full address code of the second function
generator. Therefore, the cryptographic system of the
invention has a smaller disruption time than that of the
second type of prior art while eliminating the disadvantage
of the first type of prior art.
ROUGH DESCRIPTION OF_ THE DRAWINGS
The present invention will be described in further
detail with reference to the accompanying drawings, in
which:
Fig. 1 is a schematic illustration of a preferred
embodiment of the invention; and
Fig. 2 is an illustration of an alternative
embodiment of the invention.
DETAILED DESCRIPTION
Referring now to Fig. 1, there is shown a
cryptographic system of-the present invention. The system
. 5
generally comprises a data scrambler lo and a data
descrambler I connected over a transmission medium OWE
The data scrambler 10 comprises a function generator 11, a
key pattern generator 12, a random pattern generator 13, a
shift register 14 and a muddle adder or Exclusi~e-OR gate
15. The function generator 11 may comprise a read-only
memory or random access memory for storing a random
sequence of binary l's and 0's supplied from the key
pattern generator 12 in addressable locations. The random
pattern generator Lo may comprise a linear feedback shift
register which generates a sequence of random patterns of
parallel binary l's and 0's in response to a clock pulse
supplied from a clock source 17. The function generator 11
reads the stored binary l's and 0's as a function of an
address code which combines the outputs of the random
pattern generator 13 and shift register 14. The output of
the function generator 11 is therefore a random sequence of
scrambling binary l's and 0's which are fed to the muddle
adder 15. A sequence of input digital data at input
terminal 16 is muddle summed in the adder 15 with the
scrambling bits on a per bit basis. The scrambled data
bits are sequentially applied on the one hand to the shift
register 14 and on the other hand to the transmission
medium 30~ The shift register 14 supplies the stored bits
to the function generator 11 in parallel form in response
to the clock pulse supplied from the clock source 17 which
is synchronized with the input digital data. The function
generator 11 is also synchronized with the clock source 17
so that the scrambling data bits are time coincident with
the input data bits at terrlinal 16.
The transmitted scrambled data bits are received by
the data descrambler 20. The descxambler 20 operates on
the received data bits in a process inverse to that of the
scrambler 10. The scrambled data bits are applied to a
shift register 24 having the same number of bit positions
as the shift register 14. A function generator 21
identical to the function generator if stores a key pattern
supplied from a key pattern generator 22 and reads the
stored bits as a function of a combined set of address bits
supplied from the shift register 24 and a random pattern
generator 23 which is also identical to the random pattern
generator 13. A bit synchronization pulse is obtained from
a sync generator 27 coupled to the input terminal of the
descrambler. The input bit stream is muddle summed in an
Exclusive-OR gate 25 with a sequence of descrambling bits
from the function generator 21. The original bit stream is
delivered from the muddle adder 25 to an output terminal
26.
Since the number of bits stored in the shift
register 24 accounts for a fraction of the number of
,..
I
address bits and is much smaller than the corresponding
number of bits of the feedback type of prior art
cryptographic system, a bit error in the received sequence
will exist in the shift register 24 for a small interval
tire as compared with the prior art system, and the
resultant disruption does not persist for a long period of
time. Since the scrambled data sequence contains no
repetitive patterns, the system ensures security against
wire tapping.
Fig. 2 is an illustration of an alternative
embodiment of the invention which is similar to the
previous embodiment with the exception that in the
scrambler 10 one of the output leads of the shift register
14 is disconnected from the function generator 11 and
coupled instead to an input of a muddle adder 18. The
muddle adder 18 takes its another input from the function
generator 11 to provide a sequence of scrambling bits for
coupling to the muddle adder 15. Alternatively, one of
the output leads of the random pattern generator 13 may be
disconnected from the function generator 11 and coupled to
the module 2 adder 18, instead of applying the one-bit
output from the shift register 14. In like manner, the
descrambler 20 includes a muddle adder 28 which receives
one of the output leads ox the shift register 24 to prove
muddle summation with-the output of the function
So.
generator 21 for generating a descrambling bit sequence for
application to the muddle adder 25.
w
