SYSTEM FOR REGULATING DATA TRANSFER OPERATIONS

SYSTEME REGULATEUR DE TRANSFERT DE DONNEES

English Abstract

ABSTRACT OF THE DISCLOSURE
SYSTEM FOR REGULATING DATA TRANSFER OPERATIONS

A Magnetic Tape Peripheral Controller is used to
manage data transfers between a peripheral tape unit and a
main host computer. A buffer memory in the peripheral
controller is provided with a status counter unit to monitor
the amount of data-in-transit which momentarily resides in
the buffer. The status counter unit provides output signals
to the peripheral-controller to elicit action calling for
more date from the peripheral tape unit or from the host
computer or to indicate that the amount of data in the buffer
memory was fully loaded before the main host computer
responded to allow acceptance of it.

Claims

The embodiments of the invention in which an exclusive
property or privilege is claimed are defined as follows:-

1. In a network wherein data is transferred between a main
host computer and a magnetic tape peripheral unit via a
peripheral-controller, wherein said peripheral-controller is
initiated by commands from said host computer to execute data
transfer operations and said peripheral-controller includes a
common control circuit unit for sequencing microcode
instructions and a peripheral dependent circuit unit for managing
said tape peripheral unit, the system for regulating data trans-
fer operations comprising:
(a) buffer memory means in said peripheral-controller
for temporarily storing blocks of data being
transferred, said buffer memory means having
channels of connection to said tape peripheral
unit and said host computer;
(b) status means in said peripheral dependent circuit
unit for providing information data for indicating
the number of blocks of data residing in said
buffer memory means;
(c) signal output means connected to said status means
and functioning to provide status signals to said
common control circuit unit.

2. The system of claim 1, wherein said host system initiates
a Write operation command to said peripheral-controller to
transfer data from main host computer, and said common control
circuit unit initiates routines to transfer data from said host
computer to said buffer memory means.

3. The system of claim 2, wherein said status means includes:
(a) shift register means which shifts up to count the
number of blocks of data received into said buffer
memory means.

4. The system of claim 3 wherein, when said buffer memory is
filled with blocks of data from said host computer, said shift
register causes said signal output means to pass information data
to said common control circuit unit;
and wherein said common control circuit unit dis-
connects said host computer from said buffer memory
means.

16





5. The system of claim 4 wherein, after disconnection of said
host computer, said common control circuit unit connects said
peripheral tape unit to said buffer memory means.

6. The system of claim 5 wherein, upon connection of said
peripheral tape unit to said buffer memory means, said common
control circuit unit causes execution of data transfer from
said buffer memory means to said peripheral tape unit.

7. The system of claim 6, wherein said shift register shifts
down each time a block of data is removed from said buffer
memory means to said peripheral tape unit.

8. The system of claim 7 wherein, when said shift register
is reduced by one block count, said signal output means will
pass information to said common control circuit causing it to
reconnect to said main host computer for enablement of more
data transfer to said buffer memory means.

17




9. The system of claim 1, wherein said host system
initiates a Read operation command to said
peripheral-controller to transfer data from said peripheral
tape unit to said buffer memory means.


10. The system of claim 9, wherein said status maens includes:
(a) shift register means which operates to shift up
one unit for each block of data received by said
buffer memory means from said peripheral tape
unit.


11. The system of claim 10 wherein, when said shift
register means indicates two blocks of data have been
received, said signal output means provides a signal to said
common control circuit unit causing said buffer memory means
to be connected to said main host computer.


12. The system of claim 11, wherein data is simultaneously
transferred from said peripheral tape unit to said buffer
memory means, and also from said buffer memory means to said
main host computer.


13. The system of claim 12, wherein said shift register
shifts up for each data block received by said buffer memory
means, and said shift register shifts down for each block of
data transferred to said main host computer.




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14. In a network wherein data is transferred
between a main host computer and a magnetic tape peripheral
unit via a peripheral-controller, wherein said
peripheral-controller is initiated by commands from said
host computer to execute data transfer operations and said
peripheral-controller includes a common control circuit unit
for sequencing microcode instructions and a peripheral
dependent circuit unit for managing said tape peripheral
unit, the system for regulating data transfer operations
comprising:
(a) buffer memory means in said peripheral-controller
for temporarily storing blocks of data being
transferred, said buffer memory means having
channels of connection to said tape peripheral
unit and said host computer;
(b) status sensing means in said peripheral
dependent circuit unit for providing
status signals to said common control
circuit for indicating the number of blocks of
data residing in said buffer memory means
during each clock cycle;
(c) signal output means connected to said status
sensing means and functioning to provide said
status signals to said common control circuit
unit ;
(d) said common control circuit unit including:
(d1) means for generating basic clock cycles;
19




(d2) means for executing buffer-host data
word transfers using said basic clock
cycles;
(d3) means for concurrently executing
buffer-peripheral data word transfers
by stealing selected clocks of said
basic clock cycles;
(d4) wherein said means for executing and
said means for concurrently executing
are controlled in response to said status
signals.


15. The system of claim 14, wherein said
means for executing buffer-host
data word transfers include:
(a) a burst mode data word transfer operation
functioning to transfer data words between
said buffer memory means and said host computer
at a speed at least eight times faster than
data word transfers between said buffer
memory means and said peripheral tape unit.






16. The system of claim 15, wherein said
status sensing means includes:
(a) shift register count means
having "Xm"
bit positions where a "true" signal in each
bit position represents a full block of N data
words residing in said buffer memory means
during that clock cycle, said "true" signal
being incremented/decremented for each block
of data words added to/removed from said
buffer memory means:
(b) block counter logic means for incrementing/
decrementing said shift register count means,
and including:
(b1) means for counting blocks of data words
added to/removed from said buffer memory
means.




21


17. A system for maximizing the effective rate
of data transfer operations between a host computer and a
peripheral tape unit, wherein data transfer instructions
from said host computer are executed by a
peripheral-controller having a data buffer storage means
and a microprocessor means, said system comprising, in
combination:
(a) data buffer storage means organized to store
data words in multiple blocks where each block
holds N data words;
(b) said data buffer storage means having channels
of connections between said host processor
and said peripheral tape unit and functioning
to temporarily store data words-in-transit
between said host computer and said peripheral
tape unit;
(c) buffer memory sensing means for providing
status data signals to said microprocessor
means, as to the number of blocks of data
words residing in said buffer storage means
during each basic clock cycle;
(d) said microprocessor means for selecting and
controlling data transfer operation cycle
and including:
(d1) means for generating basic clock cycles;
(d2) means for sensing said status data
signals;
(d3) mean for addressing data words in said
buffer storage means;

22

(d4) means for concurrently executing
Read/Write data transfer cycles between
said buffer storage means and said
host processor, and between said buffer
storage means and said peripheral tape
unit.
18. The system of claim 17, wherein said
microprocessor means includes.
(a) Automatic Read/Write logic means for executing
data word transfer of blocks of data between
said buffer storage means and said peripheral
tape unit without interruption to said
microprocessor means wherein selected basic
clock cycles are stolen from buffer-host
transfers to be used for buffer-peripheral tape
transfers.

23


19. In a system using a peripheral controller
providing for word transfers between a host computer and
buffer memory, and for concurrent word transfers between
a peripheral tape unit and buffer memory, and operating
to monitor the number of blocks of data words in said
buffer memory and to provide control signals to a
microprocessor means in said peripheral controller for
maximizing the rate of data transfers and minimizing the
occurrence of incomplete transfer cycles, the combination
comprising:

(a) a buffer memory organized to store blocks of
"N words" each of data and including:
(a1) first channel means for transferring
data between said buffer memory and
said host computer;
(a2) second channel means for transferring
data between said buffer memory and
said peripheral tape unit;
(b) block counter register means receiving block
count increment/decrement/no change signals
from a block counter logic unit and
including:
(b1) means to store status signals representing
the number of blocks of data words
residing in said buffer memory at each
clock cycle;
(b2) means to communicate said status signals
to said microprocessor means;
(c) said block counter logic means including:


24


(c1) means to count the number of data words
transferred between said buffer memory
and said host computer for each
selected transfer cycle, via receipt of
a system data block signal from an
address register means;
(c2) means to count the number of data words
transferred between said buffer memory
and said peripheral tape unit for each
selected transfer cycle, via receipt of
a peripheral data block signal from said
address register means;
(c3) means to sense the condition of each
selected-transfer cycle as to being a
Read or a Write operation through Read/Write
microcode signals from said microprocessor
means;
(c4) means to generate said increment/decrement/
no change signal to said block counter
register means;
(d) address register means for receiving buffer
memory addresses from said microprocessor
means and including:
(d1) system address register means for sensing
the number of data words transferred
between said host computer and said
buffer memory, on a selected transfer
cycle, and generating a system data block
signal for each block of N words;




(d2) peripheral address register means for
sensing the number of data words
transferred between said buffer memory
and said peripheral tape unit on a
selected transfer cycle, and generating
a peripheral data block signal for each
block of N words;
(e) microprocessor means for controlling and
selecting data transfer cycles and including:
(e1) means for selecting Read/Write data
transfer cycles between said host and
buffer memory or between said peripheral
tape unit and buffer memory, and
including means to generate said
Read/Write microcode signals to said
block counter logic means;
(e2) means for sensing said status signals
in said block counter register means to
enable selection of the optimum data
transfer operation;
(e3) means for generating basic clock cycles
for enablement of buffer memory-host
computer data transfers;
(e4) means for selectively stealing certain or
said basic clock cycles for enablement
of buffer memory-peripheral tape data
transfers;
(e5) wherein concurrent data transfers between
buffer-host and transfers between
buffer-peripheral may be interleaved.

26

20. The combination of claim 19 including:
(a) automatic Read/Write logic means, initiated
by said microprocessor means, for controlling
data word transfers between said buffer
memory and tape peripheral unit using stolen
clock cycles concurrently with data word
transfers occurring between said host and
buffer memory.

21. The combination of claim 20 which includes:
(a) automatic incrementing register means for
automatically incrementing said peripheral
address register means during operation of
said automatic Read/Write logic means.

22. The combination of claim 21 which includes:
(a) means for testing said block counter register
means by simulating said increment/decrement/
no change signals.

27


23. In a peripheral controller which manages data
transfers between a host computer and a peripheral tape
unit wherein said peripheral controller has a buffer memory
for temporary storage of data words-in-transit and provides
a rapid burst-mode routine for host-buffer data transfers
and automatic read/write logic control for buffer-
peripheral tape data transfers, said burst routine and
automatic logic control occurring concurrently on an
interleaving clock cycle operation, an
optimizing system for monitoring the number, on each
clock cycle, of blocks of data words residing in said
buffer memory to provide information for said peripheral
controller in selecting optimum routines for maximizing the
rate of data transfer operations while minimizing the
likelihood of incomplete and erroneous data transfer cycles,
said optimizing system comprising:
(a) buffer memory means having a first
communication channel to a host computer
system and a second communication channel to
a peripheral tape unit, and including:
(a1) address bus connection means for
receiving addresses from a system
address register and a peripheral
address register;
(b) said system address register for temporary
storage of buffer addresses to be accessed in
said buffer memory means when data words are
being transferred between said host computer
and said buffer memory means, and including:

28







(b1) system bus connection means for
receiving addresses from a microprocessor
means;
(b2) means to generate a system-carry signal
when "N" data words in said buffer
memory means have been addressed;
(c) said peripheral address register for
temporary storage of buffer addresses to be
accessed in said buffer memory means when data
words are being transferred between said
buffer memory means and said peripheral tape
unit, and including:
(c1) peripheral bus connection means for
receiving addresses from said
microprocessor means;
(c2) means to generate a peripheral carry
signal when "N" data words in said
buffer memory means have been addressed;
(d) block counter logic means receiving said
system-carry and said peripheral-carry signals
together with a Read/Write signal from said
microprocessor means, said logic means
generating, on each clock cycle, a first and
second count logic signal to a gating means;
(e) gating means for generating, on each clock
cycle, an up-count signal, down-count signal,
or a non-count signal to a block counter
register means and including:

29






(e1) means for generating said up-count,
down-count or non-count signals via
microcode signals from said
microprocessor means in lieu of said
block counter logic means;
(f) said block counter register means having "Xm"
bit positions where a "true" signal in each
bit position represents a full block of N
data words as presently residing within said
buffer memory means, and wherein said up-count
signal acts to increment the number "X" of
true signals in said bit positions while said
down-count signal acts to decrement the
number "X" of true signals in said bit
positions;
(g) said microprocessor means generating basic clock
cycles and operating routines for executing
(i) Read/Write data word transfers between
said host and aid buffer memory means, and
(ii) Read/Write data word transfers between
said buffer memory means and said peripheral
tape unit, said microprocessor means
including:
(g1) means to generate buffer memory addresses
for transmittal to said system and said
peripheral address registers;
(g2) means to generate Read/Write control
signals to said block counter logic means;






(g3) means to generate up-count, down-count,
non-count microcode signals to said
gating means for testing operation of
said block counter register means;
(g4) means to scan said block counter
register means to establish the number
"X" of blocks of data words residing in
said buffer memory means;
(g5) means for selecting the next appropriate
operating routine based on the value of
the said number "X".


24. The system of claim 23 wherein, on a Read
operation, when the value of X is less than 2 (blocks), the
said microprocessor means will disconnect said first
communication channel to said host computer to permit it
to service other peripheral controllers.


25. The system of claim 23 wherein, on a Read
operation, when the value of X is "2" or greater, the
said microprocessor means will initiate a connection on
said first communication channel to said host computer and
execute a burst mode data transfer operation from said
buffer memory means to said host computer.


26. The system of claim 23 wherein, on a Read
operation, when the value of X is "6", said microprocessor
means generates an access error signal to said host
computer.

31





27. The system of claim 23 wherein, on a Write
operation, when the value of X reaches "6", the said
microprocessor means will disconnect said first
communication channel to said host computer to permit it
to service other peripheral controllers.


28. The system of claim 23 wherein, on a Write
operation, when the value of X reaches "1", the said
microprocessor means will generate an access error signal
to said host computer.

32

Description

SYSTEM FOR Regulating DATA TRANSFER OPERATIONS

FIELD OF THY INVENTION
This invention is related to systems where data transfers
are effectuated between a peripheral terminal unit and a main
host computer wherein an intermediate I/O subsystem is used to
perform the housekeeping duties of the data transfer
BACKGROUND OF THE INVENTION
A continuing area of developing technology involves the
transfer of data between a main host computer system and one or
more peripheral terminal units. Jo this end, there has teen
lo developed I/O subsystems which are used to relieve the monitor-
in and housekeeping problems of the main host computer and to
assume the burden of controlling a peripheral terminal unit and
to monitor control of data transfer operations which occur
between the peripheral terminal unit and the main host computer
system.
A particular embodiment of such an I/O subsystem has been
developed which uses peripheral controllers known as data
link processors whereby initiating commands from the main host
computer are forwarded to a peripheral-controller which manages
the data transfer operations with one or more peripheral units.
In these systems the main host computer also provides a "data
link word" which identifies each task that has been initiated
for the peripheral-controller. After -the completion of a task,




the peripheral-controller will notify the main host system with
a result/descriptor word as to the completion, incompletion or
problem involved in the particular task.
These types of peripheral-controllers have been described
in a number of patents issued to the assay new of the present
disclosure as follows:
US. Patent 4,106,092 issued August 8, 1978, entitled
"Interface System Providing Interfaces to Central Processing
Unit and Modular Processor-Controllers for an Input Output
Subsystem", inventor D. I. Millers, II.
US. Patent 4,074,352 issued February 14, 1978, en-titled
"Modular Block unit for Input put Subsystem" inventors
D. J. Cook and D. A. Millers, II.
US. Patent 4,162,520 issued July 24, 1979 r entitled
"Intelligent Input-Output Interface Control Unit for Input-Output
Subsystem", inventors V. J. Cook and D. A. Millers, II.
US. Patent 4,189,?69 issued February 19, 1980, entitled
Input Output Subsystem For Digital Data Processing System",
inventors D. J. Cook and D. A. Millers, II.
US. Patent 4,280,193 issued July 21, 1981, entitled
"Data Link Processor for Magnetic Tape Data Transfer System",
inventors K. W. Bun and J. G. Saunders.
US. Patent 4,313,162 issued January 26, 1982, entitled
'' T JO Subsystem Using Data Link Processors", inventors K. W. Bun
and D. A. Millers, II.
US. Pa-tent 4,322,792 issued March 30, 1982, entitled
"common Fronted Control for a Peripheral Controller Connected
to a Computer", inventor K. W. Bun.
The above patents provide a background understanding of
the use of the type of peripheral-controllers known as "data link
processors", DIP, used in a data transfer network between a main
host computer and peripheral terminal unit.
In the above mentioned Bun pa-tent, there was described
a peripheral-controller which was built of modular components
consisting of a common front end control circuit which was of a
universal nature for all types of peripheral controllers and which
was connected with a peripheral dependent board circuit. The
peripheral dependent circuit was particularized to handle the
idiosyncrasies of specific peripheral terminal units.

The present disclosure likewise uses a peripheral-
controller (data link processor) which follows the general
pattern of the above described system, in that the peripheral-
troller uses a common control circuit or common front end
which works in coordination with a peripheral dependent circuit
which is particularly suited to handle a specific type of
peripheral terminal unit, such as a Tape Control Unit (TCU)
which connects to one or more magnetic tape Llnits.
SUMMARY OF THE INVENTION
.
The present invention involves a data transfer network
wherein a peripheral-controller known as a data link processor
is used to manage and control data transfer operations between
a peripheral such as a magnetic tape unit (or a tape control
unit) and the main host computer system, whereby data is trays-
furred rapidly in large Buicks, such as a block of 256 words.
The data link processor provides a RAM buffer memory
means for temporary storage of data being transferred between
peripheral and host system. In this case, the RAM buffer is
capable of holding a least six blocks or units of data, each
of which consists of 256 words, each word being of 16 bits.
In order to facilitate and control those activities in
which (a) data is sometimes being "shifted into" the RAM
buffer Emory means from either the peripheral unit or from
the main host computer and (b) the data in the RAM buffer
memory is being "shifted out" either to the magnetic tape unit
peripherals, for example, or to the main host computer, it is
necessary that the peripheral-controller and the system have
data which informs it of the condition of the RAM buffer memory
means with regard to the amount of data residing therein at any
given period of time.
Thus, there is disclosed a system for regulating data
transfer operations between host and peripheral whereby a
peripheral-controller senses blocks of data stored in its RAM
buffer in order to chose routines for data transfer appropriate
to the data condition of the RAM buffer. The peripheral
controller makes use of a block counter monitoring system which
will inform the peripheral-controller and the main host system
of the "numerical block status" of data in -the RAM buffer memory
means.

'73
--4--
In particular, the present invention discloses a system
whereby the coon front end (common control) circuit uses
routines providing microcode instructions to address registers
which access locations in the buffer memory for the insertion
of data or the withdrawal of data. There are two address
registers one for addresses of data taken from to -the peripheral
unit and one for addresses of data which are to be forwarded
from/to the main host computer.
A block counter logic circuit receives input from the
peripheral address register and the system address register.
In addition, a flip-flop output to the block counter logic
circuit indicates the direction of data flow as being a "Write"
(host-to-peripheral) or a "Read" (peripheral-to-host). The
block counter logic circuit provides two output logic signals
which control a block counter. This enables the block counter
to be shifted up or shifted down so that the internal signal
data indicates the number of blocks of data residing in the RAM
buffer memory. Certain parameters may be set to trigger signal
output conditions when the amount of data in the RAM buffer
memory falls below a certain figure.
GRIEF DESCRIPTION OF THE DRAWINGS
.
FIG. 1 illustrates the block counter system of the
present disclosure which is used to inform the data transfer
system of the status of a buffer memory means.
FIG. 2 is a system diagram showing the host computer
cooperating with a peripheral-controller in order to control
data transfer to and from a peripheral unit.
FIG. 3 is a drawing showing an eight bit shift register
which can be shifted up or down according to conditions which
occur between certain logic signals and clock signals.
FIG 4 is a diagram showing how the block counter logic
unit of FIG. 1 is organized to operate during Read or Write
operations and the effect of either shifting up or shifting down
the shift register.
FIG. SPA is a schematic drawing illustrating the
significance of each bit-position in -the block counter
FIG. 5B is a surety indicating various "shift" relation-
ships of the block counter with regard to "Read" and "Write"
operations.



--5--
A "Read" operation takes data from a peripheral magnetic
-tape unit and temporarily stores it in a RAM memory buffer for
later transfer to the host system.
A "Write" operation takes data from the main host system
for temporary storage in the RAM buffer memory for subsequent
transfer to a selected magnetic tape unit via a q'CU or Tape
Control Unit.
GENERAL SYSTEM OPERATION
To initiate an operation, the host system 10, Fig 2 1
sends the peripheral controller (data link processor 20t) an
I/O descriptor and also descriptor link words The I/O descriptor
specifies the operation to be performed The descriptor Link
contains path selection information and identifies the task to
be performed, so that when a report is later sent back to the
main host system 10, the main host system will be able to
recognize what task was involved. After receipt of the I/O
descriptor link, the data link processor (DIP) makes a trays-
it ion to one of the following message level interface states:
(a) Result Descriptor: this state transition indicates
that the data link processor 20t is returning result descriptor
immediately without disconnection from the host computer 10.
For example, this transition is used when the DIP detects an
error in the I/O descriptor.
(b) DISCONNECT: This state transition indicates that
the Magnetic Tepidity Link Processor (MT-DLP) cannot accept
any more operations at this time and that the I/O dose_ poor
and the descriptor link were received without errors. This
state also indicates that data transfers or result descriptor
transfers can occur.
(c) IDLE: this state transition indicates that the
DIP 20t can accept another legal I/O operation immediately and
that the I/O descriptor and tile descriptor link were received
without errors.
When the operation is completed, the DIP 20t returns a
result descriptor indicating the status of the operation in the
main host system. If the DIP detects a parity error on the I/O
descriptor or the descriptor link, or if the DIP cannot recognize
the l/O descriptor it received, then the DIP cannot proceed with
execution of the operation. In this case, the DIP returns a

I 3
I
one-word result descriptor to the host. In all other cases the
DIP returns a two-word result descriptor.
The data link processor 20t is a mul-tiple-descrlptor
data link processor capable of queuing one I/O descriptor for
each magnetic tape unit to which i-t is connected. Inhere are
certain descriptors Test Cancel Test/Discontinue; and Test/ID)
which are not queued, but which can be accepted at any time by
the DIP. lest Cancel and Test/Discontinue Opus are issued against
a single magnetic tape unit in a queue dedicated to that
peripheral unit, and require that an I/O descriptor for -that
particular magnetic tape unit already be present within the
DIP. To an I/O descriptor is received and violates this rule,
the DIP immediately returns a result descriptor to the host.
This result descriptor indicates "descriptor error" and "incorrect
state".
As previously discussed in the referenced patents, the
MT~DLP utilizes the following status states (STY) transitions
when "disconnected from the host:
STY - 3 to STY - 1 IDLE to DISCONNECT
indicates that the DIP is attempting to process a queued OP.
STY = l to STY = 3 DISCONNECT to IDLE
indicates that the DIP is prepared to accept a new I/O
descriptor
STY = 3 to STY = 5 IDLE to SEND DESCRIPTOR LINK
indicates that the DIP is executing an OPT and that the DIP
requires access to the host computer.
STY = 1 to STY = 5 DISCONNECT to SEND DESCRIPTOR LINK
indicates what the DIP is executing an OPT and that the DIP
requires access to the host computer.
The DIP status states can be represented in a shorthand
notation such as STY - n.
Upon completion of an I/O operation, the data link
processor forms and sends the result descriptor to the host
system. This descriptor contains information sent by the tape
control unit 50tC to the DIP in the result status word, and also
information generated within the DIP. The result descriptor
describes the results of the attempt to execute the operation
desired

lo
I
DESCRIPTOR ~NAGEMENT
.
All communications between the DIP 20t and the host
system 10 are controlled by standard DIP status states as
described in the previously referenced patents. These status
states enable information to be transferred in an orderly
manner. When a host computer 10 connects to the DIP 20t, the
DIP can be in one of two distinct states: (a ready to receive
a new descriptor, or (b) busy.
When in STY = 3 (IDLE), the DIP can accept a new I/O
descriptor. When in STY = 1 (DISCONNECT) or in STY = 5 (SEND
DESCRIPTOR LINK), then the ALP is busy performing a previously
transferred operation.
When the DIP receives an I/O descriptor and descriptor
link that does not require immediate attention, the DIP stores
I the descriptor in its descriptor queue. The ALP is then able
to receive another I/O descriptor from the host system.
When the host system 10 "Disconnects" from the DIP 20t
after issuing one or more queued I/C descriptors, then the DIP
initiates a search of its descriptor queue. This search
continues until the DIP finds an I/O descriptor that needs
DIP attention, or until the host "reconnects" to send additional
I/O descriptors. If the DIP finds an I/O descriptor that
requires attention, and if the descriptor specifies neither a
Test/Wait for Unit Available OPT nor Test/Wait for Unit Not
Available OPT then the DIP verifies that the host is still
"disconnected". If these conditions are it., the DIP goes to
STY = 1 (DISCONNECT) and initiates execution of the descriptor.
Once the DIP goes to STY = 1, then no further I/O descriptors
are accepted from the host until the initiated operation has been
completed and a result descriptor has been returned to the host
The DIP searches its descriptor queue on a rotational
basis. The order for search is not disturbed by the receipt
of one or more new I/O descriptors, nor by the execution of
operations. This means that all queued entries are taken in
turn regardless of DIP activity and all units have equal priority.
When cleared, the DIP halts all operations in progress
with the peripherals and invalidates all the queued IT desk
critters, and returns to Status STY = 3 (IDLE).

I
DLP-DATA BUFFERS AND Dicta TRANSMISSION
_____ _
The data buffer I IT 1) of the DIP provides storage
for six blocks of data which are used in a "cyclic" manner.
Each of the six blocks holds a maximum of 512 bytes of data.
Data is transferred to or transferred from the host system one
block at a -time, via the buffer 22, followed by a longitudinal
parity word (LOW). Data is always -transferred in full blocks
(512 bytes) except for the final block of data for a particular
operation. This last block can be less than the 512 bytes, as
may be required by the particular operation.
As seen in FIG. 1, logic circuitry (-to be described
hereinafter) is used to feed information to a block counter 34c
which will register the number of blocks of data residing in
buffer 22 at any given moment. When certain conditions occur,
such as a full buffer, or empty buffer, or "n" number of blocks,
the counter 34 can set to trigger a flip-flop eye which will
signal the common control circus t unit 10c to start routines
necessary to either transfer data to the hot 10 (after
reconnecting to the host) or to get data from the host 10 to
-transfer to the buffer 22i or else the unit 10c can arrange to
connect the DIP 20t to the peripheral (as tape control unit
50tc) for receipt of data or for transmission of data.
During a Write operation, the block counter 34c counts
the number of blocks of data received from the host system 10.
The data link processor "disconnects" from the host system
once the DIP has received six buffers; or it will disconnect
upon receipt of the "Terminate" command from the host system
(a Terminate indicates the "end" of the Wrote data for that
entire I/O operation). After disconnecting prom the host, the
data link processor connects to the peripheral tape control
unit (TCU 50tc) Once proper connection is established between
the data link processor and the tape subsystem, the data link
processor activates logic which allows the tape control unit
50tC a direct access to the DLR RAM buffer 22 for use in data
transfers.
After the data link processor has transmitted one block
of data to the tape control unit, the data link processor
attempts to "reconnect" to the host system by means of a "poll
request" (as long as the host 10 has not "terminated" the opera-
lion). Once this reconnection it established, the host transfers

I
g
additional data to the data link processor. This transfer continues until either the six blocks of RAY buffer memory 22 are again
full (a buffer which is in the process of briny transferred to the
tape control unit is considered full during this procedu~~j, or
until the host 10 sends a "Terminate" commando Data transfer opt
orations between the data link processor 20t and the tape control
unit 50tC continue simultaneously with the host data transfers
occurring between host 10 and DIP 20t (via the buffer 22).
If the data link processor has not successfully reconnected
to the host before the DIP has transmit-ted, for example, three
blocks of data to the tape control unit 50t the data link pro-
censor sets "emergency request" on the data link interface 20i,
FIX. 1. If the "emergency request" is not successfully serviced
before the ALP has only one block of data remaining for transmit-
soon to the tape control unit, the data link processor sets block Error" condition by signal from flip-flop eye to circuit
10C. This is reported to the host system as a "host access error"
in the result descriptor.
The last block of data for any given I/O operation is trays-
furred to the tape control unit 50t directly under micro-code
control. During a "Read" operation, the data link processor first
attempts to connect to the tape control unit 50tC. Once a success-
fur connection is accomplished, the data link processor initiates
logic to begin accepting data from the tape subsystem Once the
data link processor has received two blocks of data (or once the
DIP receives all the data from the operation if the total length is
less than two blocks), the data link processor attempts to connect
to the host using a "poll request". The data link processor con-
tinges to accept tape data while at the same lime affecting this
host connection.
If the host does not respond to the "poll request" before
four blocks of data are present in the DO RAM buffer 22, the data
link processor sets "emergency request" on -the data link interface
20i. If no connection to the host system is effectuated before awl
I of the six RAM buffers are filled, then the data link processor sets
"host access error" in the result descriptor.
Once the host system answers a "poll request", the data link
processor 20t starts to send data to the host system 10 while at
the same time continuing to receive data from the -tape

- 10--
control unit 50tco After the host 10, FIG. 2, has received one
block of data, the data link processor checks whether or not two
full blocks of data remain to be -transferred to the host. If
this is so, the DIP uses a "break enable". If _. wreak enable"
request is granted, then transmission of the next data buffer
to the host continues to occur. If there are less than two full
blocks of data in the RAM buffer 22 (or if the "break enable" is
refused), the data link processor disconnects from -the host and
waits for two full hocks of data to be p~esent.If a "break enable"
is refused, the data link processor initiates another "poll
request" immediately after disconnection.
When the data link processor has completed data transfer,
the tape control unit 50t enters the result phase and sends
two words of result status to the data link processor 20t. The
DIP when in~orpoxates this information, plus any internal result
flags, into the result descriptor which the DIP then sends to
the host.
DESCRIPTION OF PREFERRED EMBODIMENTS
Referring to FIG. 2, the overall system diagram is shown
whereby a host computer 10 is connected through an I/O subsystem
to a peripheral unit, here, for illustrative purposes, shown
as a tape control unit 50t . This tape control unit (TCU) is
used to manage connection to a plurality of Magnetic Tape Unit
(MU) peripherals. As per previous descriptions in the above
cited patents which were included by reference, the I/O subsystem
may consist of a base "Doyle which supports one or more
peripheral-controllers, in addition to other connection and
distribution circuitry such as the distribution control circuit
ode and the data link interface 20i. The peripheral-controller
20t is shown in modular form as being composed of a common front
end circuit 10c and a peripheral dependent circuit shown, in
this case, as being composed of two peripheral dependent boards
designated 80p1 and 80p2.
In this network situation, it is often desired that data
from the main host computer be transferred on to a peripheral
unit, such as a magnetic tape unit, for recording on tape. This
would be done via a peripheral tape control unit TCU such as
50tC. Likewise, at times it is desired that data from the
magnetic tape unit be passed through the tape control unit to be

I

read out by the host computer. Thus, data is transferred in a
bidirectional sense, -Thea is, in two directions at various times
in the activities of the network.
The key monitoring and control unit is the data link
processor 20t which when initiated by specific commands of
the host computer will arrange for the transfer of the desired
data in the desired direction.
As seen in FIG. 1, the RAM buffer 22 is used for temporary
storage of data being transferred between peripherals and the
main host computer. In the preferred embodiment this RAM buffer
has the capability of storing at least six "blocks" of data,
each block of which consists of 256 words.
Again referring to FIG. 1, a block counter logic unit
33c is used to receive input from two address registers design
noted as the per furl address register, P and the system
address register, S . The peripheral address register, Pa,
handles addresses required when data is retrieved from the
peripheral tape unit or when data is being sent to the peripheral
tape unit. The system address register, S , is used when data
is being received from the host system into the buffer 22 when
data is being sent to the host system from the buffer 22. These
two address registers in FIG. 1 are seen to receive their
address data via microcode signals from the common front end
circuit 10c of FIG. 1.
The address data outputs from Pa and Spa are fed to the
RAM buffer 22 in order to address the desired location in the
buffer memory. Further, the block counter logic unit 33c
receive one input designated "P Carry" from the peripheral
address register and another input "S Carry" from the system
address register, in addition to a Read/Write control signal
from read-write flip-flop 33f. The flip-flop 33f is controlled
by microcode signals from the peripheral-controller common
front end unit 10 . The block counter logic unit 33 provides
a first logic signal LSl and a second logic signal Lo which are
fed to OR gates Go and Go These gates also have additional
inputs from the microcode of the common front end card 10c which
inputs can be used to simulate the LSl and Lo signals for
diagnostic or other control purposes. The OR gates provide two
output signals designated So and So which are fed to the block

I
~12-
counter 34 . As will be seen in FIG. 3, the output signals
So and So are combined at certain tires on occurrence of
rising clock signals in order to provide conditions which will
make the block counter either "shy C' It" or "swift down" or
"no shift".
Referring to FIG 3/ there is seen a schematic drawing
which illustrates the use of the block counter 34 of Fog 1
Referring to FIG 3, there is seen, schematically, an
eight bit shift register which will be affected at selected
points in lime where the clock signal is in its "rising" state
as illustrated by the arrows shown in FIG 3. Referring to
the leftmost schematic of the shift register, it will be Sue
that there are two "ones" which illustrate that the RAM buffer
22 has been loaded with two full blocs of data. At time To
it will be seen that conditions are such that "no shift" has
occurred and the two "ones" remain in the shift register. At
time To there is a "shift up" and the shift register now has
three bits with -the "1" signal. it time To there is a "shift
down" signal and the shift register is back where two bit
positions include a "1". At time To there is a "shift up" and
the shift register now has three bit positions manifesting the
"1" signal, which indicates three full blocks of data residing
in buffet I at that moment.
Referring to FIG. 4, there is seen a chart whereby the
block counter logic unit 33c is organized to show overall
operating conditions. Thus, as seen in the FIG. 4 chart, the
conditions of the S Carry and P Carry during the "Read" condition
show that there is a no shift or no change when S Carry and P
Carry are the same, that is to say they are both 0 or they are
both 1.
However, when S Carry is "0" and the P Carry is equal
to "1", then there is an up shift, while if the S Carry is "1"
and the P Carry is "0", there is a down shift during "Read"
operations.
Referring to FIG. 4, it is seen that during "Write" opt
orations, again when the S Carry and the P. Carry are equal
both "0" or both "1") to each other, -then there is no change

I 57~
-13-
or shift in the shift register. However, when the S Carry
equals "0" and the P Carry equals "1" there is a down shift
in this situation, and when the S Carry is equal to "1" and
the P Carry is equal to "0" there is an up shift.
The block counter 34 will reflect the situation that
when data is being taken out of the magnetic tape unit in order
to be fed to RAM buffer 22 ("Read" operation), the block counter
will shift up unless at the same time -there is data being
removed from buffer 22 for transfer to the main host computer
system in which case the block counter will shift down. Thus,
the condition of the block counter's numerical status will
indicate the "balance" between what data has gone ought of and
what data has come into the buffer 22.
Referring to FIG. 4, if there is a "Write" operation, this
determines that data is to be written into the magnetic tape
unit. Then, as data is removed from the RUM buffer over to the
magnetic tape unit, the block counter will shift down but if
more data is transferred from the main host computer into the
RAM buffer 22, the block counter will be shifted up. Thus, again
the placement of "ones" in various bit positions provides a
running balance of the data blocks taken out as against the data
blocks taken in at any given period.
Referring to FIG. 4 there are certain logic equations
which indicate the logic used in the block counter logic unit 33c
In the hollowing logic equations it should be indicated
to the asterisk refers to AND logic operation while the plus
sign refers to OR logic operation.
pa) If signal counter So equals "1" and signal So equals
"0", there occurs what may he called a condition of "Up enable"
which is equal to (Read * S Carry * P Carry) + (Write * S Carry
P Carry).
(b) Under the conditions where the signal So equals "0"
and the signal So equals "1", this could be considered as a "Down
enable" which is equal to (Read * S Carry * P Carry) + (Write *
S Carry * P Carry).
(c) In the condition where the signal So equals "0" and
the signal So equals "0", there is the condition called "no change".
This is equal to (Read * S Carry * P Carry) + (Write * S Carry *
P Carry).

l I 7 3
-14-
(d) The condition known as the "host access error", H
causes the setting of a flip-flop 34 , FIG 1. (This is also
called a block counter error). Thus, the host access error
signal or block course- error signal is a result of:
He = (Read * 6 BLACKFLY) -I (Write * 1 BACKFILL).
Thus, on a Read operation, a full PAM buffer (six blocks
of data) will signal an error condition.
Likewise, on a Write operation, a single (one) remaining
block of data will trigger an error condition.
Referring to FIG. PA, a schematic drawing of the block
counter 34c is shown to indicate that when a "1" resides in a
series of bit positions, it is an indication Dow many blocks
of data reside in the RAM buffer 22 (FIG. 1).
For example, if a lo resides in each of bit positions
lo 1, 2, 3, 4, this indicates that "4 blocks" of data reside in
RAM 22. Each "block" consists of 256 words (512 bytes of eight
bits each).
In FIG. 5B the chart illustrates that during "Read"
operations:
(a) us the P Carry increases data being transferred from
peripheral tape to buffer memory 22), the block counter 34c will
"shift up" indicating the buffer is being "loaded".
(b) As the S Carry increases (data from buffer memory
being transferred to main host system), the block counter 34c
will "shift down" indicating the buffer memory is being "emptied".
In JIG. 5B the chart illustrates that during "Wright"
operations:
(c) As S Carry increases (data being loaded in buffer
memory from main host system), the block counter 34c will "shift
up" to indicate the number of blocks of data in the buffer.
(d) As P Carry increases (data in buffer being unloaded
for transfer to peripheral tape unit), the block counter 34
will "shift down" and show how much data is left remaining in
buffer I
In FIG. 5B, during "Read" operations, when a "1" appears
in the Thea bit position of block counter 34c' then a flip-flop
circuit 34 (FIG. 1) is "set" and provides a signal to the
coon front end circuit 10c which will inform the main system
of an "access-error" condition. This signifies that -the buffer

-15-
memory 22 was "overfilled" in that the main host system dip not
accept data quickly enough.
During "Wrote" operations, when -the buffer memory 22 has
received six s of data from -the host system, and the sty
bit position (1 BLACKFLY) becomes "0", this indicates that the
huller memory has been completely unloaded (cleared) and -then
the flip-flop eye is set to signal -the common front end circuit
10c that more data is required from the host. Issue indicates
the host did not supply data quickly enough to the RAM buffer I
There has been thus described a system for the control of
data transfers which is sensitive to the condition of the
data-in-transit residing in a RAM buffet Myra and by which
it is possible to monitor blocks of data being transferred be-
tweet peripheral units and a main host computer when there are
I simultaneous flows of data being put into or taken out of the
RAM buffer means.
While the disclosure herein illustrates one embodiment of
the described system, the described system is not to be deemed
limited to but rather to embrace those systems as defined in
the following claims.