Note: Descriptions are shown in the official language in which they were submitted.
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The invention relates to a system for transmitting digital
information-signals, more particularly for digital transmission through
satellites, wherein the data-sequences are arranged in a frame chronologically
one after the other, a synchronizing word with several bits being transmitted
at the start of a limited data-sequence.
In a bit-series data-transmission, the data-blocks, consisting of
code-words, namely frames and possibly part-frames, are periodically repeated.
If the data-blocks are to be correctly decoded, the chronological position of
the frame must be known. If self-synchronizing codes are used, the band-width
of the transmission is increased by increased redundancy requirements. A so-
called point-code prevents any appreciable increase in band-width. Especially
in the case of a 4-phase CPSK modulation, data-regeneration is ensured by a
point-code on the basis of the frame-structure.
In this connection, each transmission-block contains a prefixed code-
word, the synchronizing word, serving to recognize synchronization. This is
generally followed by a sequence of data-code-words which also contain testing
information.
Time and amplitude-errors may arise in the transmission path under
consideration. In timing regeneration, time-errors produce so-called bit-slips.
Amplitude-errors, i.e. bit-inversions, vitiate data and synchronizing words.
Where a 4-phase CPSK modulation is used, the ambiguity of phase-demodulation
must be compensated for in the data-regeneration. The relevant literature
(BARKER, MAURY~ discloses synchronizing words in which a small number of bit-
errors in a synchronizing word do not impair unambiguous synchronizing-word
recognition.
~lowever, known synchronizing words are not suitable for the purposes
of the present inv~ntion, especially if time- and amplitude-errors occur simul-
taneously.
- 1 - ~:
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It is therefore the purpose of the invention to provide synchroniz-
ing words for transmitting digital information-signals, by means of which
recognition of the chronological position of the data-flow is improved and the
influence of time-errors, amplitude-errors and phase-ambiguity can be compen-
sated for.
According to a broad aspect of the invention there is providecl a
system for transmitting and receiving digital information signals, particularly
for digital sound transmission via satellites, wherein the data sequences are
arranged in a frame chronologically behind one another and wherein in a
receiver the frame is divided into time parallel part frames representing the
data sequences, characterized in that each part frame comprises a synchronizing
word of the same or equivalent type of equal length, that a correlator is used
for each part frame for chronological recognition, that code words are used
for synchronization, said code words comprising a definite maximum of their
autocorrelation function for the moment T = O, and that the autocorrelation
function for all moments T ~ O is quantitatively minimal.
Using the synchronizing words according to the invention makes
it possible to recognize the chronological position of the frame with sufficient
reliability. The synchronizing word is relatively short as compared with the
length of the part-frame and the redundancy associated therewith is minimal.
The synchronizing words are selected in such a manner that a synchronization
failure occurs much less frequently than an uncorrectable error in the formation,
If the synchronizing words are to be recognized at the receiving
end, the said words must be consldercd in a outstanding chronological position
in correlators. The synchronizing words according to the invention contain, in
the unshifted position of the autocorrelation function, i.e. for the moment
T = O, a pronounced maximum. The autocorrelation function eor all moments
T ~ O is quantitatively minimal.
72~
A CPSK modulation exhibits phase-ambiguity. This may lead to the
synchronizing word reaching the receiver in the inverted position. The synch-
ronizing words according to the invention therefore exhibit a very small
difference between autocorrelation function and inverted autocorrelation func-
tion. The synchronizing words may therefore also be reliably recognized in the
inverted position.
The ambiguity in CPSK demodulation may be compensated for by evaluat-
ing the correlation function, formed in the receiver, between the stored and
the received synchronizing word. The chronological position of the beginning
of the frame is determined by the result of the value determined in the correla-
tor, and of a subsequent threshold-value logic, in that the control-signals
derived from both correlators are fed to a logic circuit which is interrogated
in a specific time-window.
For the purpose of correcting time-errors, which may lead to a bit-
slip, it is proposed to check the cross-correlation function in a slightly
widened time-window. In conjunction with the position of the maximum cross-
correlation function within this time-window, an immediate conclusion can be
drawn as to the appearance and magnitude of a bit-slip, and a correction can be
made for the next frame. To this end, the cross-correlation function for the
moment T = 0 must be quantitatively greater than that for the moment T ~ O, but
this is possible only as far as a maximal number of bit-errors in the synchroniz-
ing word. The longer the synchronizing word, the greater the maximal permissible
number of bit-errors. A satisfactory compromise has been reached between the
two requirements for less redundancy and greater residual-error probability.
In the case of a synchronizing word 16 bits in length, the synchroniz-
ing words according to the invention make it possible to accept up to 3 bit-
23
errors of any kind in one synchronizing word while still maintaining unambiguous
synchronizing-word recognition. If the width of the window for checking the
synchronizing word is more than 1 bit, it must be borne in mind that the synch-
ronizing word can be impaired by bit-errors produced by the disturbed channel
and adjacent data.
With the synchronizing words according to the invention, and a
window-width of five timing pulses, bit-slips of up to ~ 2 timing steps can be
recognized by a threshold-value logic and the chronological shift can be elimi-
nated. In order to meet the criterion that synchronization failure must occur
less frequently than it is predetermined by the maximal permissible residual-
error-probability for uncorrectably impaired information, it is proposed that,
with the main frame divided into two part-frames (bit-planes A and B), the same
or an equivalent pattern of the same length be provided for synchronization in
both part-frames. With one correlator for each part-frame A and B, both synch-
ronizing words can be checked simultaneously, whereby the chronological position
of the frame can be recognized and phase-demodulation eliminated. When this
system for frame-synchronization is used, synchronization-errors occur only if
both synchronizing words are distu-rbed by four bit-errors.
The invention is described hereinafter in greater detail in conjunc-
tion with an e~ample of embodiment and the drawings attached hereto, wherein:
Figure 1 is a block circuit-diagram for evaluating the synchronizing
words in part-frames A and B;
Figure 2 is a block circuit-diagram for determining the cross-
correlation function;
Figure 3 is a bridge circuit;
Figure ~ is a table;
7~3
Figure 5 is a circuit for determining the position of the synchroniz-
ing word;
Figure 6 is a sequence-control.
Figure 1 shows a block circui~ diagram for recognizing synchronizing
words. The signal arriving at terminal 1 is fed to a 4-phase demodulator 2
~CPSK). The data-flow is divided into two bit-planes A and B. Since the
demodulation in CPSK demodulator 2 is ambiguous, signals A and B may appear
inverted or non-inverted, i.e. there are two possibilities for each bit-plane.
The data from each bit-plane are passed to shift-registers 3,4. The cross-
correlation function is formed in stages 5 and 6 by comparing the data read
into shift-register 3,4 with the synchronizing word hard-wired by a circuit
arrangement 44 ~Figure 2). Stages 5 and 6 are storage-modules which are divided
into two parts. By adding the contents of the storage-addresses called up in
adding stages 7,8, the respective value of the cross-correlation function can
be determined. A subsequent threshold-value logic 9,lO ascertains, from the
cross-correlation value fed in, whcther the sync-word, its inversion, or no
sync-word has been received. The chronological position of the synchronizing
word is determined in stage 11 and the internal frame-pulse is adjusted if
necessary. It can also be determined whether part-data-flows A and B have been
received in the inverted, non-inverted and/or transposed position. The part-
data-flows are corrected if necessary by means of bridge-circuit 12.
~igure 2 is a circuit diagram for determining the cross-correlation
function. The data-flow passes from terminal 13 in series into shift-register
3. A sequence of 16 bits lies at each of the parallel outputs from shift-
register 3. 8 bits at a time from the data-word lying at the parallel outputs
from shift-register 3 are compared, through an exclusive OR-gate 47 - 49, 50 -
52, with the corresponding part-code-word of the synchronizing word. The out-
~A.2~P;~
puts from the exclusive OR-gate are passed to a PROM (= programmable read-only
memory) 14,15. The data-pattern lying in each case at the eight outputs from
exclusive OR-gates 47 - 40, 50 - 52 provides an address in PROM-circuit 14 or
15. The contents of the PROM-circuit storage positions called up are passed to
an adder 7. Depending upon the code-word lying at the outputs from shift-
register 3, specific addresses are called up in PROM-circuits 14,15. These
call up a binary-coded storage content between - 4 and -~ 4 corresponding to the
relevant number of matches. The addition in adder 7 gives the value of the
cross-correlation func~ion (- 8 to ~ 8). The two highest-order bits of the
storage contents lying at the outputs from PROM-circuits 14,15 are passed to an
exclusive OR-gate 16. The output from exclusive OR-gate 16, and the highest-
order position of the output from adder 7, lead to another exclusive OR-gate 17,
the output from which represents the highest-order bit of the cross-correlation
value in the two's complement lying at the output from adder 7. The output from
adder 7, together with the output from exclusive OR-gate 17, constitutes the
ascertained value of the cross-correlation function represented in the two's
complement.
In this connection, the output signal from exclusive OR-gate 17 is
the highest-order bit and thus represents the sign of the cross-correlation
function.
A further PROM-circuit 18 is activated by the values at the output
from adder 7 and from exc]usive OR-gate 17.
If the address-code-words lying at PROM-circuit 18 quantitatively
exceed, in their significance, a predetermined threshold, the storage positions
pertaining thereto are identified with a logic "1". A called-up storage-content
logic "1", released from terminal 19, indicates recognition of a synchronizing
word. Whether the position is inverted or non-inverted is shown at the status
of terminal 22.
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Figure 3 shows a bridge circuit controlled by signals E and F at
terminals 22,23.
Signals E and F arrive from the correlators for bit-planes A and B
and correspond to the relevant highest-order bits in the A and B correlation-
signal. The circuit according to Figure 3 has the following structure:
C = (E.F+E.F) . (A.E-~A.E~ + (E-~+F-E) (B-F~B-F)
D = (E.F+E.F) . (B.F+B.F) ~ (E.F~E.F) (A-F+A-F)
Output signals C and D at terminals 2~ and 25 of the bridge-circuit
according to Figure 3 are produced in the case of an input-signal A and B at
terminal 20 and 21, depending upon the control-information at terminal 22 and
23. This circuit permits two data-flows to be either transposed and/or inverted
(see Figure ~).
Figure 5 shows a circuit for recognizing the position of the synch-
ronizing pattern in the frame. Signals from the storage-positions in a PROM-
circuit 18, as shown in Figure 2, are passed to terminals 19 and 27. A shift-
register 28, 29 is provided for each part-frame. Shift-registers 28, 29 each
contain 5 bit-positions, to the average values of which an AND-gate 30 is con-
nected. Also present are "strobe"-inputs 31,32. Parallel outputs from shift-
registers 28,29 run to a 102~ x ~ PROM-circuit 33. The content of the addressed
storage-positions in PROM-circuit 33 passes to an adder 3~ to which counter-
states from a pre-programmable frame-counter 26,36 are also passed. In the
example shown, each counter counts up to an address 320. As soon as the counter
has reached its end-address, a pulse is fed to load-input 37 thereof and the
counter is set back again to the pre-programmable starting state.
A signal is fed to restart-input 39 for initial search of the frame-
timing, the said signal resetting counter 36. At the same time, strobe-inputs
-- 7 --
31,32 and shift-registers 28,29 are addressed through OR-gate 40. Since the
outputs from shift-registers 28,29 run to PROM-circuit 33, a specific address
in that circuit is addressed each time. The outputs from the correlator
threshold-value logic in bit-planes A and B are connected, through terminals
l9 and 27, to the series inputs to shift-registers 28 and 29.
The position of the time-window, obtained from the sequence-control
lies at terminal 38. It is passed through STROBE-gate 40 to strobe-inputs
31,32.
The information read into shift registers 28,29, after 5 timing
pulses appear in the time-window, is then evaluated with the aid of the content
of PROM-circuit 33. The content of the stora~e-position of the address called
up tells adder 34 how far the present timing pulse is from the frame-timing.
Located in the nominal position of the synchronization pulse is the pulse in the
central cells of shift-registers 28,29. A pulse is released to terminal 41
through AND-gate 30 connected thereto. A pulse is passed, through terminal 39,
to load-input 37 through a connected evaluation logic shown in Figure 6.
Counter 36 thus begins to count again. If the nominal position is not reached,
e.g. through a bit-slip, the total in counter 36 is altered by calling up
another address in PROM-circuit 33. This causes the clock-synchronization of
the frame to shift correctly.
Figure 6 shows an evaluation logic for controlling ~he sequence of
the search-and-hold procedure. Positional information regarding the synchroniz-
ing word is passed to terminals 22,23 from the two part-frames A and B. As
soon as the synchronizing word is in its correct chronological position, input
terminal 31 receives a pulse from AWD-gate 30. The search-mode is initiated by
a state-change to logic 1 at terminal 38 leading to OR-gate 40. ~ pulse at
~L2~ 3
terminal 39 passes, through an OR-gate, to load-input 37 of counter 36 and
restarts frame-counter 36. The signal at load-input 37 also represents the
frame-timing.
PROM~circuit 33 passes a pulse to terminal 43 only if no synchroniz-
ing word is found. The pulse at termi.nal 43 passes to an OR-gate 45 to
terminal 46 of which a pulse may be passed in order to initialize the whole
circuit for the ~irst time. PROM-circuits 18 in the circuit according to
~igure 2 for both part-frames appear at terminal 42, so that the threshold
values for the cross-correlation function~ obtained with the aid of PROM-
circuits 18, may be switched over.
