Note: Descriptions are shown in the official language in which they were submitted.
The present invention relates to a semiconductor power component,
together with its method of manufacturing.
Power semiconductors, whether they are used for amplification or for
switching, must be capable of passing high currents. This presents special
problems, both concerning the structure of the component (the current density
within the semiconductor material must be limited to acceptable values) and con-
cerning the manner in which contacts are made to the different semiconductor
zones (in particular the voltage drop due to these contacts must be reduced to
a minimum).
These two requirements are generally contradictory in power semicon-
ductors: in fact, in such semiconductors, the width of the electrode which is
diffused in the surface of the substrate (ie. the emitter if a planar type semi-
conductor is taken as an example) must be relatively small since only the edge
of the diffused zone conducts current. To limit the local current density in
the junction, the component is given a so-called "interdigitated" structure, ie.
the emitter, while remaining in one piece, is given a tree and branch like or
ramified structure to increase the length of its perimeter. Contact is made at
one or more points on the emitter.
Because of the single connection via the ramified emitter, current is
badly delivered to the most distant ends of the ramifications due to voltage drops
along the various ramifications. As a result, the current density is very
uneven between regions of the emitter located close to a contact point and regions
distant therefrom. This lack of uniformity increases very rapidly with increasing
rated power for the semiconductor. Increasing the rated power requires both an
increase in the size of the component and a more complicated interdigitation
pattern in order to cover the increased area of the component. The complexity
of the pattern and the large voltage drops thus very rapidly impose an upper
limit on the power performance of such ramified emitter structures.
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To mitigate this drawback, proposals~ have been made to
divide the emitter instead of ramifying it.
In such a semiconductor struc-ture (~nown as a multi-
cellular structure), a plurality o:E ~ or P t~pe zones are
diffused on the surface of a subs-trate of P or ~ type
respectively so as to provide an ordered pattern on said
surface comprising a plurality of diffused ~ones and of 30nes
where the substrate emerges arranged in a patchwork of
alternating ~ and P ty~e cells. All the cells of each type are
connected to one another and to a common conductor which
constitutes one of the terminals of the component.
~emiconductors of this type provide better performance
than rami~ied emitter semiconductors, and this applies not only
to maximum admissible voltage, gain, cutoff frequency, and
current density in the cells, but also to the current x voltage
product at switch on.
In contrast there is a difficulty when it comes to ma~ing
the contacts~ since it is necessary both to interconnect all
the cells of the same type (since the electrode is not in one
piece as previously) and also to provide two sets of
connections (one for the emitters and the other for the bases)
instead of just one.
One proposal for doing this has been to place two
conductors on the substrate adjacent to the cells which are
arranged in the form of islands which are located along the
conductors but which are isolated therefrom. Each island is
then connected to the corresponding common conductor by a
conductor bridgec
By putting the various cells in parallel, this structure
enables the expected voltage, freguency, ..., performance to be
obtained. However, it suffers from the drawback explained
above with respect to ramified emitter structures, of poor
current distribution, particularly to the most distant cells.
~ urther, a large amount of substrate surface area is lost
to the two common conductors which must r~m along the entire
length of the cells (and any increase in conductor length
conflicts with the desired reduction in voltage drops). It
becomes impossible to make high density components or to
multiply the number of cells (and hence increase the power)
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without the size becoming prohibitive and the cutoEf frequency
being limited.
One of the aims of the invention is to provide a solution
to this problem by providing a multicellular type semiconductor
structure in which the cells of each type are interconnected with
as little loss of surface area as possible and with current being
distributed in an entirely uniform manner to all the cells in the
network.
According to a broad aspect of the invention there is pro-
vided a semiconductor power component comprising:
a semiconductor substrate of a first conductivity type compris-
ing a plurality of doped regions of a second conductivity type
opposite the first conductivity type to form a patchwork of cells
of alternating first and second conductivity types;
a lower conductive layer comprising first and second portions
insulated from each other, overlying said substrate and insulated
therefrom, said first portion being connected to the underlying
cells of the first conductivity type and said second portion being
connected to the underlying cells of the second conductivity type;
an upper conductive layer comprising first and second portions
insulated from each other and substantially overlying said first
and second portions of said lower conduc-tive layer respectively,
said first portion of said upper layer being connected to the under-
lying cells of the second conductivity type and said second portion
of said upper layer being connected to the underlying cells of the
firstconductivity type; and
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means in a frontier zone including adjacent parts of said first
and said second portions for connecting the first portion of the
lower conductive layer with the second portion of the upper con-
ductive layer and the second portion of the lower conductive layer
with the first portion of the upper conductive layer, said first and
second portions of the upper conductive layer thereby forming first
and second terminals of the component.
The two layers provide optimal parallel connection for -the
cells of each type, because there is no significant voltage drop~
This enables the number of cells to be increased while reducing
their individual size without thereby inereasing the overall size
of the eomponent. Unlike all prior solutions, there isno penalty
of increased voltage drop.
~Z~ 7~
urther, the current is applied perfectly uniformly to all
the cells thereby ensuring good frequency performance -for the
component, or extremely short switching times.
Dispensing with wasted areas -~hat only serve to convey
current, not only saves silicon, but above all it also improves
component operation by avoiding parasitic injection in the
wasted P type areas while avoiding excessive width in the N
type areas, (or vice versa).
. .
~urther, the configuration in accordance with the
invention lends itself very well to ballasting the emitters (or
even the bases), ie. to connecting a ~sl~;~or in series with
each emitter in order to equalize the currents flowing through
the emitters.
~hermal behaviour is also greatly improved b~ the very
short links between each cell and its conductive layer. Not
only are losses due to voltage drops reduced to a mini~um, with
consequent miminal Joule effect heating; but also the heat
generated at each junction can be effectively dissipated in the
conductive layer since the cell-to-layer connection is so short.
~inally, passing the two layers through each other
provides a semiconductor having two large surface electrodes
(for example) -~hich are easily connected to external circuits.
One such case consists in turning the semiconductor component
face downwards and soldering it directly to the substrate of a
hybrid circuit. Such a technique ~ould be difficult to apply to
a component having connection points at its sides rather than
on top. And in any case current would be applied less
effectively than conduction via the large surface area
electrodes of a semiconductor in accordance with the invention.
More precisely, the lower conductive layer is divided into
two half layers along a first line having a ~irst shape, the
upper layer is divided into two half layers along a second line
having a second shape, and the lines are not superposed,
whereby each upper half layer has at least one portion that
overlaps a portion of the lower half layer on the opposite side
of the frontier, and an electrical connection is made between
said half layers through said overlapping portions.
7~
Advantageously, the patchwork or multicellular structure
is periodic in at least one direction parallel to the frontier, in
which case the first shape is a regular shape having a pitch equal
to the patchwork m~sh and the second shape is identical to the first,
and is symmetrically disposed thereto about the axis f'f of the
frontier zone.
Preferably an insulating third layer is also provided on
the surface of the component, said third layer including bared por-
tions of large area which form contact poin-ts for connecting the
component's electrodes to external circuits.
The method of manufacturing a component in accordance with
the invention comprises the steps of:
Providing a substrate of a first conductivity type a method
of manufacturing a semiconductor power component, comprising the
st~ps of:
providing a substrate of a first conductivity type, and doping
a plurality of regions with impurities of a second conductivity
type opposite the first conductivity type at predetermined locations
of the substrate to form a patchwork of cells of a:Lternating first
0 and second conductivity type:
forming a first insulating layer on said substrate:
forming openings through the first insulating layer over at
least a number of said plurality of cells:
depositing a first conductive layer interconnecting said exposed
cells:
patterning said first conductive layer to form conductive is-
lands over selected one of said openings and to divide said first
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eonductive ].ayer into first and seeond portions insulated from
each other by a first groove, the islands whlch are surrounded by
said first portion being formed over exposed cells of the second
conductivity type and the islands which are surrounded by said
seeond portion being formed over exposed eells of the first eon-
ductivity type, said first and second portions thereby remaini.ng
conneeted to the exposed cells of the first and second eonductivi-ty
type respectively
forming a second insulating layer on said first eonduetive
0 layer:
removing the second insulating layer from the tops of said
islands, and exposing addi.tional regions of said first conduetive
layer on either side of the first groove:
depositing a seeond conductive layer for interconnecting said
islands: and
patterning the second conductive layer to divide said second
conduetive layer by a second groove into first and seeond portions
substantially overlying the first and seeond portions respeetively
of said first eonduetive layer sueh that the first portion of said
second conduetive layer has at least one region overlapping a re-
gion of the seeond portion of said first eonduetive layer and the
seeond portion of said seeond eonduetive layer has at least one
region overlapping a region of the first portion of said first
eonduetive layer, said overlapping regions including said exposed
additional regions.
7~.
Advantageously the method includes final steps of:
depositing a third insulating layer over the entire surface of
the component; and
removing said third insulating layer from large extents of said
surface in such a manner as to provide contact regions for making
subsequent connections between the component and ex-ternal circuits.
Although -the following description concerns a bipolar
transistor made according to the teaching of the present invention,
the invention is not limited to this type of semiconductor compon-
ent and also covers, in particular, triggerable semiconductor com-
ponents such as thyristors or triacs; in which case the cathode and
the gate of the triggerable component correspond respectively to
the emitter and the base of the transistor.
More generally, the invention provides a method of ma~ing
integrated connection points and is applicable wherever to series of
distinct elementary zones formed on the surface of a substrate are
to be connected in parallel.
Other characteristics and advantages of the invention will
appear on reading the following detailed description which is made
with reference to the accompanying drawings, in which:
~igures 1 to 3a show different stages in the manufacture
of a component in accordance with the invention, they are
sections in vertical planes defined in ~igures 9 to 13 by lines
xx' (for ~igures 1 to 8) and yy' (for ~igures 4a to 8a);
~igure 9 ls a plan view of a component substra-te in which
different semiconductor zones have been diffused to form a
patchwork of cells;
~igures 10 to 13 show the different masks used in
succession during manufacture of the component;
~igure 1~r is ~1 overall perspectlve view of a completed
component;
~igure 15 is an elevation of the same component mounted
face-down on a hybrid circuit substrate;
~igures 16 to 18 are variants of ~igure 9 showing
different patchwork patterns;
~ igure 19 is a plan view o~ a wafer on which a plurality
of different components are -to be manufactured simultaneously;
and
~ igure 20 is a variant of ~igure 1~ showing a semi-
conductor having two frontier zones.
~ y way of example, the following description concerns themanufacture of a bipolar ~P~ transistor in accordance with the
invention. In this case, and as can be seen in ~igure 1, the
substrate 10 is P type and a plurality of N type zones 11 are
diffused therein. ~he diffused zones 11 and the zones 12 where
the substrate emerges are distributed in suc'n a manner as to
form a patchwork of individual cells which are alternately
type and P type, as can be seen in ~igure 9 which shows a
checkerboard pattern of square cells of identical size. 3y
convention, the unshaded areas represent P type cells and the
darkly shaded areas represent ~ type cells. ~he pattern
described here ~s thus a periodic patchwork of mesh a (ie.
twice the side of a cell) in two orthogonal directions.
~or example, the cell squares may be chosen to be of side
a/2 equal to about 70 ~m, with the number of cells being
determined as a function of the component's power rating 9 eg.
2000 cells for a 10 A transistor, which corresponds to a
current of a~out 5 mA per individual cell.
7~
It is not necessary to use a patchwork which is a regular
pattern of square cells, and mlmerous patterns may be
applicable, eg. alternating juxtaposed P type and N type
strips, or a honeycomb pattern of hexagonal cells (an example
of which is described below with reference to ~lgure 16).
~ he patchwork is then covered with a uniform insulating
layer 20, eg. made of silicon o~ide. Then (see Fi~ure 2), a series of
openings 21 or 22 are made in the insulating layer, with one
opening per cell. In -the example being described of` square
cells of side 70 ~m, the openings may9 for example, be circu]ar
with a diameter D1 of about 10 ~m.
Figure 10 shows a mas~ suitable for making the openings.
In this figure, as in figures 11, 12 ard 13, and by convention7
lightly shaded areas represent portions of the mask situated
over ~ type regions of the patchwork (even though such areas
are transparent) and unshaded areas are portions of the mask
situated over P type regions of the patchwork. Darkly shaded
~arks correspond to regions of the substrate (or overlying
layers) which are to be etched eg. by the conventional method
of applying a photosensitive resin and then engraving chemically.
The openings may be made, for example, using round marks
21a and 22a on the mask.
Reference Z~ corresponds to a frontier zone defined on
ei-ther side of an axis f'f which divides the component into two
regions ZB and Z3. As is described below, the N type cells in
each of these regions are interconnected by the same operation
as interconnects the P type cells in the other region, and
vice versa.
-
At this stage of the method, the two regions Z3 and Z~ are
still indistiguishable, with all of the cells in the patchworkoutside the frontier zone being provided with an opening 21.
In the frontier zone Z~, it is very advantageous to provide
openings 22 leading to the cells thereof, particularly in the
pattern shown where the frontier zone is a straight line of
single cell width (ie. the width of the frontier zone is equal
to half the patchwork mesh, thereby enabling cell type to be
inverted on elther side of the frontier zone). Additional
7~
openings 22 (corresponding to marks 22a on the mask) are thus
provided in the frontier zone for each of its cells.
In the next step, (see ~igure 3), a irst ^onductive
layer 30 ïs deposited over the entire component; this flrst
layer ~which is also referred to æs the lower layer)
thus interconnects all the cell~ of -the patchwork via the
openings 21 and 22 made in the previous step. ~his first
conductive layer may be made of aluminum, for example.
In the next step of the method, shown in ~igures 4 and 4a
(where igure 4 is a section along a line xx' and ~igure 4a
along a line yy', said sections being spaced at half the
patchwor~ mesh), said lower layer is etched.
~ irstly, studs 31 are isolated on top of each N type cell
in the region Z~ and on top of each P type cell in the region
ZB- ~he studs or islands 31 are provided by routing annular
grooves 32, eg. with an inside diameter of D2 o~ 20,um and an
out~Qide diameter D3 of 50 ~m. Each groove is formed through
the en~ire thickness of the conductive layer so as to lay bare
the insulating layer 20. ~hus, in the region Z~ all the P type
cells are electrically interconnected by the first layer, while
all the ~ type zones are isolated (and vice versa for the
region ZB).
~ he routing is performed by means of a mask shown in
~igure 11 and comprising opaque rings 32a which are placed over
the P type areas of the region Z~ and the ~ type areas of the
region Z~.
Secondly, during the same step of the method, an
uninterrupted groove 33 is formed to split the first conductive
layer along the frontier zone Z~ into two half layers which are
insulated from each othsr and each of which covers a
corresponding one of the regions Z~ and Z~.
~ he groove 33 is not straight. It is sinuous with a
period a that is preferably equal to the mesh of the patchwork.
In other words, in the example being described, it has a
sinuous pattern which repeats with a period equal to twice the
width of a cell.
In the figures, the groove 33 (which corresponds -to a mark
33a on the ~igure 11 mask) is roughly sinusoidal in shape,
being in the form of a series of alternating semicircles having
an inside radius R1 of about 25 ~m and an outside radius R2 of
about 45 ~um.
In practice~ the exact shape of the groove 33 is
unimportant, and many sinuous shapes may be used, including
rounded or angular shapes. ~he essential condition is that the
groove defines an alternating series of salient areas 34 and
34' belonging alternately to one or the other of the two half-
layers. ~he areas 34 belong to the nalf-layer on the region Z~
and are thus all in contact with P type areas thereof (future
bases of the trænsistor), while the areas 34' belong to the
half-layer on the region ZB and are thus connected to all the N
type cells thereof (future emitters of the transistor).
~he next step in the method (~igures 5 and 5a) consists in
covering the first layer 30 (after it has been etched as
described above) with a uniform insulating layer 40, eg. of
silicon oxide.
During the next step (shown in ~'igures 6 and 6a), the tops
41 of each of the previously routed out islands 31 are
uncovered by etching the insulating layer 40 on said islandsO
At the same time, additional openings 42 and 42' are uncovered
along the frontier zone Z~ on either side of the groove 33
running therealong. ~he openings referenced 42 correspond to
the salients of the lower half-layer covering the region ZE,
while the openings referenced 42' correspond to the salients of
the lower half-layer covering the region Z~.
~igure 12 shows an example of a suitable mask for
performing the above uncovering operation. Opaque areas 41a
having a diame-ter D4 of about 20 ,um in the present example,
serve to uncover the islands which make contact with the N type
cel1s of the region ZB (future emitters of the transistor) and
with the P type cells in the region ZB (future bases of the
transistor). Opaque areas 42a and 42'a having a diameter D5 of
abou, 40 ~lm correspond respectively to the openings 42 ar,d 42'
which are made alternately through the lower half-layer
~2~;~7~
1 1
covering the region ZE and through the lower half-layer
covering the region ZB. The posit:ion of the firs-t sinuous
groove 33 in the lower layer is indicated by dashed lines 33a.
A second conductive layer 50 is then uniformly deposited
over the entire component (see ~igures 7 and 7a). ~he second
conductive layer (referred to as the upper layer or sheet) thus
electrically interconne,cts all the islands 31 of the component
together with all the additional openings 42 and 42' as
provided in the preceding step.
The last step of the method (see ~igures 8 and 8a)
consists in dividing the second conductive layer along the
frontier zone ZF by means of a second sinuous groove 53 made
through the entire thic~ness of the second conductive layer.
The second sinuous groove 53 thus divides the upper layer into
two mutually isolæted half-layers. ~he second sinuous groove
53 is not superposed on the ~`irst sinuous groove 33, in such a
manner that the upper conductive half-layer on each side o~ the
frontier zone is connected to the lower conductive half-layer
on the other side via at least one of the previously prepared
additional openings. For example, in ~igure 8, the lower half-
layer covering the r0gion ZE has a salient 34 ~-hich overlaps a
salient 54 of the upper half layer covering the region ZB, and
the overlapping salients are interconnected via an opening 420
These two half-layers are thus electrically connected together.
Given that the lower half layer covering the region Z~ inter-
connects all the P type cells thereof via the openings 21 and
that the upper half-layer covering the region ZB interconnects
all the P type cells thereof via the islands 31, it can readily
~e seen that the P type cells of the component (including the
3 cells under the openings 42) are all connected together in
parallel and to the upper half-layer covering the region ZB.
~his half-layer thus con~titutes the base electrode of the
componentO
By reasons of symmetry, the upper half-layer covering the
region ZE constitutes the emitter electrode of the component by
interconnecting all the N type cells of the patchwor~. In
particular, the emitter upper half-layer has salients 54' which
12
overlap and are in contact with sa] ients 34' of the emitter
lower half-electrode which covers t;he region ZB and is n
contact with all -the N type cell~ thereof. It should also be
oberved that the ~ type cells under the openings 42' are
likewise connected to the emitter conductive half-layers.
~igure 1~ shows an example of a mask suitable for maki ng
the second sinuous groove 53. It can be seen that the corres-
ponding mark 53a is symmetrical about the frontier zone axis
f'I to the mark 33a which was used to make the first sinuous
1 0 groove.
~he resulting component 100 shown diagrammatically in
~igure 14 thus includes, on either side of the frontier zone Z~
which divides it into two halves, an upper surface (the second
conductive layer 50) which is divided into two large extents
50e and 50b respectively constituting the emitter electrode and
the base electrode of the component. ~he electrode 50e is
connected to all the ~ type regions of the l?atchwork (including
those located in vhe zone Z~ and in the region Z~3) and the
electrode 50b is connected to all the P type cells in the
patchwork (including those located in the zone Z~ and in the
region Z~ his result is obtained by the way the two layers
overlap in the frontier zone Z~. As can be seen, the proposed
structure for the frontier zone enables the two layers to cross
connect within the zone without significantly lengthening
current paths (unlike interdigitated structures) and thus
without significant drop in voltage.
Preferably, a third insula-ting layer 60 is deposited over
tne entire surface of the component (see ~lgure 14) through
which holes 61 and 62 OI large area are made to uncover only
those portions of the surface of the electrodes 50e and 50b
which are subsequently _overed with solder when making
connections to outside circuits. The unsoldered portions of
the second conductive layer are thus protected from the
environment.
Further, t'ne final structure with two large electrode
contact areas makes it possible to mount the component face
downwards on the substrate of a hybrid circuit. ~his arrangement
13
is shown in ~igure 15. The component 100 of ~igure 14 is
turned over. Its substrate 10 is thus facing upwards, ~hile
its contact areas on the electrodes 50e and 50b are connected
to marks 201 and 202 formed on the sur-face of a hybrid circuit
substrate 200. This enables contact to be made over substantially
the entire surface of each of the two electrodes 5Ce and 50b,
ieO over about half the total area of the component in each
case. Current can thus be distributed optimally ~o the
component with minimum voltage losses at the connection.
It is mentioned above that the checkerboard patchwork
described ~y way of example is not the only ima~inable
configuration. ~igure 16 shows another example in which the
cells are hexagonal and form a honeycomb patchwork. In the
example shown, each P type cell is surrounded by six ~ type
cells. This results in there being twice as many ~ type cells
as there are P type cells. One type of cell can thus be given
preference over the other, which is advantageous in particular
when the tra~sistor is used as a power amplifier. In s-uch a
case, the average emitter current is always greater than the
average base current, and it is thus desirable to give
preference to emitter cells over base cells. In contrast, when
a semiconductor is used as a switch, the average base current
is of substantially the same order as the average emitter
current, in which case it is preferable for base cells and
emitter cells to be equally represented in the patchwork, as in
the case of the checkerboard patchwork described above or of a
patchwork in the form of identical strips~
In the ~igure 16 configuration, the mesh in a direction
f1'f1 is three cells: the grooves diYiding each layer into half
layers thus has a pattern which is periodic every three cells.
The lower groove is marked 33' and the upper groove is marked
53'. ~t can be seen that the two grooves are symmetrical about
the axis f1'f1. Eowever, there is no need for the symmetry
to be perfect; the essential point is that salients from each
layer overlap. The configuration shown nonetheless minimizes
voltage drops where the two layers are interconnected.
~2~
~4
It will be observed that for a hexagonal patchwork, a
second axis f2'f2 can also be used to define the frontier
with correspcnding grooves 33" and 53". However, it will also
be observed that in this case the grooves are periodic with a
pitch o-f two cells and that they are not sy-mmetrical to each
other which i~ due to the fact tha-t there are as many P type
cells in the second frontier zone as there are ~ -type cells,
unlike the first frontier zone where there are two ~ type cells
per P type cell, a ratio which corresponds to the overall ratio
of the component.
Figure l7 shows a variant of the Figure 9 patchwork. In
this variant the P type areas l2 (base areas) are no longer
square, but are circular with a diameter of a/2. ~his
configuration is geometrically advantageous over the hexagonal
con~iguration while retaining the feature of a total emitter
surface area which greater tnan the base surface area.
It will be observed that in this case, the grooves 33a and
53a dividing each layer into two half-layers may be of exactly
the same shape as described with reference to ~igure 9.
~igure l8 shows another variant patchwork in which the N
type cells are also given preference over the P type cells 7
which in this case are in the form of small squares.
Another advantage of the structure in accordance with the
invention is that it enables components of different ratings
(maximum admissible current) to be obtained without modifying
the masks and using a single diffusion batch.
A large number of components are made in conven'ional
manner on a single wafer 300 of silicon (shown diagrammatically
in ~igure l9) which is then cut up into individual components.
~o make components in accordance with the invention, a
plurality of frontier ~ones f'lfl, f'2f2, ~ , f'n-lfn-l~ f'nfn
are defined on the wafer. After performing the various steps
of the method, the top layer of the wafer as a whole is divided
into alternating emitter rgions ZE and base regions Z~.
Individual components such as lO0 and lO3 can then be cut out
from these regions on either side of the frontier zones.
One of the advantages provided by the invention is the
possibilit~ of choosing the rating of each individual component
at the moment it is cut out simply by choosing the length of
the region to be cut out. ~hus, for example, if component 100
of length l1 is rated at 5 A, a 10 A or a 15 A component 101
is obtained by cut-ting out a portion of length 12 which two
- or three times the length l1- This increase in rating is
made possible by the fact that the number of cells in the
patchwork is proportional to the size of the component and that
an increase in rating merely requires an increase in the number
of cellsO This is not true of interdigitated structures for
which complexity increases much more rapidly than size.
It is also possible to cut out from the same wafer a
component such as the component 102 which has a plurality of
~rontier zones, eg. two. This component is shown in more
detail in ~igure 20. It has a central emitter region Z~ in
between two base regions Z~1 and Z~2 The upper and lower
layers th~s pass through each other twice, once in each of the
frontier zones Z~1 and Z~2 This structure is advantageous
for very high power "double-base" semiconductors.
It can thus be seen that a single diffusion batch is
capable of providing an entire range of components, simply by
choosing the size of component to be cut out. This is in
contrast to prior art structures in which it is necessary to
define the desired rating from the outset, and thus the size of
the component, and to make a set of masks specifically for each
rating.
In a variant, the wafer 300 may be provided with strips Z~
and Z~ of dif~erent widths, thereby giving rise to components
after cutting out having base and emitter contact zones of
different sizes. This variant is applicable in particular when
one type of electrode is to be given preference over the other.
