Note: Descriptions are shown in the official language in which they were submitted.
~19337
-1- RCA 7~,994/80,596
REDUC~D-NOISE CCD CAMERA WITH
SINGLE-SAMPLED OUTPUT
The present invention relates to reducing noise
accompanying the image response of a CCD camera, while
avoiding double sampling.
BACKG~OUND OF THE INVENTION
In this text, description of a charge transfer
device uses the following convention: a semiconductor
substrate surface, on which gate el~ctrodes of the device
are disposed, is described as the device's "top" surface,
even though the gate electrodes actually may be
differently oriented with respect to the substrate
surface. Additionally, words, such as "under" and "over",
are used in the text in accordance with this convention.
Typically, a floating diffusion output stage of
a CCD incorpcrates a metal-insulator-semiconductor field
effect transistor ~MISFET) having a gate electrode
connected to the floating diffusion. The transistor is
operated in common-drain (or common-source) configuration
as an electrometer, in order to measure the potential on
the floating diffusion. This potential is indicative of
charge in a potential well "under" the floating diffusion.
The potential m~asurements takes place during respective
signal-sampling intervals, which are interspersed by reset
intervals.
During such a reset interval, the floating
diffusion is clamped b~ MISFET action to a reference
potential at a reset drain. More particularly, the
floating diffusion is a virtual source in this MISFET,
action, and the MISFET action occurs in response to
potential applied to a reset gate electrode, which is
disposed between the floating diffusion and the reset
drain. It is accepted practice to interpose an additionai
gate electrode between the floating diffusion and the
reset electrode and to apply direct potential to this
additional gate electrode, in order to prevent potential
1219337
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responses to the reset pulses from being induced on the
floating diffusion.
The resetting process of periodically clamping
the floating diffusion to the potential at the reset drain
is undesirably accompanied by a type of noise called
"reset" noise. Reset noise arises as variations in the
potential left upon the floating diffusion from one reset
interval to another. Reset noise is a problem in charge
transfer devices having floating-gate output stages, as
well as ones with floating-diffusion output stages. Reset
noise is the predominant noise in the upper-video
frequencies of the output signals of charge transfer
devices such as CCD imagers. Reset noise typically is
about 8 dB larger than noise in the MISFET electrometer
stage following the floating diffusion. At lower video
frequencies, flicker (or "1/f") noise predominates.
Flicker noise arises in the MISFET electrometer stage.
It is known to supply the imager output signals
to a sample-and-hold circuit. Such a circuit samples
during the sample intervals in the imager output signal
and then holds the samples through the intervals between
samples. The response of ~he sampl~ and hold circuit has
increased baseband (or first harmonic spectral) content
and decreased higher harmonic spectral content, as
compared to the imager output signal it receives. The
duty factors of the imager output signal and of noise
admixed during subsequent amplification processes are made
alike through sampling and holding. Consequently,
signal-to-noise does not suffer as greatly during such
amplification. This procedure is denominated "single
sampling" in this disclosure.
The desire to reduce both flicker and reset
noise has led to the practice of correlated double
sampling. In this procedure, in each clocking cycle of
the CC~ imager output register, the signal on the floating
diffusion is sampled a first time when charge dependent
upon reset noise, but not upon signal, is present in the
potential well induced "under" the floating diffusion.
1~19337
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The signal is then sampled a second time when charge
dependent upon both that reset noise and signal is present
on the floating diffusion. Each pair of samples is then
differentially combined to generate samples dependent
substantially only on signal, with reset noise being
suppressed.
Correlated double sampling becomes less
practical as the sampling rate of the charge transfer
device output stage increases. Pulse widths become
narrower, and pulse spacing is lessened towards the limit
imposed by the time needed for charge equilibration under
the floating-diffusion or floating-gate output. As output
register clock rate rises to more than a few megahertz,
the correlated double sampling technique becomes difficult
to employ. The inventor has observed that although with
correlated double sampling 20db noise xeduction is
obtainable at 100 kHz clock rate in an imager system, at a
clock rate of 1 MHz more than three to six dB noise
reduction is obtained only with difficulty.
L.N. Davy in his United States Patent No.
4,330,753 issued 18 May 1982 and entitled "METHOD AND
APPARATUS FOR RECOVERING SIGNAL FROM A CHARGE TRANSFER
DEVICE" describes a method for obtaining information
signals, which he characterizes as relatively noise-free,
from the output stage of a charge transfer device. In the
method Davy describes, the output signal from the
regularly-sampling electrometer stage is passed through a
band-pass filter to separate double-sideband
amplitude-modulation sidebands flanking a harmonic of the
clocking frequency of the electrometer stage. The
separate sidebands are then synchronously detected, using
a switching demodulator operated at the harmonic of that
clocking frequency. The baseband spectrum of the
synchronously detected AM sidebands i5 separated from the
associated harmonic spectra. This baseband spectrum is
used as the output signal from the charge transfer device,
rather than the baseband spectrum of the imager output
~2~9337
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signal, which is suppressed by the band-pass filtering
before synchronous detection.
The method Davy describes is effective in
suppressing the flicker noise in the electrometer stage,
which noise resides principally in the baseband.
Reset noise is ignored by Davy; but, as noted
above, reset noise is a primary source of noise in a
semiconductor imager with a floating gate or floating
diffusion output stage. Reset noise is wideband and
extends through the harmonic frequency spectra of the
video samples supplied at the semiconductor imager output.
Consequently, reset noise is a major contributor to noise,
even when synchronous detection of the sidebands
surrounding a clocking frequency harmonic is used to
recover video signal from the imager output samples. (It
is to be understood that in this discussion reset noise
does not refer to the simple feedthrough of reset pulses,
the reduction of which feed-through Davy does concern
himself with.)
The present inventor has discerned that when the
CCD imager output signal is high~pass-filtered or
differentiated before sampling-and-holding, then the
sample and hold circuit converts harmonic spectrum
components of the imager output signal to baseband
spectrum components, which are in the frequency domain in
a synchronous detection. Consequently, low frequency
content of the image is recovered, despite high pass
filtering of the imager output signal. Furthermore, the
holding process is responsive to the peaks of the harmonic
spectrum content of the imager output signal, not to the
average absolute value. Consequently, conversion
efficiency of the presently contemplated procedure is
significantly higher than in the synchronous detection
process described by Davy. These processes use sampling
followed directly, without holding, by low-pass-filtering
to smooth detection response.
W.F. Kosonocky and J.E. Carnes of RCA
Corporation's David Sarnoff Research Center described the
~2:19337
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floating-diffusion amplifier in their paper entitled
"Basic Concepts of Charge-Coupled Devices" and published
September 1975 in RCA Review, Vol. 36, pp. 566-593. The
paper suggests resetting of the floating diffusion to the
barrier potential afforded by a gate, which is biased with
direct potential and interposed between the floating
diffusion and a gate operative as a reset gate. That is,
the floating diffusion is reset to a channel potential
within the charge transfer channel in which the floating
diffusion is disposed, rather than to the drain potential
at the end of the charge transfer channel. This approach
to resetting the floating diffusion has for the most part
been discarded as impractical by those skilled in the art,
because the approach introduces a pronounced low-frequency
distortion in the modulation transfer function (MTF).
Smearing of the trailing edges of bright areas into darker
areas is noted in television displays based on the video
samples from CCD imagers having floating diffusion output
stages reset to in-channel voltages rather than to drain
voltages, when the output stages have their output samples
processed conventionally and a sample-and-hold output
circuit is used to suppress clock feedthrough.
The present inventor has discovered that the
low-frequency distortion in the Kosonocky and Carnes
resetting procedure adversely affects only the baseband
portion of the frequency spectrum of the CCD imager output
signal. If the baseband (or at least the lower
freguencies in which distortîon appears) is suppressed
before sample and holding to recover a signal free of
spaces, then distortion to the Kosonocky and Carnes
procedure does not appear in the sample and hold output
response.
The present inventor has discovered that reset
noise can also be suppressed, if reset pulses are
appropriately timed, even though the floating diffusion is
reset to reset drain potential following each picture
element sample being clocked to be "under" the diffusion
for electrometer measurement. Furthermore, this reset can
~2~337
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be achieved without the need to sample more than once
during each pixel scan interval.
It is observed that following reset, there is an
intelval which precedes the introduction of the next
charge packet under the floatiny element of the
electrometer CCD output stage. The reset noise level
during this preceding interval is the same as the reset
noise level during the ensuing interval after introduction
of charge and before subsequent reset. This phenomenon is
exploited in correlated double sampling.
Considering this phenomenon somewhat
differently, the inventor notes: that the transition in
signal, which is caused by introduction of a charge packet
under the floating element may be superposed on a reset
noise pedestal; and that such a noise pedestal changes
only from pixel-to-pixel. The inventor notes that
differentiation with respect to time of the CCD imager
output signal, in accordance with the present invention,
suppresses response to reset noise pedestals with respect
to responses to those transitions which are caused by
introduction of charge packets under the floating element.
Synchronous detection of the differential output signal
then can take place over sampling periods which extend
over respective fixed portions of the decaying responses
to these transitions. The resulting output signal
exhibits good signal to reset noise ratio.
-
\
~,
~9337
- 6A~ RCA 79g94/805~6
SUMMARY OF INVENTION
The present invention is embodied in a charge
coupled device arrangement receptive to a regular clocking
frequency for transferal of charge packets to signal
samples supplied at an output circuit. For generating a
response with an improved modulation transfer factor (MTF )
at higher frequencies the following is provided. A
synchronous detector is provided for demodulating at a
carrier frequency that is harmonically related to the
clocking frequency. The detector has an input and an
output circuit for supplying said response with improved
MTF at higher frequencies. The detector response is not
balanced against the signal applied to its input. A
filtering circuit is connected between the output of the
charge coupled device and the input of the synchronous
detector. The filtering circuit limits the frequency
spectrum of the energy of the signal samples supplied to
the detector. Input to include energy in the double
sideband spectrum flanking the carrier frequency, to
2~ include the higher frequency content of baseband
spectrum of the signal samples, and to exclude the energy
in at least the lower frequency portion of the baseband
spectrum of the signal samples.
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BRIEF DESCRIPTION OF T~E DRAWING
In the drawing:
FIGURE 1 is a schematic diagram of the signal
recovery system of the present invention, shown used with
a CCD imager of the field transfer type;
FIGURE 2 is a potential profile descriptive of
resetting the floating diffusion to reset drain potential;
FIGURES 3, 4 and 5 are potential profiles
descriptive of different representative ways in which
resetting of a floating diffusion to an in-channel
potential, rather than to reset drain potential, may be
accomplished as an element of the invention; and
FIGURE 6 is a timing diagram descriptive of the
preferred timing of resetting the floating diffusion to
reset drain potentia~ per FIGURE 2.
DETAILED DESCRIPTION
In FIGURE 1 the signal recovery system of the
invention is shown being used with a semiconductor imager.
By way of example, imager is a CCD imager 10 of field
transfer type. CCD imager 10 includes an image (or A)
register 11, a field storage (or B) register 12, and a
parallel-input-serial-output (or C) register 13. Output
signal samples are generated from the charge packets
transferred to the right end of C register 13, using a
floating-diffusion type of charge-to-voltage conversion
stage, by way of example. In such a conversion stage
charge packets are regularly clocked forward from the
output of C register 13 to a potential well disposed under
floating diffusion 14. The magnitude of charge in each
packet in the potential well is then determined by an
electrometer. The electrometer includes a cascade
connection of source-follower
metal-insulator-semiconductor field effect transistors 15
and 16. A further MISFET 17 is connected as a
constant-current-generator source load for MISFET 15.
Off-chip resistor 28 provides a source load for MISFET 16.
3337
-8- RCA 79,994/~0,596
The CCD ill~ager 10 output signal samples appear across
resistor 28. A direct potential, OD, is applied to the
drains of MISFET's 15 and 16 to condition MISFET's 15 and
16 for source follower operation. The source of MISFET 16
connects to the output signal terminal 27 of CCD imager 10
and thence through load resistor 28 to a ground
connection.
Output signal samples supplied at the output
terminal 27 of CCD imager 10 are applied to the input
connection of a low-noise voltage amplifier 29. The
output connection of amplifier 29 supplies input signal
samples to a differentiator 30. Amplifier 29 buffers the
input connection of differentiator 30 from source-follower
MISFET 16. Amplifier 29 preferably has a bandwidth
sufficiently restricted to roll off higher video
frequencies somewhat. With such roll-off, differentiator
30: (a) responds to the signal transitions having lowered
slew rate to generate pulses with greater energy content,
and (b) does not introduce into final video response
excessive-amplitude spikes, which otherwise would be
present as the result of clocking signal feedthrough. The
differentiated-with-
respect-to-time video response of differentiator 30 is
supplied as input signal to a wide-band low-noise
amplifier 35.
After each charge packet is measured, the
potential on floating diffusion 14 is reset responsive to
a ~r pulse. The ~r pulse is applied to a reset gate 18
and conventionally is somewhat narrower than the clocking
pulse applied to the last clocked gate (not specifically
shown) of C register 13. The ~r pulse occurs within the
time that the clocking pulse appears. Reset gate 18 is
disposed "o~er" a charge transfer channel 19, which
extends through the C register 13 and beyond to include
floating diffusion 14 and a reset drain 20. More
particularly, reset gate 18 is disposed "over" charge
transfer channel 19 between floating diffusion 14 and
reset drain 20 and is preceded by a d-c gate 21. A direct
~Z~3~37
-9- RCA 79,994/80,596
potential, RG, is applied to gate 21. Gate 21 is
preferably a short gate, in order to reduce the amount of
stored charge thereunder. Gate 21 is used to prevent the
~r pulses applied to reset gate 18 from being coupled
electrostatically to floating diffusion 14.
A clock generator 25 is shown in FIGURE 1
supplying respective sets of three-phase clocking signals
to A register 11, to B register 12 and to C register 13 as
customary for a CCD imager of field transfer type. Other
well-known clocking schemes using two-, four-, single- or
virtual-phase clocking could be used instead. Clock
generator 25 generates ~r pulses as described above, for
application to gate electrode 18 of the floating-diffusion
output stage.
Clock generator 25 also supplies ~s pulses, at a
repetition rate equal to the clocking frequency of C
register 13 during serial line read-out. Such ~s pulses
are applied via a line 26 to a synchronous detector 40.
The ~s pulses are used as carrier for controlling the
times that signal supplied to synchronous detector 40 from
the ouput connection of wide-band low-noise amplifier 35
is sampled in the synchronous detection process.
- Amplifier 35 provides voltage gain which raises signal
level such that its accompanying noise is larger than that
introduced by the synchronous detection process to follow;
the noise attributable to amplifier 35 is negligible
compared to the l/f noise generated within CCD imager 10.
Differentiator 30 is shown in FIGURE 1 as a
simple RC high-pass filter comprising a series-arm
capacitor 31 and a shunt-leg resistor 32. The RC time
constant ~ is chosen to suppress at least as much of the
baseband frequency spectrum of the CCD imager 10 output
samples as is accompanied by flicker or "l/f" noise that
is substantially large, as compared to background thermal
noise. This suppression of baseband frequency spectrum is
manifested in the output response of differentiator 30
supplied to synchronous detector 40. The time constant I
is the reciprocal of a corner frequency fc, as expressed
9337
-10~ RCA 79,994/80,596
in radians per second, amplitude components at which
frequency fc are suppressed 3dB by the RC filter.
Frequency fc may be considered as a frequency of
demarcation between substantial suppression and
substantial non-suppression of frequencies present in the
input signal of differentiator 30, but only selectively
present in its output signal.
A 430 picofarad capacitor 31 and a 75-ohm
resistor 32 have been used by the present inventor in a
signal recovery system with 7.5 MHz C register 13 clocking
frequency. The RC high pass filter has a thirty-five
nanosecond time constant, or ~, which provides for a 5 MHz
corner frequency. The upper frequencies of the baseband
spectrum of the CCD imager 10 output samples from
differentiator 30 combine with the demodulated first
harmonic spectrum in synchronous detector 40 output signal
to provide video high-frequency peaking. (~he baseband
signal remnants and the demodulated
first-harmonic-spectrum signal are correlated and add
algebraically, while the noise components from the
respective bands are uncorrelated and add vectorially.
Conse~uently, signal-to-noise advantages accrue with this
form of video high-frequency peaking.)
A switching demodulator followed by low-pass
filtering could be used in place of synchronous detector
40. ~owever, such switching demodulators perform average
detection, providing demodulator output signal in which
the reco~ered baseband is accompanied by strong harmonic
spectra. It is preferable to use a synchronous detection
process, which is peak detection by nature, to reduce the
strength of the harmonic spectra remnant from the
detection process relative to the recovered base-band
spectrum. A sample-and-hold circuit performs as such a
synchronous detector here.
FIGURE 1 shows a simple sample-and-hold circuit
40 comprising MISFET 41 and capacitor 42. The channel of
MISFET 41, when conductive, admits a respective sample to
capacitor 42, which holds the admitted sample. The gate
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of MISFET 41 receives from line 26 the ~s pulses, which
are supplied at a rate equal to the C register clocking
frequency. The channel of MISFET 41 is rendered
conductive responsive to each ~s pulse. MISFET 41
operates as a transmission gate of a type in which control
signals (~s pulses from line 26) do not feed through to
any appreciable extent to the conductive channel. The
output circuit of this form of synchronous detector is not
balanced with respect to input signals supplied to the
conductive channel. The remnants of baseband spectrum
applied to the input of this synchronous detector appear
at its output, which allows passage of higher frequency
components of the baseband spectrum. This provides for
some video high-frequency peaking.
The detected output signal, from sample-and-hold
circuit 40 (unlike a signal taken directly from a
switching demodulator) is a usable video signal and does
not need filtering beyond that afforded by video amplifier
cut-off. The detected output signal from detector 40 is
shown applied to a buffer amplifier 50 and thence to a
smoothing filter 51. Filter 51 is preferably a lo~-pass
filter that removes clocking frequency remnants, so as to
supply a low-noise video signal that is also free of
aliasing on image details. This low-noise video will
usually be directed to a video processing amplifier ~not
shown) where synchronizing and equalizing pulses will be
inserted at times coordinated with the timing of clock
generator 25.
The phasing of the pulses supplied via line 26
from clock generator 25 to the gate of MISFET 41 is
arranged so that the channel of that transistor is
conductive during the decaying portions of differentiator
30 spike responses to certain transitions in CCD imager 10
output signal level. Those certain transitions are
attributable to the introduction of charge packets under
floating diffusion 14. Those transitions are not
accompanied by reset noise. However, there is remnant
reset noise from the decaying portions of differentiator
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30 spike responses to transitions in CCD imager 10 output
signal at the leading and trailing edges of the ~r reset
pulses. Consequently, the latter transitions do have
reset noise components. Such noise components arise
respectively from the previous pixel, and from the current
pixel, as will be treated in greater detail further on.
Synchronous detection of the decaying portions of spike
responses to the trailing edges of the 0r can be reduced
by arranging for a shorter RC time constant I in
differentiator 30. However, such arrangement reduces the
amount of horizontal peaking obtainable from the passing
remnant baseband spectrum.
Avoiding synchronous detection of transtions at
the leading and trailing edges of the ~r pulses can be
made easier by giving special attention to the timing with
which ~r reset pulses are applied to reset gate electrode
18 of the floating-diffusion CCD imager output stage. The
intricacies of this reset procedure will be explained
later with the aid of the potential profile diagram of
FIGURE 2 and the timing diagram of FIGURE 6.
Each of potential profile diagrams of FIGURES 2,
3, 4 and 5 has at its top stylized representations of the
structures encountered by charge packets in moving from
left to right in the charge transfer channel. In the
profile, more positive potentials will be more downward in
the diagram. The diagram will assume empty potential well
under floating diffusion 14. For the sake of simplicity,
fringing field effects will be ignored. Consideration of
fringing field effects is not essential to understanding
operation of the invention.
FIGURE 2 potential profile diagram is
descriptive of resetting floating diffusion 14 to reset
drain potential R~, which is applied to reset drain 20.
~c is the phase of C register clocking applied during line
read-out to the last clocked gate 61 of C register 13. C
register 13 has a final gate 62 following clocked gate 61,
to which final gate a direct potential BP is applied.
Potential BP establishes a barrier height to block the
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passage of charge from a potential well under clocked gate
61 to a potential well under floating diffusion 14, except
for those intervals when ~c pulses lower gate 61 to less
positive potential. Gate 21 has a potential RG applied to
it such that the channel potential under gate 21 is as
positive as, or more positive than, the drain potential
RD. Fringing field effects will strongly affect the
actual in-channel potential under gate 21, which is
normally made very short to reduce charge sharing with the
floating diffusion 14. ~r ranges between: (a) during
charge measurement time, a voltage sufficiently negative
to erect an unsurmountable barrier to passage of charge
from floating diffusion 14 to reset drain 20 diffusion and
(b) during reset time, a voltage sufficiently positive to
allow the charge level under floating diffusion 14 to
drain to RD potential as shown. Consequently floating
diffusion 14 is reset to reset drain potential RD.
The RC time constant of the portion of the
charge transfer in which floating diffusion 14 is disposed
is short in this reset scheme. This is so, because the C
portion of the time constant is the small capacitance of
substrate of floating diffusion 14 and because the R
portion is the low resistance offered by the channel of
the cascode field-effect-transistor action (which extends
between floating diffusion 14 and reset drain 20 when
positive-going pulse ~r is applied to reset gate 18).
Resetting to the final value of thermal noise variations
superposed on reset drain potential RD occurs, because
this time constant is too fast to integrate out the noise
variations. This is a sample-and-hold process, which
extends the duration of the last value of thermal noise
variation until the next reset interval, and thereby
creates reset noise.
The inventor has found a method by which the
reset noise encountered in operating the RCA Corporation
403-column CCD imager can be reduced from a 100-electron
or so level to a level less than the 35-electron or so
level. Noise at this latter level is attributable to
~ Z~9337
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MISFET's 15, 16, 17. This method will be explained with
the aid of FIGURE 6.
In FIGURE 6, timing diagram waveform (a) is the
clocking signal applied to the last clocked gate electrode
61 of C register 13. This last-clocked gate electrode per
conventional practice is immediately followed by a gate
electrode 62. Gate 62 is biased with direct potential,
and is subsequently followed by the floating diffusion 14.
For purposes of illustration, three-phase clocking is
assumed. The clock cycle is of 133 ns. duration in a
403-column-image-register CCD imager of field transfer
type, which is to be operated to furnish a component of
NTSC broadcast television signal. When the clock voltage
applied to the last clocked gate electrode 61 of C
register 13 goes negative, a charge packet sampling an
image picture element is transferred under floating
diffusion 14. This transfer is represented in waveform of
FIGURE 6 (a) by an arrow on the voltage transition.
Waveform (b) of FIGURE 6 illustrates the timing
of the positive-going reset pulse ~r applied to reset gate
18. ~n initial ~r pulse ~r 1 is shown in waveform (b)
followed by ~r pulses ~r 2 and ~r 3; these pulses are in a
succession of ~r pulses. Each such ~r reset pulse
conventionally would be applied shortly before the
negative-going transition in waveform (a~ when correlated
double sampling is not used. However, as shown in
waveform (b), the ~r reset pulse used here, is applied
well before ~he negative-going transition of a respective
clocking pulse. Each clocking pulse is of length of time
t, which is at least not appreciably shorter than 1, the
RC time constant. This timing arrangement allows the
spike response of differentiator 30 (to transitions
generated at leading and trailing edges of ~r pulses) to
be substantially completed by th~ time a ~s pulse occurs
(to render the channel of MISFET 41 conductive, in the
process of sampling the spike response of differentiator
30 to the transition associated with introduction of a
charge packet under floating diffusion 14). Such early
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occurrence of ~r reset pulses is used in operation with
correlated double sampling as well, but for purposes which
are different from purposes of the present invention.
FIGURE 6 waveform (c) shows the resulting
potential variation on floating diffusion 14. The same
potential variation, perhaps of different direct bias
level, appears at the source electrode of MISFET 16 and
across the load resistor 28 of the CCD imager 10. A range
of variation, R, attributable to reset noise, appears in
unclamped portions of waveform (c) between the reset
pulses ~r-l and ~r-2 shown in waveform (b).
A range of variation R', also attributable to
reset noise, appears in portions of waveform (c) occurring
during the time between the reset pulses ~r 2 and ~r 3
shown in waveform (b). The ranges of variation R and R'
are of similar amplitude, ~ut the amplitude variations in
ranges R and R' are not correlated. The introduction of a
charge packet under floating diffusion 14 following the
reset pulse ~r 2 creates a sample height ~ on which reset
noise in the R' range is superposed.
FIGURE 6 waveform (d) is an ideali~ation of the
voltage samples appearing at the output of amplifier 35
following differentiator 30. Clocking noise is not
considered. The differentiator 30 suppresses low
fre~uency content in its response, which response will be
analyzed by superposition of responses to transition
edges. The differentiation of the range of amplitudes of
the transition of waveform (c) at the leading edge of the
reset pulse ~r 2' as accompanied by reset noise of range R
amplified by the voltage gain G of amplifier 35, causes an
initial value of GR within the range of reset noise
appearing in waveform (d) during the ~r 2 pulse. This
initial value of GR decays exponentially to GR exp (dT 1)
during the duration d of ~r 2 pulse. The differentiation
of the transition of waveform (c~ at the trailing edge of
the ~r 2 pulse, which is accompanied by reset noise of
range R' and is amplified by the voltage gain G of
amplifier 35, increments GR exp 1(dT 1) by non-correlated
~93'~
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reset noise GR'. This incrementing gives an initial value
N for the exponentially decaying range of total reset
noise in the period between ~r 2 and ~r 3 pulses. The sum
of these non-correlated reset noise components is such
that N on average substantially e~uals G[R'2+R2
exp 2(dl 1)]( 2) at the trailing edge of the ~r 2 pulse.
At a time t duration later, when a charge packet
is introduced under floating diffusion 1~, reset noise
will be reduced to a value N [exp 1(tl 1)]. At this time
the response of voltage amplifier 35 to differentiated ~
sample height has a value of G~. Signal-to-noise ratio at
this time has a value, then, of
'2 2 ~2(dl~~)]~(l~)exp(tl~l). Since both G~ sample
and N/[exp(tl 1~] reset noise decay exponentially, this
signal-to-noise ratio remains substantially constant as
the G~ sample decays.
FIGURE 6 waveform (e) shows a representative
phasing of two (~s 1 and ~5 2) f the succession of 0s
sampling pulses, which are applied via line 26 to the gate
electrode of the n-channel MISFET 41 and are used as the
sample switch in synchronous detector 40. Although
circuit 40 is considered as being sample-and-hold in
nature, it more accurately is described as being
track-and-hold in nature, with the last value of each
sample being held throughout the ensuing hold period. In
this last context, the amplitude of sample-and-hold
circuit 40 output response is increased, if sampling is
done with a narrower pulse sooner after th~ G~ negative
transition.
Since the component of reset noise owing to the
previous pixel and the component of reset noise owing to
the current pixel are not correlated and tend to be on
average the same amplitude, shortening d as much as
possible for given value of d+t, tends to reduce reset
noise. Making d 33 nanoseconds and t 40 nanoseconds (as
compared to the 35 nanosecond time constant ~ of filter
30) reduces reset noise by a factor of three compared to
resetting just before admission of charge under floating
123L9~37
-17- RCA 7~,994/80,596
diffusion 14. In terms of the operation of the circuit
specifically described using the RCA Corporation
403-column CCD imager, this reduces reset noise to less
than the 35-electron amplifier noise.
As noted above, ~eset noise results when the
reset of floating diffusion 14 is by hard clamp to reset
drain 20, by reason of the attendant short RC time
constant on the voltage appearing at floating diffusion 14
allowing reset to thermal noise. Reset noise
alternatively may be lowered by taking measures to
lengthen the RC time constant on the floating diffusion
14. This can be done by resetting the floating diffusion,
not to reset drain potential, but to an in-channel
potential. Such resetting introduces an accumulation
process. The accumulation process provides time
integration of the charge under the floating diffusion 14.
Such integration lengthens the effective RC time constant
associated with floating diffusion 14. Alternative modes
of resetting using these principals are set forth later in
this description.
Other differentiator circuits than the resistor
31, capacitor 32 high-pass RC network can be used to
implement the invention, of course.
The extension of the decaying response to the
leading edges of reset pulses to overlap the response to
the measurement of the ensuing pixel sample has a
pronounced effect on video peaking (in line scan
direction) of the synchronously detected CCD imager output
signal. This will be explained with the aid of FIGURE
6(d)-
The loss of d-c baseline reference during
passage of the CCD imager 10 output signal through
differentiator 30 cooperates with the lack of d-c
restoration except during line retrace to produce the
following effect. The decaying exponential response to
the leading edge of each reset pulse has a tail with an
amplitude component that depends to on the value of the
image sample admitted under floating diffusion 14 prior to
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-18- RCA 79,994/80,596
that reset pulse. The lower frequency components of that
previous image sample are similar to that of the next
image sample admitted under floating diffusion 14 after
that reset pulse. Consequently, the positive decaying
exponential response to the leading edge of the reset
pulse opposes the negative decaying exponential response
to that next image sample. This opposed relationship
reduces the lower-frequency modulation of each harmonic of
C register clocking frequency in imager lO output signal.
These opposed-relationship, higher frequency components of
the two image samples are dissimilar, so that the
cancellation effect is less pronounced. This incxeases
the amplitude of higher-modulating-frequency sidebands of
the harmonics of C register clocking frequency relative to
the amplitude of their lower-modulating-frequency
sidebands.
The factor by which the synchronous detector 40
output signal is pe~ked at each frequency is substantially
constant despite variations in reset pulse amplitude or
variations in the difference between amplitudes of
successive pixel samples. The amount of peaking depends
primarily on -the degree to which the tail of the
exponentially decaying positive response to difference of
successive pixel samples is reduced in its overlap with
the exponentially decaying negative response to the later
pixel sample. The amount of tail amplitude reduction
depends on the expired time between the leading edge of
reset pulse and the admission of succeeding image sample
charge under floating diffusion 14. In other words, the
amount of tail amplitude reduction depends on the sum
(~+t) of the duration d of the reset pulse and the
interval t between the trailing edge of the reset pulse
and that admission of charge.
The duration d of the xeset pulse can be chosen
to provide flat video response at the output connection of
synchronous detector 40 (or, for that matter, to provide
rolled-off or peaked video response if one so desires).
The length of interval t can be adjusted to a degree to
~Z~933~
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affect peaki~g as well. As noted above, this adjustment
is constrained by the desire to avoid reset noise.
Quantities d,t, and I may be selected so as to provide for
over-peaked video response, then the video response may be
trimmed as desired, using a variable resistance inserted
in series with the channel of MISFET 41 to introduce a
varying degree of roll-off.
The use of differentiator 30 prior to
synchronous detector 40 solves another problem encountered
in CCD imagers. During the parallel transfer of charge
packets from the B register 12 to the C register 13, a
transient change occurs in the substrate bias. This
transient causes a level shift in CCD imager to response.
The level shift is manifested as an initially pronounced
decaying overbrightness in the first few video samples
clocked out of C register 13 in each line of video. This
overbrightness "hook" at edge of picture decays at a rate
pixel-to-pixel slow enough to be suppressed substantially
entirely in diff~rentiator 30 response. A similar effect,
which is manifested at the top of the displayed image,
results from A register-to-B register transfer during the
vertical retrace interval. This manifestation also is
substantially reduced entirely by differentiator 30.
The earlier-mentioned, alternative modes of
resetting are considered next. The difference between
resetting floating diffusion 14 to reset drain potential
and resetting to an in-channel potential will now be
explained with the aid of potential profile diagrams,
FIGURES 3, 4 and 5.
FIGURE 3 is a potential profile diagram descrip-
tive of resetting floating diffusion 14 to an in-channel
potential. The in-channel potential is established by the
most pcsitive excursion of ~r~ which is not so positive
as RD. This most positive excursion presents a lowered
barrier height which will be surmounted by charge carriers
in the region of floating diffusion 14 and under gate 21,
until a potential level somewhat more positive than the
barrier height is established on the floating diffusion
~X~L9337
-20- RCA 79,994/80,596
14. This potential is less positive than RD. Reset is to
the barrier height with a small offset owing to dark
current flowing responsive to thermal excitation of charge
carriers. (Variation in the offset owing to this thermal
excitation is a principal cause of the low-frequency peak
up of the base-band of the modulation transfer function
when reset is to an in-channel potential.)
FIGURE 4 is ~ potential profile diagram of a
preferred way of resetting floating diffusion 14 to an
in-channel potential. Reset gate 18 is operated over a
range including reset drain potential RD. The positive
excursion of ~r is not the in-channel potential to which
floating diffusion 14 is reset. Rather, the direct
potential RG applied to d-c gate 21, which direct
potential is easily filtered to remove noise therefrom, is
made less positive than reset drain voltage RD. A
potential barrier 63 is erected under d-c gate 21, and
floating diffusion 14 resets to the barrier potential 63,
with a slight positive offset. The offset occurs because
the flow of charge proceeds only until the barrier
potential can no longer be surmounted.
FIGURE 5 is a potential profile diagram of
resetting to floating diffusion 14 barrier potential under
d-c gate 21 when reset gate 18 has a further d-c gate 64
interposed between it and reset drain 20. Such a further
d-c gate 64 is found in the CCD imagers presently manufac-
tured by RCA Corporation. This further d-c gate 64 is
internally connected to d-c gate 21 in these devices. The
strongly preferred direction of flow of charge from under
reset gate 18, when gate 18 is no longer positively
pulsed, is towards reset drain 20. This is because the
barrier potential under d-c gate 21 tends to be less
easily surmounted than the barrier potential under d-c
gate 64, o~ing to fringing field from reset drain 20
reducing the barrier height under d-c gate 64.
While the invention has been described in
connection with a field transfer type of CCD imager, 10,
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-21- RCA 79,994/80,596
it is equally useful in other types of CCD imagers such as
those of interline-transfer or line-transfer types.
