Note: Descriptions are shown in the official language in which they were submitted.
I BACKGROUND Ox Toll V~NTION ~5~S6
Jo This invention relates to document processing systems
Al in general, more particularly to document processing systems
I adapted to be utilized in the processing of financial documents
such as checks, invoices, payment advises, vouchers, drafts,
credit card charges and the like, and even more particularly
to improved document encoders, scanners, digital image processors,
and video image data compressors particularly useful in the
l document processing system.
¦ Document processors which read and sort financial
documents have been in common use for some time; however,
various other functions which are necessary to most financial
operations have been relegated to separate sub systems or
¦ specialized processors to prevent major bottlenecks in the
1¦ document processing system. Among the peripheral functions
Jo which have not, in the pus', been accomplished by the primary
¦¦ document processor are encoding with magnetic ink, microfilming
¦, and endorsing. Additionally, state of the art document pro-
I censors utilizing digital imaging still require manual transfer
I of documents to other processors to accomplish traditionally
slower speed operations such as encoding, thus resulting in
lower efficiency in processing and increased probability of
l errors.
if An effective document processing system desirably
1 utilizes an effective document encoder. state of the art
encoders typically fall into two general categories. The
first category of encoders includes those encoders which utilize !
a step function to position the document to be encoded at
Al a particular point. Such encoders function in a manner
typically associated with typewriters or other mechanical
printers and are not generally compatible with high speed
document processors. A second category of document encoders,
,1 including laser printers and ink jet printers, while capable
of encoding continuously moving documents is nonetheless income
', potluck for use with modern financial document processors.
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Document processing systems also desirably require
effective means of image storage. Early attempts at image
¦ storage utilized so-called "hard copy" image storage such as
I microfiche, microfilm or reduced photocopies. More recently,
I document images have been obtained utilizing electronic video
equipment, and still more recently, utilizing digital elect
ironic video equipment.
,¦ Typically, in a digital document image capture system,
if a moving document is repetitively scanned in one axis and
If individual sections ox the documents are assigned a value as
¦ either a "black" or "white" section, as a result of a comparison
with an arbitrarily assigned reference value. This simplistic
i approach to rendering a document image into a series of "black"
l or "white" sections is sufficient for many applications,
I however, if the system must operate upon molted documents,
I such as personal checks, it is possible that the background
Al color of a particular document may exceed the reference value,
If and therefore may result in the entire image undesirably being
1, classified as "black".
I Further, an optical sensor is typically utilized to
detect the presence of a document prior -to the initiation of
! digitization in such known systems. Tess additional piece of
electronic equipment provides a possible source of error, in 1,
that a malfunction of the optical sensor may result in a
Al document passing through the system without being scanned.
Digital image processing for creating visual images
I from digital data is known. Typically, state of the art
i' systems display an entire image corresponding to the digital
I values stored in memory. More sophisticated systems utilize
¦ video displays with permanently established boundaries between
two sections of a display and separate images assigned to each
section, in order to visually compare one image to another.
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I As the complexity of such systems increases and the demallds
Al upon digital image processors grow to include such state of the
¦¦ art devices as laser printers, the need continues to exist
I for more sophisticated and flexible digital image processing
It systems, particularly in financial document processor systems.
Al An effective document processor desirably includes
Jo video image data compression apparatus. Specifically, in
circumstances in which it is desired to store or recall a
,, plurality of video images, the magnitude ox data required for
I each individual image makes data compression a highly desired
I! feature
Known data compression schemes which are utilized in
conjunction with black and white document images typically
involve a scan which it perpendicular to the direction of
1 document travel. Scan data is then analyzed and long kinesic-
! live black or white sections are removed and replaced with
coded substitutes. In more sophisticated data compression
schemes, scan data is analyzed and repetitive patterns
I containing both black and white sections may be encoded and
, removed. Present apparatus, however, is not completely
acceptable, particularly or an effective document processor
system.
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i SUM OF TIRE INVENTION
If accordingly, it is a principal object of the present
Al invention to provide an improved financial document processor.
Jo It is another object of the present invention to
Jo provide an improved financial document processor which utilizes
1, a modular transport system and combines all required operations
I¦ into a single document processor.
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I! It is yet another object of the present invention to
i! provide an improved document encoder capable of encoding
10 1' continuously moving documents. i;
- It is another object of the present invention to provide
¦ an improved digital document image scanning system with a
¦ variable reference value being utilized fox black/white decisions
! It is another object of the prevent invention to provide
15 I an improved digital image processing system.
! It is another object of the present invention to provide i
, a video data compression system which provides a higher degree
If of data compression than known systems.
I In accordance with these and other objects, the invent
20 11 lion, briefly described, is directed to a document processing system which comprises a modular transport system including a
digital image capture system, character recognition circuitry,
document encoding systems, document endorsing systems, audit
Fiji trail printers, an in-line microfilm record system and a high
if speed document sorter. Associated video terminals and non-
impact printers such as laser printers are utilized to provide
! visual images of documents processed by the system. Selected
documents may be read, endorsed, encoded, annotated with an
i! audit trail indicia, digitally imaged, filmed and sorted in a
I¦ single continuous pass through the document processing system
Al of the present invention.
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For encoding, the documents are transported between a
plurality of fixed dies and a plurality of electronically
!¦ controlled hammers. A magnetic ink bearing ribbon is interposed ¦
I between the documents and the fixed dies and is transported at
5 if the same velocity as the documents. As the documents traverse
the plurality of fixed dies, the electronically controlled
hammers are cycled, in a selected sequence and at selected
positions. In twos applications in which the cycle time of the
,1 electronically controlled hammer is too slow to allow identical
Al encoding in adjacent positions, a second plurality of fixed
11 dies and associated electronically controlled hammers may be
I located adjacent to the first plurality or interspersed
l! among the first plurality of fixed dies.
Al As further described, the documents are continually
15 it transported across the focal plane of a stationary scanner,
Al and repetitively scanned Inca single axis. Circuitry is
1, included in the digital scanner which permits the presence or
j' absence ox a document to be detected by means of an evaluation
I of the output of the digital scanner. Additional circuitry in
I the digital scanner allows a dynamic adjustment of reference
levels, thereby 'acco~nodating molted documents which may
utilize shaded backgrounds.
A digital image processing system includes an image
If memory and circuitry enabling the display to be partitioned'
- 25 j into discrete portions of variable sizes, each portion of which
¦ may be utilized either to display a selected portion of the
image within the image memory or to display a plurality of
1 alphanumeric characters. During alphanumeric character mode,
I coded representations of each alphanumeric character are
i! stored in the image memory, in an appropriate section.
j Alternately, selected portions of one document image may be
visually compared to selected portions of a second document
image by utilizing this display partitioning feature. Add-
tonally, circuitry is provided which allows image rotation,
35' ', mirror imaging and discrete video attribute selection within
; each portion of the display.
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, In accordance with an improved data compression scheme,
If an image is obtained by vertically scanning a selected document.
Jo The image is then represented by a series of consecutive Verdi-
Al eel scans identifying particular sections or cells of the image
l, as either black or white. A plurality of consecutive scans
If are then temporarily stored and analyzed horizontally. Analysis j
I circuitry is utilized to identify certain consecutive white or
black sections of the image, repetition of previous sections of
It the image, or repetition of certain selectable patterns within
If, the image. The coded output of the analysis circuitry is then
', stored and may be utilized to reconstruct the image of the
i! financial document
According to one broad aspect of the invention, it
, comprises on apparatus for processing documents comprising:
Al means for transporting a series of continuously moving documents
,', along a selected track; means disposed adjacent to said
selected track for selectively encoding machine readable
data upon selected ones of said documents; means disposed
I adjacent to said selected track for reading machine readable
'` data encoded upon selected ones of said documents; and means
, disposed at the end of said track for sorting said documents.
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1 In another broad aspect, the invention is an apparatus for
2 processing documents comprising: (a) transport means for continuously
3 transporting said documents along a transport path; (b) encoding means
4 disposed adjacent said transport means for encoding machine readable data
upon said documents; (c) reader means disposed adjacent said transport
6 path for reading machine readable data on said documents while said documents
7 are transported, without interruption, past said reader means; and
8 id) image capture means disposed adjacent said transport path for capturing
9 and digitizing en. image of at least a portion of said documents, said
image capture means comprising means for vertically scanning said documents,
11 means for horizontally analyzing consecutive vertical scans to identify black
12 and white sections as well as repetitive patterns of said image, and means13 for generating distinctive codes representative of said analyzing.
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BRIEF DESCRIPTION OF THE DRAWINGS
The novel features believed characteristic of the
invention are set forth in the appended claims. The invent
lotion itself; however, as well as a preferred mode of use,
'Further objects and advantages thereof, will best be under-
stood by reference to the following detailed description of
an illustrative embodiment when read in conjunction with the
! accompanying drawings, wherein:
I! Figures lo and lb form a general block diagram of
lo lithe document processing system of the present invention;
Figure 2 depicts a diagranunatic view of the clock-
lament transport of the document processing system of the
Present invention;
If Figure pa depicts a block diagram of the encoder
off the document processing system of the present invention;
¦ Figure 3b depicts a diagrammatic view of the
encoder of the document processing system of the present
invention; ,
. Figure 4 depicts a diagrammatic View of the en-
1 dowser of the document processing system of the present
invention;
Figure 5 depicts a diagrammatic view of the camera
¦ system of the document processor of the present invention;
. I Figures aye depict a schematic View of the
components of the camera buffer and interface circuitry of
Thea document processor of the present invention;
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¦ Figures aye and Figures aye depict a schematic
ilview of the components of the data compression system of the
!¦ document processor of the present invention;
. !¦ Figures Ahab depict a block diagram of the major
5 Al components of the data expansion system ox the document
processor of the present invention;
Figure 10 depicts a detailed block diagram of the
video terminal subsystem of the document processor of the
Present invention; and
10 ¦¦ Figures Lyle and Figures awoke depict a
! schematic view of the video formatter of the document
processor of the present invention. .
If GENERAL SYSTEM DESCRIPTION
15 I Referring to Figures lo and lb, there is depicted
joy general block diagram of the various subsystems comprising
Thea document processing system which embodies the present
invention i,
. ¦ The document processing system is controlled by
20 ' digital computer 100. Digital computer 100 coordinates the
storage and retrieval of digitized document images and
associated data which are stored, in the disclosed embody- !
¦ mint, in magnetic disk storage. Disk controller 102 con-
. ¦ trots the actual access ox digitized document images via
25 1 disk drives 10~, 106, and 108. Additional data, accounting
information or program data may be ascessQd by digital'
j computer 100 through tape cur tier 110 which control-
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magnetic tape drives 112 and 114. It Jill be appreciated by
Those skilled in the art that disk controller 102 and tape
controller 110 may control an increased or decreased number
off disk or tape drives, as a matter of design choice.
!IDigi-i_al computer 100 may selectively access either magnetic
disk storage or magnetic tape storage through channel so-
Hector 116.
I Digital computer 100, in the embodiment disclosed,
! interfaces with a local operator via the computer bus
¦ and printer interface 118. Printer interface 118 controls
I line printer 120. In alternate modes of operation wherein
remote communication with digital computer 100 is desired, a
modem and appropriate interface circuitry may be utilized.
. I Digital computer lulls controls the operation
1 of laser printer subsystem 124, through laser printer inter-
face 122. Issuer printer subsystem 124 is utilized to provide
hard copy of selected digital images and may be utilized to
I generate account statements, billing statements, or other
correspondence comprising any combination of alphanumeric
characters and images. The operation of laser subsystem 124
is described in greater detail herein.
Video terminal subsystem 136 is utilized in the
document processing system of the present invention to
. provide a real time, controllable video display of selected
documents and alphanumeric information. The display is
l utilized to facilitate processing of information on each
! document. Digital computer 100 controls the operation of .
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video terminal subsystem 136 through buffer interface 144
I and synchronous data link control master 146. A plurality
of video display terminals may be utilized with each SDLC
I master, in a manner which will be explained in detail below.
High speed transport subsystem 1~8 is utilized to
transport individual documents through image capture stay
I lions, machine readers, encoders and sorters. A plurality
I of high speed transports may be utilized within each dock-
! mint processing system, thereby increasing the capacity of
1 an individual system. High speed transport system 148 is
controlled utilizing buffer interlace 156 and synchronous
data link control master 158. High speed transport system
148 will be explained in greater detail with respect to
Figure 2.
¦ Digital image data obtained from the digital
camera or cameras installed in each high speed transport is
transferred to camera interface 160. Camera interface 160
is described in detail with reference to Figures pa through
l I and is utilized to couple the image data to digital image
1 compactor 162. Digital image compactor 162 is utilized to
, remove any redundancies contained in a selected image and to
if encode the remaining data. In addition to the specific
algorithm -taught in the disclosed embodiment, the document
I processing system ox the present invention will function
, with other known data compaction algorithms, such as, for
example, the CCITT standard algorithm. The thus compacted
digital image will require substantially less storage space
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in tile docunlent processing system. The compacted image (fate
may be transferred to storage via multiplexed direct memory
axis I and multiplexed direct memory access lG60 Tao ¦ '
direct memory systems are utilized in order to provide .
compatible interfaces between the local X bus and the direct
memory access interface bus of digital computer 100.
Retrieval and display of a compacted digital image .
may take place in several ways. A compacted image is trays-
. furrowed to the local Bus via direct memory access 1~4 and .
direct memory access 166. The compacted image is applied to
digital image expander 168. The redundancies present in the
original image are restored and the subsequent image is
trarlsferred via X bus distributor 170 or X bus distributor
172 to either laser printer subsystem 124 or video terminal
subsystem 136 for reproduction of a hard copy or an elect
ironic image.
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DIGITAL COMPUTER
The document processing system of the preferred
embodiment ox the present invention utilizes' a digital
. computer 100, Figure 1, to control the operation of the '
system and coordinate the storage and retrieval of document
images, In a preferred embodiment of the present invention,
digital computer 100 was actually constructed utilizing a .
Sirius 3200 minicomputer, manufactured by the Perkin-~lmer .
Computer Systems Division of Oc^anport,-New Jersey.
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I¦ The Model 3242 minicomputer utilizes 32-bit
architecture and a 32-bit operating system. The main memory
storage, in the embodiment disclosed, contains 1536 kilobytes
luff 15~ nanosecond MOW memory. Supplementing the computer's
lain memory store are disc drives 104, 106 and 108, Figure
1, Model 9775 manufactured by Control Data Corporation of
Minneapolis, Minnesota, and tape drives 112 and 114, Figure
1, Model TPAC 4516, manufactured by Perkin-Elmer of Ocean-
sport New Jersey.
1 Digital computer 100 also includes a rechargeable
I battery backup system (not shown) to sustain thiamine memory
! in the event of a power failure. The preferred embodiment
~1f digital computer 100 utilizes a battery rated at 320
Jo megabyte-minlltes, which is capable of maintaining the memory
¦ integrity of 16 megabytes for twenty minutes.
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I DOCUMENT TRANSPORT
Referring now to Figure 2, there is depicted a
lldiagrammatic plan view of document transport 200. Document
I, transport 200, in a preferred embodiment, is a specially
built transport which may be modified to include additional
equipment or to exclude undesired capabilities. The trays- ¦
- Import constructed and depicted in Figure 2 utilizes high
speed endless belts which are driven by pinch rollers in the
1 manner well known in the art. The punch rollers are driven
by synchronous AC motors at a nominal speed of 52 inches per
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second in the disclosed embodiment. Sections of the trays-
port may be driven at different speeds in a manner described
l below
documents are loaded into document transport 200
by means of document hopper 202. Single documents are
loaded from document hopper 202 via feed drum 204. The
documents are then passed along document transport 200
between rollers and the endless belts snot shown).
The first section of document transport 200,
! reader section 206, includes an optical character reader 208
and a magnetic ink character reader 210. Those skilled in
l the art will appreciate that a single model optical reader,
i such as the 30-250 its read head manufactured by Input
Business Machines, Incorporated of Rockville, Maryland, can
function as either an OCR reader or may be utilized to opt
tidally read MICRO characters with appropriate control elect
l ironies. OCR reader 208 may be utilized in the applications
¦! wherein the amount field or other information is printed in
Al an OCR format.
The next section of document transport 200 is
encoder section 212. Encoder section 212 includes hammer
bank assembly 214 and die and ribbon assembly 216 and is
utilized to encode selected documents with selectable
indicia, while the document is traversing document transport
200. The operation of the encoder section will be explained
in greater detail with reference to Figure 3.
llSection 218 of document transport 200 is the
! end son section. Endorser section Z18 contains ink jet
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Imprinters 220 and 222 and endorser 224. Ink jet printers 220
i! and 222 are standard state of the art ink jet printers that
iamb be utilized, in the disclosed embodiment, to print
'Selected indicia upon each document which passes through
lldocument transport 200. The selected indicia may be utile
sized to assist in audit trail functions or in any other
function desired. Endorser 224 is utilized to endorse
documents such as checks. The structure and operation of
I endorser 224 will be explained in greater detail with
respect to Figure 4.
The next section in document transport 200, through
itch each document is transported, is camera section 226.
I Camera section 226 contains, in the embodiment disclosed,
Tao digital video cameras, 228 and 234 and two illumination
if¦ sources, 230 and 232. Each document which passes through
camera section 226 is scanned on both sides utilizing video
cameras 228 and 234. The operation of camera section 226 is
explained below with reference to Figures 5 and 6.
I The penultimate section of document transport 200,
microfilm section 2361 contains a microprocessor controlled
microfilm recorder 238. Microfilm recorder 238 is described
in greater detail below, and is utilized to provide hard
copy of selected documents which have been processed by the
system of this invention. Microfilm recorder 238 is capable
11 of accurately recording documents traveling at greater rates
of speed than that present in earlier sections of document
transport 200, and as a consequence, the transport speed is
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increased in microfilm section 236 to a nominal speed of 100
I inches per second. This transition is accomplished by
I utilizing a slipping drive at the interface between micro-
i film section 236 and camera section 226. Thus, while a
, portion of a document is still traveling at a nominal speed
luff 52 inches per second in camera section 226, the slipping
Drive (not shown) in microfilm section 236 allows the
document to slip until fully released.
if The final section of document transport 200 is
1 stacker section 240. Stacker section 240, in any manner
well known in the art, sorts the documents processed through
l document transport 200 into one of several pockets. The
! number of pockets is, of course a design choice wholly
l dependent upon the application desired.
1 As those skilled in the art will appreciate, the
modularity of design employed in document transport 200 will
hallow great flexibility in many applications. whole sections
I of document transport 200 may be deleted or rearranged to
Permit a wide variety of custom applications. Further, thy
Number and type of devices within each module may be increased
or decreased as a matter of design choice.
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if ENCODER
I¦ With reference now to figure pa, there is depicted
1! a schematic view of encoder 300 of the present invention
i! An important feature of the present invention is an ability
It encode continuously moving documents. On known document
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jlprocessing systems document encoding proves to be the major
bottleneck to high speed processing. Typical solutions have
¦ included a separate slower portion of the document processor
Jo in which a document is stepped through an encoder, or a
I separate off-line encoder. Document encoder 300 is capable
¦ of encoding documents which are continuously moving at the
rate of the document processing system of the present invent
lion.
Document encoder 300 utilizes, in the illustrated
llembodiment of the present invention, two identical electron
magnetic hanker banks, hammer bank 302 and hammer bank 304.
It will be apparent, however, upon reference to the fore-
I going explanation, that a fewer or greater number of hammer
! banks may be utilized in systems wherein slower or faster
, transport speeds are desired. Hammer banks 302 and 304 are
electromagnetic hammers such as part no. CCE-05-306 menu-
lectured by Data products, Woodland Hills, California. Each
¦ hammer bank is controlled by a Henry driver. In the disk
closed embodiment, hammer driver 306 controls hammer bank
¦ 302 and hammer driver 308 controls hammer bank 304 Hammer
power supply 310 provides operating power for all hammer
drivers and hammer banks.
Positioned opposite each hammer bank is an apt
l propriately encoded die. The selection of characters utile
! iced in a particular application is strictly a design choice
and may include OCR characters, MICRO characters or any other
desired character pattern. The illustrated embodiment
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includes two substantially identical die sets, die set 312
Andy die set 314. However, as a matter of design choice, a
ilsingle die set may be utilized. Also included in the thus-
trotted embodiment is microprocessor control 316, which
provides control signals to hammer drivers 306 and 308 in
response to signals from optical sensor 318. Optical sensor
318 is utilized to detect the presence of a document along
, document path 320. Ribbon mechanism 322 is also depicted in
Figure pa, and will be explained in greater detail with
¦ reference to figure 3b.
Figure 3b depicts a partially diagrammatic view of
the major components of document encoder 300. As explained
I above, hammer banks 302 Andy selectively strike portions
,1 of die sets 312 and 314, upon receipt of control signals
Generated by a microprocessor control 316 (see Figure aye,
in conjunction with an item presence signal generated by
optical sensor 318.
.¦ Ribbon mechanism 322 (figure pa) is shown in
Ijgreater detail in Figur,e.3b and includes a ribbon supply
I reel 324, ribbon wakeup reel 326, ribbon tensioning arms 330
and 332 and ribbon capstan 33~. Ribbon supply reel 324
provides a fresh supply of magnetic ink ribbon 340. Such
magnetic ink ribbons are typically single strike ribbons,
that is to say the magnetic ink associated with each char-
1 cater is totally removed from the ribbon during the printing
of that character and further attempts to print utilizing .
the some section of ribbon 340 will result in invalid
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i magnetic signatures. Therefore, it is necessary to advance
magnetic ink ribbon 340 after each character is printed, and
it is advantageous, from an economy standpoint, to advance
. ¦ ribbon 340 only while a document is present in encoder 300.
1 This is accomplished utilizing ribbon capstan 338 which it
electronically controlled by microprocessor control 316
I during those periods when a document is detected by optical
sensor 318. For reasons which will be explained below,
. I ribbon 340 is driven by ribbon capstan 338 at the same speed
1 as documents on the transport. The rapid acceleration of
ribbon 340 to transport speed it accomplished without
damage to ribbon 340 utilizing ribbon tensioning arms 330
and 332. Ribbon tensioning arms 330 and 332 are pettily .
l mounted at point 342 and resiliently biased utilizing !
springs 334 and 336. A rapid acceleration of ribbon 340 is
'I then absorbed by ribbon tensioning arms 330 and 332 until
Jo ribbon supply reel 324 and ribbon wakeup reel 326 can
! compensate. , ' '', i
Jo In operation, encoder 300 utilizes two character
I sets to compensate for the duty cycle of the hammer bank
I¦ utilized. Each individual hammer within hammer banks 306
I and 30~ has a duty cycle of approximately .004 seconds.
- Jo Document encoding standards for MICRO require individual
. characters to be encoded approximately one-eighth inch
! apart, or one-tenth inch spacing for OCR. At a nominal
, transport speed of 52 inches per second, a document will
travel one elgheh owl in asp oxlmately .0024 seconds. It
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llshould therefore be apparent that with a duty cycle of .004
seconds a single hammer and die combination will be unable
Vito repetitively strike a single character at one-eighth inch
intervals Thus, the use ox multiple hammers and sub Stan-
lltially identical character sets will allow full encoding at
the present duty cycle. Consider a possible worse case
analysis, a desired encoding of eight consecutive identical
characters. Those skilled in the art will appreciate that a
single hammer and die will be able to encode alternate digit
Impositions at the stated speed of operation. The second '
group shammers and characters allows encoder 300 to fill
in the missing digits. More specifically, hammer bank 306
Ijand die set 312 may encode the odd digit positions in a
desired field, and hammer bank 308 and die set 314 may!
encode the even digit positions. Thus, it should be appear-
en that increased or decreased transport speeds may be
accommodated by utilizing greater or fewer number of
hammer banks and die sets, without requiring a faster duty
cycle or individual hammers. It should also be apparent
jlthat since certain portions of a particular digit field may
jibe encoded by one hemmer bank while other potions may be
! encoded by a second hammer bank, it will be advantageous to
maintain ribbon 340 at the same speed as the documents,
llpassing through encoder 300. By so doing the used portion
jiffy ribbon 340 associated with a particular chA~acter'will
Montana its relative position directly above that paretic-
ocular character on the document.
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ENDORSER
Referring now to Figure 4, a cutaway view ox the
major components of endorser mechanism 400 is depicted. A
section of a document 402 is shown on document path 404.
Tithe belt drive mechanism which transports document 402 along
document path 404 is not shown ,
if Ink roller 406 is mounted in bracket 408, which
! may be pivoted upward at pivot point 410 to allow replace-
immunity of ink roller 406. Additionally, pressure adjuster 412 ,
1 may be utilized to adjust the amount of pressure exerted by
! ink roller 406 upon transfer roller 414.
Transfer roller 414 is mounted in tangential
l proximity to endorser plate 416 and is utilized to transfer
I ink to endorser plate 416 from ink roller 406. Transfer
! roller 414, endorser plate 416 and platen 418 are all driven
i by belt 42~ and belt 422 and drive pulley 424; however,
electronically controlled clutch 426 is utilized to select
'Itively engage endorser plate 416. Thus, when it is desired .
to endorse a selected document, ink is transferred to en-
lldorser plate 41S and electronic clutch 426 is energized,
'lunging endorser plate 416 into contact with platen 418 and
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irritating endorser plate 416 and platen 41~ at an appropriate
. speed.
l Electronic clutch 426 is controlled, in a pro-
¦ furred embodiment, utilizing an appropriately programmed
l microprocessor type device. Therefore, documents may be
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Transported through the document processing system of the
present invention and be selectively endorsed.
if VIDEO CAMERA
I.¦ Figure 5 depicts a diagrammatic view of a system
utilizing two video cameras 50Q and illumination sources 502
whereby the image on both sides of a document may be cap-
~jtured. Each illumination source 502 is comprised of two 500
Lotte tungsten halogen bulbs, encased in a housing having
llcooling means and an optical focus assembly 504. Optical
okays assembly 504 comprises a plurality of lenses arranged,
yin any manner well known in the art, to focus a vertical bar
of intense light onto document plane 506. In the embodiment
l¦aisclosed, the vertical bar is generally rectangular in
Shape and is approximately six inches tall and one tenth of
loan inch wide. As discussed above, documents are transported
jllaterally across this illuminated portion to enable video
image capture. ,
I¦ The light reflected from each document passes
through each camera lens assembly 508 and is focused on line
scanner 510. Camera lens assembly 508 is a fixed magnify- ¦
location ratio lens typically utilized in fixed working disk
Tunis applications such as photographic enlargers. Line
llscanner 510 is a solid state line scanner such as those
Commercially available from the Retaken Corporation of
Sunnyvale, California. Line scanner 510 is a high density
monolithic, linear array ox silicon photo diodes with
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If . .
integrated scanning circuits for serial readout. The array,
in the embodiment disclosed, consists of a row of 76~ silicon
photo diodes, having a storage capacitor associated therewith
lupine which may be integrated the photo current, and a tray-
S jjsistor switch for periodic readout via an integrated scan-
¦ nine circuit The individual photo diodes of line scanner
510 are one mix square and are spaced center-to-center, one
mix apart.
. During image capture, a document is transported
Lo laterally across the vertical bar of light generated by each
I illumination source 502. Each camera lens assembly S08
, focuses the reflected light from the document onto line
skinnier 510. Each of the 768 silicon photo diodes contained
within line scanner 510 produces an electrical signal which
Lo Lois proportional to the intensity of the incident light. The
photo diodes are then sampled at a high rate, the fine
I scanner utilized in the preferred embodiment may be sampled
.1 at frequencies as high as ten megahertz. The combination of
l the lateral motion of the document and the vertical action.
'1f sequential sampling of the photo diodes in line scanner
510 will produce a two dimensional picture of a document
with a resolution within .007 of an inch.
The output of line scanner 510 is amplified and
l coupled to additional circuitry as Azores of pulses where-
. in the area of each pulse is proportional to the intensity
of the incident light on each photo diode. This series of
pulses s utilized in the camera control circuitry to sense
`
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i
. I . ' 19
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22~ I
If . . , .
the presence of a document and to dynamically adjust the
threshold level utilized to determine whether a particular
value is white or black. The series of pulses is also
¦ applied to the data compression system for compression,
storage and subsequent retrieval.
Jo CAMERA BUFFER AND INTERFACE CIRCUITRY
!¦ With reference now to Figures aye, there is
lldepicted a schematic view of the major components of the
lo camera buffer and interface circuitry of the document
processor of the present invention. While the disclosed
embodiment of the present invention utilizes two video
cameras, in many cases only one set of buffer and interface
I circuitry will be depicted Those ordinarily skilled in the
! art will appreciate the simple duplication of circuitry .
necessary to accommodate two video cameras.
Referring now to Figure pa, oscillators 601 and
l 602 are utilized, in conjunction with the basic clack signal
¦¦(3~.5 megahertz in a preferred embodiment) to provide the
scanning pulses to lone scanner 606. Oscillators 601 and
;,602 are implemented, in a preferred embodiment of the pros-
en invention, utilizing standard 74S74 type flip-flop
llintegrated circuits. The control pulses necessary to open- ¦
; late line scanner 506 are applied via amplifiers 6Q3, 604 and
I 605, which are utilized to provide level adjustments. Line
scanner 606, in the illustrated embodiment, is an RL-76~C
integrated circuit manufactured by the Retaken Corporation
l . ' '' ','',
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-20-
I LIE
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of Sunnyvale, California. Additional details concerning the
construction of line scanner 606 are disclosed above with
respect to the video camera description. Line scanner 606
Lois scanned at a parallel rate of three megahertz. That is,
Thea odd numbered cells in line scanner 606 are scanned at a
Thor megahertz rate and the even numbered cell are also
scanned at a three megahertz rate. Thus, line scanner 606,
with proper multiplexing of the dual outputs, is capable of
l generating video pulses at-a six megahertz rate.
1 Even cell and odd cell outputs of line scanner 606
are applied to amplifier 611 and 610 respectively. Amply-
liens 611 and 610, in conjunction with capacitors 607 and
608, are utilized to capture the output of each individual
l scan cell. Switching transistor issue utilized to alter-
'Natalie remove all charge accumulated on capacitors 607 and
608 between sampling times for adjacent cells of line scan
nor 606. The RESET signal accomplishes this and is applied
! to switching transistor through inventor 612.
!¦ The outputs of amplifiers 610 and 611, represent-
sling the relative charge present on capacitors an 607
liduring each cell scan, are further amplified by amplifiers
,l613 and 614, in A manner well known in the art. The outputs
I of amplifiers 613 and 61~ are next applied to two sample and
, hold circuits. The sample and hold circuits are comprised
! of switching transistors 617 and 618 and storage capacitors
l 615 and 616. Thus, the charge present on capacitors 615 and
' .' . ., ,' ..
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.
-21~
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.
¦616 is indicative ox the amount of light striking the eon-
responding scanning cells of line scanner 606 at any select ¦ !
ted time. The signals are then coupled, via lines 620 and
Ij621 to a final stage of amplification consisting of amply-
¦Ifiers 622 and 623 see Figure 6b).
i With reference now to Figure 6b, the outputs of
amplifiers 622 and 623 are each applied to two points within
the dynamic threshold circuitry. Dynamic threshold adjust-
lament is an important feature of the document processing
system of the present invention and allows a single system
Vito process multicolored documents without requiring India-
ideal level adjustments.
The output of amplifier 622, representing the
amplified outputs of the odd numbered cells of line scanner
1l606 (See Figure pa) is applied to one input of comparator
¦633 and to diode 624. Similarly, the output of amplifier
623, representing the amplified outputs of the even numbered
cells of line scanner 606, it applied to one input of
Comparator 634 and to diode 625.
;¦ Diodes 624 and 625 perform an OR function and
apply the more positive of their individual inputs to
'capacitor 626. Capacitor 626 is, therefore, rapidly charged
I alto the level of the highest signal applied through diodes
¦624 and 625. This level lo the iota threshold and
1 represents a reference point for black/light decisions. The
voltage level present on capacitor 626 is applied through
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it -22-
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! diodes 627 and 628 to the second input of comparators 633
tend 634. The voltage drop across diodes 627 and 628 assures
That the signal creating charge on capacitor 626 will be
Greater than the resultant reference signal applied to
llcomparators 633 and 634. I
Jo The charge present on capacitor 626 will eventual-
sly discharge slowly through resistors 629 and 630; however,
a reference voltage applied through diode 632 will prevent
litotal discharge and will apply a minimum level which a cell
I output must exceed in order to be considered "white."
Additionally, the time constraints associated with capacitor
626 and resistors 629 and 630, while chosen to be "slow"
with respect to individual cell sample times, are suEfic-
lintel "fast" to allow discharge of capacitor 626 between
adjacent documents. Thus, a totally white background
lldocument, while in process, will result in a high reference
signal being generated on capacitor 626, and result in any
signal greater than two diode drops below that level being
characterized as "black." However, during the gap between
zoo documents, capacitor 626 will discharge sufficiently so that
a colored background document (blue, for example) will
Generate a lower reference level. This system of dynamic
Reference adjustments allows a single system is process an
Ilentire variety of molted documents without system ad-
Ijjustment, and without the possibility of losing all data
'contained Oil a relatively dark background document.
Al . .. ..
-23-
'I - . i
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if Fierceness of circuit design not important to the
I concept, an inverted output is selected from comparators 633
I and 634. Therefore, a particular cell in line scanner 606
¦ which dejects a "black" area will result in a logic 1 or
1 "high" output of the appropriate comparator, and a cell 1,
which detects a "white" area will result in a logic 0 or
''low'' output from the appropriate comparator.
Referring now to Figure 6c, the document detection
llcircuitry of the document processor of the present invention
issue depicted. The odd and even numbered cell outputs from
Comparators 633 and 634 (See Figure 6b) are applied to shift
register 635. Shift register 635 multiplexes the dual three
megahertz signals into a single six megahertz video signal.
one output of shift register 63,5 is applied to shift Russ-
if ton 636. Shift register 636 is loaded each time a "black"
'cell is detected and shifts each time a "white" cell is
detected. After eight consecutive "white" cells have been
detected, the output of shift register 636 is shifted out
Rand sets latch 640. Latch 640 is a simple JO type latch and
I is utilized to generate the signal which indicates the scan
Lucy active (ACTSCN~). ,
The output of shift register 635 is also applied
to counters 637 and 638. Counters 637 and 6,38 are the
l leading edge detectors and are reset at the end of each swan
! through line scanner 606. Counters 637 and 638 are utilized
jjto count "white" cells in a single scan. If sixty-four
Lotte" cells are detected in pa single scan, counters 637
l , : . !
I . '' ' .
!
~225
l .
joined 638 set latch 639. Latch 639 is also a simple JO latch
- hand is utilized to set edge detection latch 642.
The output of edge detection latch 642 is utilized
Into generate the signal which indicates a document is present
,I(ITMPRSl). The output of latch 639 is also applied to
counter 641.
¦ Counter 641 is the trailing edge detector.
Counter 641 is utilized to count the number of complete
jjscans in which less than sixty four "white" cells are de-
Ijtected. If sixteen such scans are counted, the output of
Counter 641 is utilized to reset edge detection latch 642.
Header 644 is merely a connection means to allow compete-
ability between systems which utilize a single video camera
Jan systems which utilize two video cameras.
I! Figure Ed depicts a series of counters and aegis-
titers utilized to provide operating information to a con-
lltrolling microprocessor type device. Counters 645a-645f are
jlutilized to count the total number of active cells in a
particular document. The number counted is latched into
llregisters awoke and is available upon query by the
control device. Similarly, in applications utilizing two
video cameras, counters 647a-647f are utilized to count the
lltotal-number of active cells in the second side of a par-
; llticular document and registers awoke store the total
Count
Figure ye depicts further counters and registers
¦ used to provide operating inoFmation. Counters aye
. . ' ,,.
'I
if -25-
. i
25~56
count the total number of lines scanned yin a particular
document and latch that number into registers aye and 650b.
Similarly, counters awoke are utilized to count the
I total number of lines scanned by the second camera and that
' number is latched into registers aye and 652b. Thus, by
knowing the total number of cells and the total number of
scans, a control device may simply divide to calculate the
exact dimensions of a particular document.
. ¦ Also depicted in Figure ye is bus driver 653. Bus
¦ driver 653 is utilized to drive or amplify data being read
! from any of the interface registers to permit transmittal to
, a microprocessor type control device.'
Referring now to Figure of, there is depicted a
If series of input and output latches utilized to provide
l' communications to and from a microprocessor type control
I device. Latches 654, 655, 656 and 657 are utilized to latch ¦
in information from the control divest the'sys~em.
¦ Information and/or commands that test, clear ox arm the'
I system are received and latched into the'appropriate'latch. ¦
I Information received may be utilized to appropriate'com-
, mends, such as depicted with logic gates Audi.
'' .
Information, device identification returning test
¦! data and busy indications may be latched into latches 659,
Jo 660, 661 or logic gate 662 for access by a control device.
I With reference now to Figure 6g, there is depicted
If additional address and control circuitry switch 666 is a
¦¦ multiple position DIP switch which may be set in a unique
:
26- ' '
' I
I! ~L225:156
If I
¦! pattern to specifically identify a particular transport and
camera recalling that a system may include additional
¦ transports as a matter of design choice. The positions of
¦ the various switches in switch 666 are coupled to comparator
¦ 664 for comparison with the eight address bits generated by
the microprocessor type control device. Theist is posy
sidle for the control device to accurately address a single '
i one of a plurality of devices. If comparator 664 indicates
¦ an address match, a valid address signal LAD is goner-
¦ axed. '
Once a valid address has been detected, the first
four bits of address, A, Al, A and A are utilized to
address up to a maximum of sixteen addressable registers on
l the addressed device. Bus driver issue utilized to couple
¦ these address bits to the addressable registers. Bus driver
!¦ ~65 is utilized to couple control commands and the A address
l bit. The A address bit is utilized, in the illustrated
j embodiment, in conjunction with the valid address signal to
j designate either of two video cameras, utilizing logic gates
I 667d and eye. Logic gates awoke are utilized in con-
junction with other decoded commands to generate internal
tread and write commands.
Referring now to Figure oh, there are depicted six
decoders utilized to decode command and address information
from the control device. Decoders 66~ and I are utilized
during a memory write command to either video camera.
Decoders 670 and 673 are utilized when the control device '
. . '' ,' ,
. .' ''''. "' ' '.
If
if -27-
5~L56
tissues a memory read to either camera Decoders 67i and 674
decode thy commands which access the total cell number and
total scan number registers depicted in Figures Ed and ye.
Finally now, with reference to Figure I, there is
1 depicted the output circuitry associated with the video
camera of the present invention. The depicted embodiment of
l the present invention utilizes eight separate video buses to
¦ transmit video data between various components of the soys-
I them. This group of buses is collectively referred to as the
' X bus, and any single bus may be selected for any single
¦ device to utilize.
I Control signals from the control device are de-
! coded utilizing decoders 675, 676, 677 and 678. Decoder
¦ 675, 676, 677 and 678 may be implemented, in a preferred
1 embodiment, by an integrated circuit ox the type 74LS138
¦ manufactured by the Signetics Corporation of Sunnyvale,
California. The outputs of decoders 677 and 678 are utile
iced to enable selected three state buffers. Three state
' I buffers Audi, in the illustrated embodiment, will
! couple the data from one camera to one of four video buses
while three state buffers awaked will couple the data
from a second camera to one of the four remaining video
blouses.
.
.. .,. ., . .
. .' ''.'
l -28-
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l ~;~2~56
¦ DATA COMPRESSION SYSTEM
l With reference now to Figures 7 and 8, there is
i depicted a schematic representation of the circuitry of the
Dwight compression system.
¦ Referring now to Figure pa, the system clock and
l its complements are applied to the inputs of high speed
i differential comparator 70~, which acts as a high speed line
¦ receiver. In the disclosed embodiment, the system clock is
a 30.5 megahertz signal generated utilizing a crystal con-
l trolled oscillator (not shown). The output of comparator 701
l is applied to multi vibrators 702 and 733, where the frequency
¦ is halved in a manner well known in the art.
The output of multi vibrator 702 is applied to four
bit binary counter 704, where the halved clock frequency is
further divided into lower frequencies which are utilized
¦ throughout the system.
Cross point switches aye, 705b and 705c are
utilized by a microprocessor type control device to select
, one of eight bus lines to be coupled to the data compression
system. The cross point switches utilized in a preferred
embodiment of the present invention are Signetics type
,SD5301 switches. As previously mentioned, the eight line
I bus referred to as the X bus is comprised, in one embodiment
¦ of the present invention of eight three wire bus lines,
¦ Each bus line has a ready line, a clock line and a data
¦ line. The particular bus selected by Ross point switches
.' ' '''""
l -29-
l;~Z5156
aye, 705b and 705c is controlled by bus control register
l 706, in response to commands from a microprocessor type
¦ control device.
¦ Bus control register 706 is utilized to control
cross point switches aye, 705b and 705c in conjunction with
shift register 707. Shift register 707 is a parallel in-
serial out PUS) register which is utilized to serialize
the command data from resister 706 and couple that serial-
I iced command data to set up the cross point switches.
¦ Shift registers aye and 708b are utilized in
conjunction with logic gates aye, 709b, 709c and 709d to
enable cross point switches aye, 705b and 705c and to
l control register 706 when data is being written into aegis-
¦ ton 706. By controlling data into register 706 and the
l¦ clocking of that data out of shift register 707, the open-
l anion of the cross point switches is carefully sequenced.
¦ In the event that the selected X bus line is
occupied, or when a pause signal indicates that incoming
! data must temporarily stop, circuitry is present which will
llcease data input to the data compression system. A not
already condition out of cross point switch aye or an intern-
Ijally generated pause signal at the input of NOR gate 710
Wylie generate a signal (BUSY) which will stop the operation
I of multivibra~or 703, and thence the operation of the output
¦ 25 I section.
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so
Also depicted in Figure pa is end of data clock
711. Clock 711 is a simple multi vibrator which is utilized
to generate the end of the output data signal
Referring now to Figure 7b, there is depicted the
circuitry by which the microprocessor type control device
may accurately address the data compression system and
various registers within the data compression system.
Jumper wire switches aye and 712b are utilized
with various apex wires to provide a unique-addréss for
the data compression system. Buffers aye and 713b are
utilized to receive a board address and register address
! from the control device. Each board may contain up to
sixteen separate addressable registers (or thirty-two
! including read only and write only registers) and therefore-
1 four bits of address AYE are utilized to select a aegis-
l ton.
i The remaining address bits are coupled to come
portrays aye and 714b where they are compared to the ad-
l dress of the data compression system board, as determined by
1 the placement of jumper wires in jumper wire switches aye
and 712b.
Control signals from the control device are coupled
to buffer 715 and one of eight decoders Audi are utile
¦ iced to decode the selected register address to determine
1 which register will be read or written to by the current
command.
I
. .. ....
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. -31-
2~;~L56
,
Logic gate 717 is utilized to receive the INITIAL
signal and is utilized to generate the signals which initial-
ire various other portions of the data compression system.
Figures 7c and Ed, when placed side by side in the
I manner indicated in those two figures, depict a schematic
representation of the "spot remover" circuitry of the elate
ccimpression system of the present invention The spot
remover circuitry is utilized to remove any single black
i "spot" from the data which corresponds to a particular
¦ image. A spot is defined for these purposes as a single
black cell detected by line scanner 606 (see Figure 6), that
if it surrounded by white cells.
¦¦ Referring now to Figures 7c and Ed, the data
stream representative of a scan through a document is
lo l coupled to an input of register aye and then out of fog--
inter aye and into delay register aye. Delay register
aye is, in a preferred embodiment, a 1024 bit random access
l memory that is utilized in the manner of a long shift fog-
i inter.
¦ The data out of register aye is written into
l delay register aye at an address determined by address
¦ generators awoke. Address generators awoke are
initially loaded to a number which correlates with the
number of cells in each scan for a particular document or
I group of documents. Address generators awoke are four
bit counters which are utilized to control the addresses in
delay no inters aye and 719b. Thus, the data from register
I . I, ., , " , .
.
!
,1 -32-
L2251~;
! aye is written into an address of delay register aye which
I will result in the leading edge of data exiting delay aegis- ¦
ton aye at the end of each scan.
The data exiting delay register aye is coupled to
¦ register 718b and to the input of delay register 719b. As
above, the data in delay register 719b is delayed for the
I length of a scan and is then coupled to register 718c.
! Those skilled in the art will appreciate that thus con fig-
i uratlon will result in a sample of the current scan being
¦ present in register aye, a sample of the previous scan
I being present in register 718b, and a sample of the next
previous scan being present in register 718c.
It is therefore a simple matter to examine the
I surrounding cells, utilizing logic gates aye and 721b, and
to determine whether or not a particular black cell is a
"spot" that should be removed. Logic gate 723 compares the
single cell with the surrounding cells and generates the
signal which removes the spot. Wire jumper 724 is provided
l to allow the spot remover circuitry to be disabled, if that
i is desired in a particular embodiment.
Register 725 is a four bit, parallel access shift
register which is utilized, in conjunction with flip-flop
726, to generate write enable signals and various system
clock signals.
1 With reference now to Figures ye and of, which
¦ when placed side by side in the manner indicated in the
drawings, evict the con memory address selector. The
I
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IL -33-
25156
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¦ data associated with a plurality of adjacent scans through a
document must be stored and examined to permit data compress
I soon, and such storage must be accomplished in a precise
¦ manner to permit later synthesis of a document image. In
1 order to accomplish this storage in an orderly fashion, the
number of scans and the number of cells in each scan must be
carefully tracked.
Comparator 725 in Figure of is utilized to compare
the number of cells in each scan with an incremented address .
1 The number of cells in each scan is loaded into the data
, compression system, by a control device, through registers
which are not shown. The incremented address which controls
the storage location of incoming data is generated by scan
memory address generators aye, ?26~ and 726c. Address
generators aye, 726b and 726c are four bit binary counters
which are initialized and then utilized to count to an
¦ address which corresponds to the number of cells in each
scan as determined in comparator 725. When the address thus
. I generated is equal to the number of cells in a scan, the
20 I process is repeated. .
Each time comparator 725 detects the end of a
. scan, the output signal is coupled Tuscan counter 727.
¦ Scan counter 727 is utilized to keep track of the number of
. scans stored, because, as will be explained below, the data
! compression system of the present invention operates with
twelve scans in temporary storage in scan m morn.
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Read address generators aye and i28b are utilized
to generate the addresses which will be utilized to read the
scan data from temporary storage in the scan memory. A
separate read address generator is necessary because as will
be explained herein, the scan data in temporary storage is
read out of the scan memory in a different order than the
order in which it was stored.
I Multi vibrator 729 is utilized to initiate the
address generators and read address generators at the
1 beginning of operation. Parallel access shift register 730
¦ and multivibra~or 731 are utilized to develop various clocks
and reset commands utilized to operate the data compression
system of the present invention. Buffers 732 an-d 733 are
utilized to buffer and isolate the clocks and reset signals
so generated.
Figures 7g and oh, when positioned side by side in
the manner indicated in the figures, form a schematic
diagram of the scan memory previously discussed. Each of
the memory blocks depicted, Audi, Audi and aye-
736d are implemented utilizing a 1024 bit random access
memory. Thus, each memory block may temporarily store one
complete scan through a document, recalling that a scan may
consist of up to seven hundred and sixty-eight separate t
I cells of line scanner 606 of Figure 6. Further, the scan
1 memory formed by the combination of memory blocks Audi,
Audi and Audi may temporarily store twelve India-
ideal scans.
. ' ,'.
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I 6
I Figures I and 7j, when positioned as indicated in -
Thea figures, form a schematic diagram of the address multi-
l pled circuitry of the scan memory of the present invention.
¦ Address multiplex circuitry is necessary because,
, although the data obtained from line scanner 606 (Figure 6)
l is obtained and written into temporary storage in the scan
¦ memory in a vertical format (with respect to the document
image), experimentation has shown that maximum data come
l press ion will occur with analysis of that data in Arizona-
¦ tat format.
As previously discussed, the scan memory formed by
memory blocks Audi, Audi and Audi (Figures 7g
l and oh) form temporary storage for twelve complete vertical
! scans. The data within the scan memory is analyzed horizon-
¦ tally in groups of four scans. Therefore, the twelve memory
¦ blocks are further broken down into three groups, two of
which are being read while the third group is being written
into.
I The two groups being read are referred to as the
¦ current data and previous data. The previous data repro-
¦ sets the previous four scans prior to the current four
scans read into the system and is maintained in temporary
l storage to determine what, if any, relationship exists
¦ between that data and the current data. This examination is
I necessary to detect possible redundancies which may be
l removed and replaced with coded equivalents.
' I . ' I.
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Jo The described system of vertical writing and
horizontal reading requires address multiplexing to insure
I proper operation. Consider the subgroup of four memory
I blocks into which data is being written. A memory block is
1 enabled, an address is supplied from scan memory address
! generator awoke (Figure ye), and the address is inane-
! minted until comparator 725 (Figure of) indicates the ad-
¦ dress has reached the end of the number of cells in a scan.
¦ Next the memory block enable signal is incremented, the
l address generators are initialized and the process is no-
peeled until four scans are written into the scan memory.
l When a subgroup ox the memory blocks is being
Jo read, an address is generated by read address generators
l aye and 728b (Figure ye) and the memory block enable signal
1 is incremented through a four count. Next, the address is
incremented and the memory block enable signal is hare
minted through the four memory blocks in the subgroup.
I Decoder 737 arts as a one of three decoder which
! enables one of the three subgroups of the scan memory at a
l¦ time. A subgroup of memory is enabled utilizing address
I multiplexes. The first subgroup utilizes address multi-
plexers Audi. Each address multiplexer is a quad two
- I¦ line to one line multiplexer. Address multiplexer aye is
if utilized to provide the chip enable signal (Of) which
Al determines which of the four memory blocks within the
subgroup is enabled. Address multiplexes 738b-d are
utilized to provide the address within the enabled memory
!
!
.
-37-
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.
¦¦ block, and the signal which determines whether data is being
¦ read from Of written to the selected address. Address
l multiplexes Audi and Audi operate identically with
¦ respect to the second and third scan memory subgroups.
I Decoder 741 is a dual one of four decoder which is
utilized to provide the read and write enable signals which
serve as the inputs to address multiplexes aye, aye and
aye. Multiplexer 742 is a dual four line to one line
l multiplexer which is utilized to select the output a
particular subgroup of the scan memory to be output as the
current data, and the output of a second subgroup to be
output: as the previous scan data.
With reference now to Figure ok, there is depicted
i the shift registers which allow examination of the scan data
1 temporarily stored in the scan memory. Current scan data is
shifted into the sixteen bit shift register formed by eight
¦¦ bit shift registers aye and 743b. Data from the previous
scan is simultaneously shifted into the sixteen bit shift
If register formed by eight bit shift registers aye and 74gb.
11 In this manner, current data may be compared to previous
data and redundancies in current data may be examined in a
bit by bit manner, as the data Schlitz through the shift
registers.
if Multi vibrator 745 is utilized to enable scan
memory address multiplexer aye, aye and aye figure I)
I after the completion of the first scan.
l I. ' !
I . . .
. . ' Jo '' .
it ' ' I
I
-38- -- __
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Referring Dow to Figure 71, multi vibrators 746 and
747 are utilized to develop the shift enable signals (SOFTEN
l and SOFTEN) which are utilized throughout the system to
lendable various shift clocks and reset signals. Multivi~
1 orator 748 is utilized to develop the duplicate enable
signal (DUPENF) which is utilized during those periods when
the scan data is duplicating previous values and the no-
l dundancy may be removed. Multi vibrator 749 it utilized to
! generate the BUSY signal in response to the signal India
kowtowing the system is armed and that data is being clocked
lunate the system.
'¦ Four bit binary counter 750 is utilized as a time
Ijout counter. Aster a signal is received indicating the end
luff scan data, counter 750 is utilized to provide the signal
wish shuts down the system. Flip-flop 751 and multivi-
brighter 752 are utilized to provide additional clock signals
wafter the end of data has been detected, to ensure that data
within the system is completely processed prior to system
I! shutdown.
j, Figures em and on, when joined in the manner -
indicated in the figures, form a schematic diagram of a
section of the redundancy removal circuitry of the data
Ijcompression system of the present invention
¦¦ Experimentation in the field of video image data
llcompression has proven that while examining horizontal
Sections of four Scan cells, there exist certain preùominaAt
If . ' ' ' ' ' .
39-
i
~2;~:51S6
repetitive patterns. These patterns are referred to herein
as "Q" codes, and the most common three codes are: a black
cell followed by three white cells ~1000 in binary repro-
¦ sensation); two black cells followed by two whit cells
! (loo in binary representation); and, three black cells
followed by a single white cell (1110 in binary represent
station).
In view of the above, it will-prove beneficial to
examine the scan data to determine if a series of these Q
codes are present. To that end, current data present in
l shift registers aye and 743b figure ok) is coupled to Q
! code logic array 753. Logic array 753 is a field program-
¦ marble logic array such as the 82S100, manufactured by
! Signetics of Sunnyvale, California. Logic array 753 is
1 utilized to determine first, whether or not one of the
aforementioned three Q codes is present in the first four
positions of the sixteen bit logic array, and second, how
many repetitions of that code are present. It will be
apparent to those skilled in the art that up to four con-
secutive your bit Q codes may be present at a single time in
logic array 753.
I The current data present in shift registers aye
¦ and 743b is also simultaneously coupled to black/white logic
¦ array 754. In a manner similar to the operation of logic
1 array 753, logic array 754 examines the first bit present to
determine whether it is black or white, and secondly how
many got captive blacks or whites follow the first bit.
.' ., '' , ,':''''', , .
.
. ~40-
', I So
,1 .
¦¦ In the preferred embodiment, logic arrays 753 and
11754 are utilized to detect the state of the data coupled
thereto and to ensure that the redundancy present is a
least eight bits in length. This requirement is a design
choice; however, since the redundancy to be removed must be
replaced with an identifying code and an-indication of the
length of the redundancy (count), eight bits seems to be a
practical minimum length.
¦¦ The state of the data in logic array 753 and 754
1 is coupled to transparent latches 755 and 756 respectively.
l The output ox latches 755 and 756 are coupled to latches
¦ aye and 757b, each ox said latches formed by one half of a
single twenty pin latch circuit, and to the address pins of
count memories 758 and 759. Count memories 758 and 759 are
¦ utilized, in conjunction with four bit binary counters 760
¦ and 761, to disable transparent latches 755 and 756 for a
selected period of time. Disabling circuitry is necessary
to avoid various problems present during data shifting.
l Those skilled in the art will appreciate that a Q code, as
1 previously defined, loses its identity if shifted one bit.
'Therefore, if four Q codes are detected in logic array 753,
flit will ye necessary to disable latch 755 until sixteen bits
jive been clocked through, to determine if additional Q
kids are present. To this end, the output of latch 755
jowl address a value in count memory 758. Counter 760 will
dozily latch 755 and continue to do so until the selected
CUD- in c unto memory 758 is achieved.
I . ,, I, .
I
-41-
'. ' lo , . I
2~5~5;~i 1
! ¦
I Similarly the output of latch 756 will be utilized
into address a value in count memory 759 and counter 761 will
disable latch 756 to allow the identified data to be shifted
i out of logic array 754. A slight difference in operation is
j utilized if logic array 754 contains data which indicates a
I series of black cells in the scan. In this case, the latch
¦ will be disabled until the last three black cells in the
previous group have been shifted to the first three post-
¦ lions in logic array 754. At this point, the data will be
¦ examined to determine whether or not the last three black
Cells comprise the beginning of a Q code. This operation
llrepeats until the last black cell is shifted out.
I Multi vibrators 762 and 763 are utilized to enable
I latches aye and 757b. Each time a particular redundancy
! has been finally coded and output by the data compression
system, Itches aye and 757b are enabled to latch in the
outputs of watches 755 and 756.
Referring now to Figure JO, two other possible
stouts of scan data may be determined. First, in the event
thought the stream of data examined by the data compression
system is not wholly black or white, or comprised of a group
lo consecutive Q codes, it is still possible that redundancy
exists in that data. The most easily detected redundancy
isle exist when the data from the current scan, while
Al varying in no discernible pattern' may entirely duplicate
the data from a proviso scat. one ~ch exile okay be an
I ., , , ' " ' ' "
. ' ' ' ,''''
.,
i . .'
i -42-
i
! intricate but repetitive border or edge design on a check or
other document.
Such cases asp identified using logic array 764.
. . 1 Logic array 764 can simultaneously examine eight bits of
1 current data and eight bits of previous data to determine
whether or not the data is duplicative. In a manner similar
. to that explained above with respect to black or white data,
the output of logic array 764 is coupled to transparent
l latch 765. The output of transparent latch 765 is coupled
¦ to count memory 766 and is utilized to address a value which
is coupled to four bit binary counter 767.
i Binary counter 767 is utilized to disable latch
. 765 while data is being shifted through logic array 764. In
the disclosed embodiment, as a matter of design choice, if
lo the data changes from one code to another and the duplicate
code was available at the beginning of the current code, the
¦ code will be changed to a duplicate code if the data being
! duplicated also changes and duplicates for at least five
I¦ additional bits.
I! If the duplication of previous data does not
, duplicate for at least five additional bits of scan data,
.- i then the data compression system will code out the old code
, and change to the new code and begin to encode the new
.. values of scan data.
. ' After a previous redundancy has been identified,
cod d and output from the data compression Swiss of the
Al :
,1 ~43-
I 6
! present invention, latch 768 is enabled, latching in the
next type of redundancy to be coded.
Multi vibrators 770 and 771 are utilized to latch
; in the duplicate data mode throughout the data compression
¦ system of the present invention and to continue the dipole
gate data mode beyond a change in state of data if the
duplication continues for at least five additional bits of
scan data.
l As a last resort, if a series of Q codes, black
lo I cells, white cells or duplications are not present, the data
compression system of the present invention will store
actual data, without compression. To overcome such a deter-
¦ munition (referred to herein as "mapping" or a "map" lung-
lion) a minimal amount of redundancy is required before the
1 data compression system will begin encoding data. As a
matter of design choice, the disclosed embodiments will
i cease mapping and begin to encode data if at least eleven
black or white cells are detected, at least three kinesic-
I live Q codes are detected, or any combination of codes which
1 exceeds eleven bits. Logic array 769 is the mapping terming
anion logic array and is utilized to examine the scan data
; for the previously enumerated situations which will overcome
! the mapping function.
¦ Referring now to Figures pa and 8b, which when
! joined in the manner indicated in the figures 9 fox a
schematic diagram of the count and code out circuitry ox the
data coup session system of the present invention.
'
i
.' I . .
I -44-
~2~:5~L56
Logic gates aye, 801b and 801c are utilized in
conjunction with the logic gates associated therewith, to
encode the output of latches aye and 757b of Figure em, and
l couple that data to quad two input multiplex 803. It should
¦ be recalled that the data in registers aye and 757b repro-
l sent the code currently being utilized in the data come
I potion system. ¦
Similarly, logic gates aye, 802b and 802c are
l utilized, in conjunction with the logic gates associated
¦ therewith, to encode the outputs of latches 755 and 756 of
Figure em. Latches 755 and 756 are the transparent latches
utilized to hold the data which represents the next data to
l be utilized in the data compression system. Thus, when a
i section of data is output by the system, tile next data to be
coded out is switched through multiplex 803.
¦ Those skilled in the art will appreciate that in
addition to the type of redundancy being removed from the
data stream, it will be necessary to include the length of
l the redundancy in order to allow eventual reconstruction of
! the redundancy. To this end, counters 804, 805 and 806 form
a twelve bit binary counter. The counter thus formed pro-
vises inputs to the field programmable logic array 807 which
I controls the coded count counters. Again, as a matter of
i design choice, the data compression system of the present
invention includes certain maximum data counts in each type
of redundancy (see Table I). The selection of a particular
maximum count is based upon requirements of thy code selected
' . ',.'''~
-45-
. . . . _ .
( f-'` /'~
It ~2~s~s~ `
l and the physical likelihood that certain redundancies occur
! with greater length than other redundancies. The longest
count acceptable in the disclosed embodiment of the present
l invention is 40~6 bits in either the white cell mode or the
1 duplicate mode. Each of the other modes has a lower maximum
¦ count, as indicated in Table I.
j When the counter formed by four bit counters 804,
,¦805 and 806 reaches the maximum count of 4095, rollover
¦Imultivibrator 808 is set on the next clock, and the output -
luff multi vibrator 808 is utilized to ensure various actions.
I¦ The lower maximum counts available for black cell
Mode or Q code mode make it advisable from a data compress
I soon viewpoint, to operate in duplicate mode or white cell
l mode if possible. Multi vibrator 809 is utilized, to force
; 15 , the data compression system into the duplicate mode, if a
code length overflow condition is reached by counters 804,
! 805 and 806 in other than the white cell mode (white cell
mode maximum count being equal to duplicate mode maximum
count and the duplicate mode is set. The forced duplicate
mud will also occur if a code change occurs (black to
loyalty, for example) and the duplicate mode could have been
'utilized. Multi vibrator 810 is utilized, for similar pun-
poses, to keep track of the cell count in a mapping mode of
I operation. If a map count occurs which is greater than five
! cells and less than eight, and the duplicate mode could have
I been utilized at the beginning of the count, the duplicate mode will be forced, rather than allow a map code.
. ', ' 1,
.
1 -46-
I
: Referring now to the figure formed by joining
Figures 8c and Ed in the manner indicate, there is depicted
a schematic diagram of additional circuitry including the
duplicate mode circuitry of the data compression system of
1 the present invention.
Multi vibrator 811 is the circuit element utilized
. to keep the data compression system in the mapping mode of .
operation, until one of the aforementioned special map
l termination conditions occurs. Multi vibrator 812 lo the
¦ circuit element utilized to enable a change to duplicate
code when the maximum data count occurs for a redundancy
type other than white cell (white cell maximum count being
equal to duplicate cell maximum count).
¦¦ The group of logic gates labeled 813, and the -
lo I inputs associated therewith, are utilized to enable logic
array 814 after a sufficient time period has elapsed to
allow the previously identified data to be clocked through.
l The output of logic gates issue then utilized to enable
I logic array 814, the decision logic array. Logic array 81.4
Al is utilized to determine whether-or not the code present
If should be coded out.
if Logic array 81S is utilized to control four bit
Jo counters 816, 817 and 818, which are utilized to generate
Thea coded count ox the section of data. Counter 819 is the
! duplicate mode load counter and is utilized to count the
. I number ox times the duplicate counter has been loaded.
SLY
Quad multiplexes 820, sly and 822 are utilized to
output the duplicate mode cell coded count or the coded
count of the number of cells in a black or white cell count,
a Q code count or a mapping count, as selected by logic gate
823.
With reference now to the figure formed by joining
! Figure ye and of in the manner indicated, there is depicted
buffers 824 and 825. Buffers 824 and 825 are first in-first
I out (FIFO) buffers that are utilized to control the cell
¦ count during a mapping function, to determine how many cells
are utilized during a particular mapping function
Multi vibrator 8~6 is utilized to provide additional
bits to fill up a four bit word in the FIFO data buffers in
larder to permit transfer of the cells stored theréin.!Output
llcontrol counters 828 and 829 are four bit counters which are
utilized to count the number of cells output from the buffers
ilduring the mapping mode of operation. Comparator 827 checks
the output of buffers 824 and 825 against a reference signal
alto determine if the maximum map count was coded. Comparator
1~827 is then utilized to prevent multi vibrators 881 and 832
from flushing out the remaining data stored in the map data
buffer, if the mapping function has been coded out due to a
maximum Kowtow. If the mapping function has been terminated
due to other than a maximum count (a forced duplicate mode,
or a code change) multi vibrators 831 and 832 are utilized to
flush out a single four bit byte in the data buffer to
indicate the end of a mapping function data stream.
., . ,, Jo .
'.' , ""'',,
! Logic gates Andy multiple multi vibrator 834 are
-I utilized to generate and latch out a terminal, count at the
end of transmitted data. This artificial count is referred
' to as a terminal count and is utilized to allow completion
of the compression of the final bits of data.
; ¦ Referring now to Figures 8g and oh, when joined in
the manner indicated in the figures there is detected
. multi vibrator 835, which is utilized to delay the data
. - 1 entering buffer 836. Buffer 836 is a four by sixteen bit
lo 1 FIFO buffer that is utilized to temporarily store data
, 1 during a mapping function. Recalling that a mapping cell'
l count of greater than five cells and less than eight cells
I may result in a forced duplicate mode, if duplication is
possible, it should be apparent to those skilled in the art
1 that at least eight cells in a mapping function mode must be
¦ examined before a map code is possible. Thus, buffer 836 is
. utilized to provide temporary storage until such a decision
1 1 is made. Logic gate 838, is utilized to reset buffer 836 if
I a forced duplicate mode occurs.
¦ In the event that eight mapping function mode
cells are encountered, and the forced duplicate mode is not.
utilized, multi vibrator 839 is utilized to dump the data
¦¦ from buffer aye into four by sixty-four buffer 837. Buffer
. I 837 is utilized Asia first 1n-first out buffer which stores
1 the data utilized during a map mode of operation.. Multi-
l ¦ vibrator 8 9 will also cause the data in buffer to dump
. , , ''. , ,''.
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I . : .
Jo , , I
Jo ~225~L5~
If .
¦! into buffer 837 if the data terminates prior to eight bits
and is coded out as a map code.
! Quad multi vibrator 840 is utilized in conjunction
. with multi vibrator 834 (see Figure of) to provide additional
delayed terminal count signals in the manner explained
I above. Multi vibrator 841 is the serial out clock enable
I circuit and is utilized to enable the output of buffer 837
l when it is desired to output the map data.
! Multi vibrator 842 is the master serial output
! enable latch which enables the various code, count and map
buffer outputs. Multi vibrator 843 is the load output counter
latch which is utilized to detect the fact that data is
present at the various counter control buffers, such as
buffers 824 and 825 (see Figure ye) and to load the counters.
1 Multi vibrator 844 is the transfer out parallel latch which
issue utilized to detect the terminal count signals which
indicate that each counter has reached the end of the count
desired. After all terminal counts are detected, the data
fin storage is transferred out in parallel, and latch 843 is
Then utilized to latch in new counter control data. multi-
vibrator 845 is utilized to disable the output of multivi-
orator 844, at logic gate 846, after the data has been
Transferred out, to ensure that only one set of data is
Transferred out.
Al Multi vibrator 847 is utilized to generate the
: Serial output clock to the code buffer and multi vibrator 848
i~i9 Tulsa d to generate the serial output lock to the count
'' I
--5 0--
. . :
~22~1S6
buffer. These two multi vibrators are then responsible for
. I serially outputting both the specific code and the count of
cells within that code. .
With reference now to Figure I, there is depicted
a schematic representation-of the count bit shifter circuit-
rye of toe present invention. Referring again to Table I, it
can be seen that the number of bits in a particular count
may vary from a maximum of eleven bits to a minimum of two
. I bits. In order to accurately keep track of the count in a
particular code, it is necessary Jo keep track of the most
significant bit of the count. The least significant bit of
the count is fixed and relatively easy to obtain, however,
the most significant bit must be ascertained.
¦ Logic array 852 is utilized to determine how many
I bits are presenting a particular code, The inputs to logic
I array 852 include the particular code encountered and the
number of times the count.has.been loaded. Utilizing this
input data, logic awry is coupled to bit shifters 853-
. ¦ 85S, to control the position of the most significant bit of
1 the count.
Bit shifters 853-858 airfare bit shifters with
three state outputs that shift each four bit word from zero
to three places. Thus, under the control of logic array
I 852~ it is possible to shift the most significant bit of the
count to a desired position. In the preferred embodiment,
the most significant bit of the output count is shifted into.
the first bit to be serially output.
. . . ' ,'' ' , : 1.. . ..
I ..
l .' ,'`"
! -51-
1 I
Lowe,
Referring now to Figures 8j end ok when joined in
l the manner indicated in the figures form a schematic diagram
I of a section of the output circuitry of the data compression
system of the present invention. Logic array 859 generates
the control information for the code and count logic arrays.
The outputs of logic array 859 are coupled to four beeswax-
! teen bit buffers 860 and 861. The data thus stored in
buffers 860 and 861 is utilized to control four bit counters
862 and 863 respectively. Counters ~62 and 863 axe utilized
¦ to generate selected terminal count signals.
¦ Logic arrays 864 and awry also coupled to the
code and load count signals and are utilized to generate the
actual code to be serially output (see Table I). The actual
llcode is loaded into buffers 866-869 for serial outputting.
I Buffers 866-869 are all four my sixteen bit first in-first
out buffer memories. Buffers 866-869 give the system the
¦ capability of utilizing up to sixteen bits of code; however,
l in the disclosed embodiment not all bits are utilized.
! Buffers 870-872 are the count buffers. The count
l data output from bit shifters 853-858 (Figure I) is coupled
'Vito buffers 870-872 to be serially output from the system
juicy above, buffers 870-872 are four by sixteen bit firestone
First out buffer memories. Logic gates B73 are utilized, in
l conjunction with certain outputs of counter 863 to generate
an a6ditio at terminal -ounce signal.
l ' '. ' :
i ' . '
.
L22~
- Referring now to Figure 81, there is depicted a
schematic representation of the section of the data come
press ion system that is utilized to determine the size of
l the document image. Four bit counters 874 and 875 are
utilized to divide the coded output of the data compression
system by thirty-two. Each time counters 874 and 875 reach
i thirty-two, the total in four bit counters 876-879 is
incriminated. Thus, the data in counters 876-879 represents
Lowe many thirty-two bit words are present in each image '
1¦ The outputs of counters 876-879 are coupled to
llregisters 880 and 381 where the control device may access
Thea data. Multi vibrator 882' lo utilized to store the count
flat the end of an image. Multi vibrator 882 is reset when
Lutz contents are read. Multi vibrator 883 is utilized to
lo initialize the counters by forcing the counters to a load
condition until receipt of a first data clock.
Referring now to Figure em, there is depicted a
schematic representation of the logic circuitry which allows
lea coded representation to be output from the data compress
I soon system. Logic gate 884 will allow a code out whenever
I code change is allowed (CNGAL) or the end of data has been
reached. Logic gate 885 will allow a code out during a map
function if the code is changed to a duplicate mode.
¦ Logic gate 886 will allow a code out if one of
these special map mode termination sequences is encountered,
as previously discussed. Logic gate 887 is the logic gate
which all we black cell codes to be terminated earl- to
. ... . . .. . .
: ' , ' :''' ,' ,
. . .
....
I
~L2ZS~56
begin Q code mode of operation, as discussed herein. In
conjunction with logic gate 887, multi vibrator 888 is '
utilized to ensure that greater than seven black cells have
been detected prior to allowing an early termination of
black cell mode of operation to code Q codes.
Multi vibrator 889 is utilized to detect the over-
flow condition which will result when the bit eountexs
exceed the maximum count for a particular mode of operation
In such event, the code in question is output and the system
begins counting anew. -'!
Each of the previously discussed code out signals
are applied to multi vibrator 890, which is utilized to
generate the parallel load signal which is utilized to load
out the current code and count. Multivibratox 891 is trig-
gored along with multi vibrator 890 and is utilized to select
certain multiplexes which allow Alec ahead function for
; the various logic arrays. Multi vibrator 892 is utilized to
generate a buffer overflow error signet if the data empress-
soon system of the present invention attempts to load'
additional data into the output buffers white these buffers
are full.
Referring now to Figure on, there is depleted the
; coded counters for the data compression system of the pros-
- en invention. Counter 893 is the load counter which is
utilized to determine how many times counters awoke have
been loaded. Counters aye are utilized to generate
the eddy count of the nut be of eye s in a eye out black,
I
. ., .,'
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' -54-
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,. _ . .. 1 ,.. .
.,
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If .
! white, Q code or mapping mode of operation. Referring
! finally to Figure Boy logic gate 895 and the logic gates
! associated therewith are utilized to generate an internal
¦ register full signal in the event that any one of the first
! in-first out buffers is full. The internal register full
signal is utilized to generate an error signal if additional
data is loaded into a full register.
Multi vibrators 896 and Audi are utilized to
generate a four phase clock signal for utilization in the
operation of the data compression system. Multi vibrator 896
is utilized to double the GX/2 clock from multi vibrators 702
i and ~33 (Figure pa) prom 15.25 megahertz back up to 30.5
megahertz In turn, multi vibrators aye are then
Ijutilized to divide the 30.5 megahertz clock down into a four
l phase clock in a manner well known in the art.
I .
I' MI CROFT LO SYSTEM
The document processor of the present invention
llincorporates a microfilm recorder 238 (See Figure 2) which
. if allows selective microfilming of documents during the same
pass in which several other processing functions occur.
I Thus, a. particular document may be read, encoded, endorsed,
¦ image captured, sorted and filmed during a single pass
I through the document processor.
i The microfilm system utilized within the present
invention is based upon the SMR-200B Scanner mate microfilm
recorder manufactured by the Terminal Data Corporation of
I
,. . .
,11 . ', . , ' .
If -55-
. . ., ~L:225~6
Woodland Hills, California. It will be appreciated by those
ordinarily skilled in the art that other microfilm recorders
¦ will find use in the present system, as a matter of design
choice .
Microfilm recorder 238 films both sides of
document, at a speed of up to one hundred inches per second.
The film motion is synchronized with the document transport
and a document detector, stopping between documents so that
inter image spacing is independent of other processing,
thereby ensuring maximum film usage and format continuity
microfilm recorder 238, in a preferred embodiment,
also records a program controlled sequence number and an
image count mark (commonly known as a "blip") above each
recorded image. Approximately 14,000 documents may be
¦ microfilmed on one hundred feet of 16mm. film, assuming an
average document length of seven inches. The sequence
numbers and image count marks allow rapid addressing and
accessing of individual documents. The microfilmed copies
l of the documents being processed may provide either a backup
1 system for the digital image system, or may be utilized as
hard copy archival storage for the documents in question.
I . ' , . .
DATA EXPANSION SYSTEM
Referring now to Figures pa and 9b, and the joint
j figure formed thereby, there is depicted a bloc diagram of
¦ the major components of the data expansion system of the
present invention.
'I . .. . .
I
.,,,.,',.
. i l
56
,
X bus receiver 901 is utilized to receive data
l from the specific X bus channel selected by X bus select
I ¦ 902. The data thus received is coupled to serial in-par-
. ¦ allot out register 903, and then latched into latch 904 and
S I parallel in-serial out register 905. The additional latch
and register circuitry is required to allow the receipt of
UP to eight more bits of data after toe input register of
the data expansion system is full. Logic gates 906 end 907
Lowry coupled to latch 904 and register 905 and are utilized
¦ in conjunction with X bus select 908 and X bus transmitter
909 to stop data flow during periods when the aforementioned
latch and register are full. . . .
'¦ The data in register 905 is coupled to a sixteen
ilbit, sexual in-parallel out working register 910. The
¦ 15 if number of bits shifted into register 910 is controlled by .
¦ shift counter 911. Shift counter 911 operates based upon .
! the content of sixteen bit adder 912. The initial count in
! sixteen bit adder 912 is applied to ROM address generator
,~914 which is utilized to address data within code ROM 9150
Code ROM 915 outputs additional data which is
I Leopold to sixteen bit adder 912. The new content of
: ! sixteen bit adder 912 is utilized to control shift counter
¦ 911, and thus control the number of bits shifted into
I working register 910.
US ¦ Examining the contents of Table I, it can be seen
¦ that in the disclosed embodiment the minimum number of bits
yin a Jo is three. Therefore, it should be apparent to
,, .. ,, ',. ...
.' ,',
I -57-
.1 .,
I
! I 5~5
those skilled in the art, that if adder 912 is empty, that
l condition should cause ROM generator 914 to select a code
i within code ROM 915 that will cause three bits to ye shifted
into register 910.
I As the contents of adder 912 are recognized as an
identifiable code, code ROM 915 will generate data which
Lyle allow the correct number of bits to be clocked into
register 910, and provide the bias necessary for the correct
l count. By way of example, when the system recognizes the
1 1110111 code, code RUM 915 will provide data to adder 912 to
allow eleven additional bits of data to enter register 910.
(see Table I, White Cell Mode) As eleven bits of count are
coupled to adder 912, a bias of 1024 is coupled into adder
11912 to be summed with the eleven bit number. The bias value
¦ may be coupled directly to adder 912, or, should the value
i be higher than eight bits, by means of high bias latch 916.
Code ROM 91S also generates a function code based
lupine the translation of the code initially entered into
I adder 912. The function code is applied to function latch
1 917, where it is applied to data multiple 918. Data multi-
i~plex 918 is utilized to select a voltage potential (black
cells in this embodiment), a ground potential (white cells)
a duplicate function pin, a mapping function pin, or Q code
! register 919. Q code register 919 is a recirculating
¦ register which contains each of the three Q codes previously
discussed, and may be accessed repeatedly to provide a
stream of repetitive Q codes.
'
if -58- '
~22
.
During a mapping function, no data compression was
possible and the actual data has been stored. When data
multiplex 918 selects the mapping function pin, data multi-
' I pled 918 is coupled to the input of register 910, and no-
chives actual data received from the X bus. During a dupe
ligate function data multiplex 918 is coupled to the output
of duplicate buffer 920, the operation of which will be ox-
planned below.
l The output of data multiplex 918, representing
¦ expanded image data, is coupled through serial in-parallel
out latch 925 and 926 onto a four bit wide data bus. The
image data is then coupled simultaneously to four scan
buffers 923 and 924, and four scan dupe buffer 920~ , Up to
l eight complete scans of data are selectively stored in
1 buffers 923 and 924, as sequenced by the operation of multi-
plexus 927 and 928. Four scan dupe buffer 920 stores the
most current four previous scans of data and thus permits
duplication. The output of buffer 920 is coupled back to
' I data multiplex 918 by means of register 922.
, The data contained in ~uffers'923 and 924 may now
¦ be selectively accessed by multiplex 930 to provident least
I two formats of data. The data stored in buffers 923 and 924
- Moe be output in the "scan" mode, that is, in the manner in
wish the data was captured by the digital scanning circuitry.
¦¦ This method of data output is obtained by accessing buffer
923 and reading out an entire scan, then incrementing the
scan number.
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.
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¦¦ . In other applications, it is more advantageous to
If output-ima~e data in the "ladder" mode. In the ladder mode,
jjdata is obtained from the first address in each scan and the
skin number is then incremented. After the first cell or
address has been read out of each of the four scans in
buffer 923, buffer 924 is accessed in, a similar manner.
IIThus, the ladder mode provides eight bits o~.data,.each bit
¦¦ from a different scan of the digital scanning circuitry.
Lithe next eight bits provided are from the next address in -
I each scan. The process of restoring eight scans owe data, at
one cell per scan resembles the structure of a ladder, and
therefore it described as the "ladder" mode.
Al As a final variation and possible image data
manipulation, latches 932 and 9.33 may be utilized to reverse
15 lithe order of each byte of eight bits. This technique may be
'utilized to provide mirror imaging. In systems which
utilized two digital cameras to capture the image of each
side of a document, one side will invariably be mirrored
From the other. Latches 932 Andy are utilized to correct
Tithe situation when restoring the mirrored image.
I The data out of latches 932 and 933 is coupled
through buffer 936 to output control circuitry 937. Output
control circuitry 937 is utilized to select an appropriate
lox bus channel and transmit the data. Output control circuitry
Al 937 is also utilized to control the recipe of signals from
I the X bus to indicate the availability of a particular .
channel.
l , . .
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.
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Il.
If VIDEO TERMINAL SUBSYSTEM
¦ Referring now to Figure 10, there is depicted a
immure detailed block diagram of video terminal subsystem 136
¦ (see Figure lb). Video terminal subsystem 136 is utilized,
in the document processing system of the present invention,
¦ to provide video images of selected documents along with
alphanumeric information. Video terminal subsystem 136
provides the selected video images by means of digital image
, data captured by the digital camera, in one embodiment, and
1 is utilized to allow processing of data present on documents
wish is not in machine readable format. For example, video
images may be utilized to examine signatures, to compare two
Jo signatures or to examine handwritten amount fields on dock-
laments such as checks. Video terminal subsystem 136 will
lulls find broad application in other areas wherein it is
desired to present a video image generated by digital data,
'With or without the additional of alphanumeric characters.
Digital facsimile transmission, digital document storage and
l word processing are a few of the many uses such a system may
1 find.
Video image data is transferred to video terminal
subsystem 136 by means of X bus distributor 142. Control or
, program information is transferred to video terminal sub-
! system 136 via synchronous data link control slave 138 and
i is mapped by way of direct memory access 1002 into micro- ¦
processor 1004 and memory 1006. In a preferred embodiment of
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the present invention, microprocessor 1004 is a high level
device capable of addressing external memory 1006 for pro-
gram instructions.
The video image data transferred via X bus disk
tributary 142 is coupled to an appropriate video formatter.
In the embodiment disclosed, up 'to four video formatters are
utilized with each video terminal subsystem; however,
additional subsystems may be utilized and/or the number of
terminal controllers may be modified as a matter of design ,
choice. Each video formatter contains a substantial amount
of memory and is capable of storing sufficient digital data
to support an entire image for the appropriate video terminal.
The detailed description of the circuitry and capability of
, the video formatters will be explained in greater depth with
reference to Figures Lyle and aye. Video formatters
1008, 1010, 1012 and 1014 each correspond to a single video
terminal/ namely, video terminals 1018, 1020, 1022 and 1024.
Each video terminal is coupled to an appropriate
video formatter and keyboard by means of dual terminal
controller I/O devices 1016 and 1017 and terminal I/O de-
vices 1019, 1021, 1023 and 1025. dual terminal controller
I/O devices 1016 and 1017 each differentially drive video to
two terminals and provide differential receivers and serial
to parallel conversion for inputs from two keyboards.
,25 Terminal I/O devices isle, 1021, 1023 and 1025 each receive
differentially driven video 'forgone terminal and provide
'
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'! parallel to serial conversion and differential drive for
! data from one terminal keyboard to the appropriate dual
terminal controller I/O port.
I VIDEO FORMATTER
! With reference now to Figures Lyle and awoke,
,1 there is depicted a schematic diagram of the circuit coupon
¦ ens of the video formatter of the present invention. The
I video formatter of the present invention is utilized to ,
1 provide image data and control to the video terminals of
video terminal subsystem 136 and image data to the laser
printer ox laser printer subsystem 124. In alternate em-
l~bodiments, the video formatter of the present invention will
Find wide application in various areas wherein images are
required to be stored or manipulated in digital format.
applications such as digital facsimile transmissi~n/~eception
I and word processing equipment are but a few of the many
I I applications such a device will find.
l Referring now particularly to Figures' ha and fib,
itch, when joined in the manner indicated in the figures,
depict a schematic diagram of the device control registers
and memory address generation circuitry of tune video for- ¦
¦ matter-of the present invention. Multi vibrator 1101 is
utilized to provide a power up master clear signal to
initialize the video formatter. Control register 1102 is
utilized to receive control signals from an appropriately
programmed external control,devlce. The outputs of control
¦ . ! '
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-63-
Z5156
register 1102 are coupled to the logic gates associated
I therewith and are utilized to generate various internal
control signals. The control signals thus generated are
l utilized throughout the system to ready the bus, select a
j bank of internal memory for access by the control device,
determine in what sequence data will be transferred and to
generate an interlace synchronized signal for image display.
suffer 1103 is the device identification buffer
Rand is utilized by the external control device to/determine
What type of device is coupled to the bus. Similarly,
buffer 1104 is utilized by the control device to test the
status ox the video formatter during and before operation.
In the discussion of the video subsystem it was
I stated that the video formatter could subdivide the display
into up to nine separate display zones. Multi vibrators 1105
through 110~ are utilized to address these zones. Multi-
vibrators 1105 and 1106 form the band counter, which is
¦ utilized to determine horizontal band across the display.
l Multi vibrators 1107 and 1108 form the zone counters which
1 are utilized to determine the address of the section within
¦ a particular band. Those skilled in the art will recognize
! that by utilizing two bit binary numbers to characterize
! both the band and zone address the system will have the
,1 capability of defining up to sixteen separate zones. In-
, deed, although only nine zones are visible in the disclosed
embodiment:, the rtoain.ng seven zones are utilized for
1'1 . . .
I -64-
5~5~;
i .
i horizontal and vertical retrace. In alternate embodiments,
l utilizing laser printers or other non-display devices, all
¦ sixteen zones may be utilized to provide visible image.
if Quad multi vibrator isle is utilized simply to
l provide a shift delay in order to coordinate with a video
¦ attribute circuit which will be discussed below.
l Octal transceiver 1110 is utilized to couple data
-, to and from the internal memory bus and inventor buffer 1111
acts as a bus receiver to the internal control memory of the
¦ video formatter.
One of eight decoder lll2 is utilized to select a
I particular integrated circuit memory chip in the internal
control memory and buffer 1113 is utilized to couple the
1 appropriate memory address to the selected integrated air-
l, cult control memory chip.
¦ Referring now to the joint figure formed by Fig-
uses tic and lid there is depicted a schematic reprint-
I¦ lion of the main timing circuitry and display memory timing
If circuitry of the video formatter of the present invention.
20. If The main timing signal is generated by crystal
¦ oscillator 1114 which provides an extremely stable 30.5
, megahertz clock signal. The main clock signal is then dip
voided by two utilizing multi vibrator 1115. Serial in-
¦ parallel out register 1116 is utilized to provide the
I¦ individual bit liming signal. Register 1116 is operated in
the manner of a counter, propagating a pulse through the
register.
I . , - '' ' .
it !
I, -65-
,
the video formatter of the present invention may
I be utilized to supply formatted video to a display terminal
I or other device such as a laser printer. In those apply-
¦ cations in which it is desired to supply video to a remote
device, it will be necessary to provide the image data over
a bus, such as the aforementioned X bus. In such applique-
l lions, it is imperative that the data transmission begin at
! a known point, such as the upper left corner of the image in
the disclosed embodiment. To that end, multi vibrators 1117
and 1118 are utilized to ensure data transmission begins at
the appropriate point. Multi vibrator 1117 is utilized to
l enable the transmit pause as the appropriate portion of the
I data approaches. Multi vibrator 1118 is then utilized to
I establish the synchronization of data transmission at that
! point.
¦, Similarly, multi vibrators 1119 and 1120 are utile
issued to temporarily pause during transmission of image data
jiffy the image memory must be refreshed or the device resolve-
l in the image data is not ready to receive additional data.
Multi vibrator 1119 is utilized to enable the clock pause
I which will eventually stop transmission of the image data.
Multi vibrator 1120 then synchronizes the paused data trays-
mission with fetches of data from image memory.
! Multi vibrator 1121 is the memory timing multi-
, vibrator and generates the timing signals utilized to no-
¦ thieve data from the image memory to be displayed or trays-
¦ milted to remote device. Mul~ibrator 1122 is a slightly -
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. , . ', ,'`
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If i22:5156
faster reacting multi vibrator which is utilized to signal
the end of a byte of image data to the video display con
¦ troller circuit, thus triggering the reading and displaying
of that byte of data. Multi vibrator 1123 is the address '
' I advance vibrator, which is utilized to load or increment the
address counters which are utilized to access image data.
'! referring now to Figures tie, ill and fig, which,
! when joined in the manner indicated in the figures, form a
I schematic diagram of thieved screen format timing circuitry
of the video formatter of the present invention. The
circuitry thus depicted is that circuitry which allows the
defoliation of the discrete display areas previously disk
cussed. Each of the display areas or zones is defined by an
operator in terms of certain parameters. These parameters
include the zone width and height. The zone height is
' ! defined by an arbitrary dimension called "rows" and each
! row is further defined as a particular number of scans by
Thea control device. I,
if ' Recalling that although nine discrete display
¦ areas are possible in the disclosed embodiment, an add-
tonal seven areas are also defined and are utilized for
horizontal and vertical retrace in the video terminal apply-
cation. The data defining these 16 zones is stored in
Al counter control memories which serve to control associated
¦ counters. Each of the counter control memories is comprised
i of a sixty-four bit random access memory organized into ,
sixteen our bit words,
If . ' .
' I -67~
Lo
Thus, counter control memories 1124 and 1125 are
! loaded with data specifying the number of scans of the
¦ display system per row of height. In actual practice, the
¦ data loaded into counter control memories 1124 and 1125
¦ represents the twos complement of the desired number; The
two's complement is utilized to permit simplified operation
of four bit counters 1126 and 1127, which are loaded with
the two's complement number and allowed to count to a carry
l condition.
1 In similar fashion, counter control memories 1128
and 1129 are loaded with data specifying the zone height in
rows, and serve to control four bit counters 1130 and 1131.
Additionally, counter control memories 1132 and 1133 are
¦ loaded with data specifying the width of the zone and serve
I to control four bit counters 1134 and 1135. Those skilled
in the art will appreciate that the sixteen four bit words
I stored in each counter control memory will serve to define
sixteen separate zones. '
Multi vibrator 1136 is utilized to keep track of
1 whether the current frame is odd or even-in number, to
permit control of the interlace circuitry utilized to in-
crease image resolution. Four bit counter 1137 is utilized
- j! in conjunction with the video display controller circuitry
when alphanumeric characters are being generated. A par-
- titular code specifying a selected alphanumeric character is
¦ utilized to enable the video display controller circuitry to
¦ generate the selected character; however, it is still
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I
L -68- .
.
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necessary to keep track of what scan through the display
device the system is currently displaying. Individual
characters, in the disclosed embodiment of the present
invention, are typically twelve scans in height and the
image generated to perform a particular character will vary
with each scan. Four bit counter 1137 is thus utilized to
count the number of scans during character generation.
Those skilled in the art will appreciate this as being
standard dot-matrix character generation.
Multi vibrators 1138 and 1139 are utilized to
cause the initial; loading of counters 1126, 11~7, 1130,
1131, 1134, 1135 and 1137 from their respective control
memories, during startup. Once operating, the Armenia-
toned counters are reloaded during each carry condition,
however, initially this load must be forced as no carry
exists. Multi vibrator 1140 is utilized during alphanumeric
character generation to ensure that an address bump by delta
(explained below) does not occur until after twelve scans
are complete, thus ensuring continuity of alphanumeric
characters. Multi vibrator 1141 is utilized to enable the
address control memories during the first scan in each band
of the display. Multi vibrators 1142 and 1143 are coupled to
the carry outputs of counters 1134 and 1135 and are utilized
to generate various zone width carry signals (ZWCRY) for
utilizat on throughout two video formatter.
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.
-69-
1.
~;225
I
l Logic gates Audi are coupled to the outputs
¦ of zone width counters 1134 and 1135 and the mode select
l signal and are utilized to generate wait signals to a con-
¦ trot device.
referring now to Figures ilk and ill, and the
joint figure formed thereby, there is depicted the display
address circuitry of the video formatter of the present
invention.
Having previously defined the-parameters' of each ;
of the sixteen zones (nine of which are display zones and
seven ox which are utilized for retrace signals) in terms of
! zone width and zone height in the arbitrary dimension ox
"rows" and the number of scans through the display per
Roy," it is now necessary to provide two additional pa-
remitters to operate the video formatter in the manner
described.
First, it is necessary to define a starting
address within the image memory to determine what section of
l the image will be contained within a selected zone. Sea-
11 only, it it likely that the zone width may not be surf-
l¦ficently wide to encompass the entire image, and therefore
Simple unitary address incrementing will not suffice. As
¦ the end of the zone width is reached, the address of the
¦ next byte of image data displayed must be determined by
1 incrementing with a selected number, which is dependent upon
the width of the entire image. This selected number is
referred to variously herein as the "delta" or "burp"
I , ' , , ','
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l . , . . .
I -70-
- :
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I 56
increment. The bump increment is calculated by examining
the width of the image and determining what number must be
added to the starting address to arrive at the start of the
¦ next scan through that zone.
The starting address of each of the zones within
the display relay be stored within control memories 1145-1149
I Control memories 1145-1149 are also sixty-four bit random
axis memories, organized into sixteen four bit words. As
! a matter of design choice, the address of image data stored
1 within image memories in the video formatter ox the present
invention typically contains seventeen bits. Thus control
1 memories 1145-11~9 are capable ox stoning the seventeen bit
starting address of each of the sixteen display zones as
llwritten into the control memories by a control device.
if Control memories 1150-1152 are utilized in a
similar manner to receive and store the "delta" or "bump"
number by which the address of the next byte of image to be
displayed is detennined.~ The starting address of each scan
Through the zone is incremented by the bump increment to
addresses the first bit of image necessary for the next scan
through a selected zone. Quad two input multiplexes 1153-
' 1155 are utilized to shift the "delta" number and thereby
j multiply it by two. This shifting is necessary during
interlace in the non alphanumeric (image mode. Interlace
issue utilized to increase resolution ox the image, and is
'accomplished by skipping a line of the imagined then
utilizing the skipped imaged during the next complete
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frame of the image. In order to skip a line of image data,
the increment number must be twice the normal number to
arrive at the address of the beginning of the scan following
. the next scan.
Having defined each zone by size and starting -
address within the image memory, and by knowing thinker-
mint or address necessary to address the first button the
I next scan through the zone, it is possible to display a
l variable window within the display which may be easily
¦ scrolled in either axis by incrementing the starting ad-
l dress) or enlarged by changing zone dimensions) and may be
! utilized to visually display 'a selected portion of an image.
Further, azalea be explained below, certain zones may be
dedicated to alphanumeric characters indicative of operating .
parameters, prompting cues or other pertinent data.
Referring now to the joint figure formed by
Figures llj and ilk and to Figure 111, there is depicted a
schematic diagram of the display address generation air-
, I quoter of the present invention.
¦ . As discussed above, during operation ox display
I devices, as the beginning of a zone occurs, the previous
starting address must be incremented by a value equal to
that of the width of the image Jo ensure that appropriate
, I data is available during the next scan through a zone (or by
¦ twice the width of the image if image interlace is desired).
Since this increment must take place at the boning of,
each scar through a zone, it is convent to conduct such
. ,' '.
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l -72-
I l
it
loan incrementation at each scan, including the first scan.
swoons the increment would then be added to the starting
¦ address for each zone, a compensation offset to each start-
in address is necessary.
The aforementioned compensated starting address is
stored as previously discussed, in control memories 1145-
1149 and is coupled to the inputs of four bit folders
l 1156-1160. Also coupled to adders 1156-1160 are the outputs
¦ of multiplexes 1153-1155, representing the "delta" inane-
Monet. Thus, adders 1156-1160 add the delta increment to the
compensated starting address and couple the sum to four bit
I by four bit registers 1161-1165. The data thus stored
l represents the actual starting address of image data to be
! displayed in each zone.
The outputs of registers 1161-1165 are coupled to
four bit up counters 1166-1170. Counters 1166-1170 are four
bit counters with three state outputs which are utilized to
incriminate headdress data. The initial data clocked into
' counters 1166-1170 is immediately clocked out onto the bus
. ¦¦ and around to adders 1156-1160 to be incremented by the '
delta increment again. us the new starting address (for the
next scan) is coupled into registers 1161-1165, counters
1166-1170 begin unitary incrementation of the previous
starting address. It is therefore possible, with the de-
plated circuitry, to generate a starting address, increment
that address until the zone boundary is reached, add a delta
in event to he previous starting address to obtain the
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, -73-
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next starting address; and begin incrementing again when the
zone is next entered. Also duped in Figure ilk are
buffers 1171 Andy which are utilized to couple the
. control device into the internal bus. .
Referring now to the joint figure formed by
Figures lam, fin and ho, there is depicted a schematic
If diagram of the video generation and video display controller
< lo circuitry of the video formatter of the present invention.
. I Central to the video generation and video Atari-
¦ byte circuitry is video generator 1173. Video generator
1173 is comprised of, in the illustrated embodiment, an SAC
I 8002 video display controller manufactured by the SAC Micro-
i systems Corporation of Hauppauge, New York, and contains a
mask programmable, on chip, one hundred twenty-eight char-
1 cater generator which utilizes a seven by eleven dot matrix
¦ block. Video generator 1173 also includes attribute logic
. including reverse video, character blank, character blink,
. underline and strike-through.' Additionally, video generator
1173 has four cursor modes including.underline,,blinking
1 underline, reverse, video and blinking reverse video.
Attribute control signals are coupled to video
llgenerator 1.173 by means of multiplexes 1174 and 1175.
¦Multiplexers.1174 and 1175 receive their inputs from either .¦
. attribute latch 1176 or from the data bus. If a global
Al attribute is selected, the correct attribute code is written
Pinto attribute control memories 1177 and 1178 by the control
. device. attribute control memories ll/7 and 1178 are
l . ' " ,.
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sixty four bit random access memories and are utilized to
store the attribute codes for each of the display zones.
During field attribute operation available only in the
alphanumeric mode), selected data from the data bus is
S utilized to generate specific attributes for selected
portions (fields) of the display zone, rather than the
entire zone as in global attribute operations. The selected
I! field attribute data is applied to video generator 1173 by
i means of multiplexes 1174 and 1175. Additional data from
I'M ¦ the data bus it applied to pins AYE of video generator
1173 and is utilized to select a specific character from the
character generator.
Logic gates 1179 and 1180, and the logic gates
l associated therewith, are utilized as a grating function for
1 the attribute capability. Logic gate 1180 is utilized to
enable multiplexes 1174 and Andy the output of logic
gate 1179 is applied to the attribute enable pin (ATTBE) of
l video generator 1173, thus controlling the generation of
¦ video attributes.
I Retriggerable single shot multi vibrators 1181,
'j1182 and 1183 are utilized in conjunction with four bit
keynoter 11~4 to time and generate horizontal and vertical
sync pulses. Multi vibrator 1181 triggers for approximately
' l¦2.5 microseconds aster the beginning of horizontal retrace'jot provide what is commonly referred to as the "front porch"'
of the horizontal retrace pulse. One output of multivlbra-
ion 1181 is utilized to trigger multi vibrator 1182 Which
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I -75-
~225~ I,
provides a five microsecond horizontal sync, the remaining
period of horizontal retrace is the "back porch".
Multi vibrator 1183 is utilized to provide inter-
lace hold off ox the vertical sync pulse. Vertical sync is
delayed for approximately one-half of the horizontal sweep
time to cause interlace and thereby increase image resole
union. Four bit counter 1184 is then utilized to generate
the vertical sync pulse and the "front porch" and "back
porch" periods.
Multivibra~ors 1185 and 1186 are utilized to
provide a delay before the application of horizontal retrace
blanking to compensate for delay encountered due to pipe-
lined internal operation during character generation by
video generator 1173. Interface 1187 is provided to inter-
connect the video formatter of the present invention to a
video terminal interface for use in a video subsystem.
Referring now to Figure aye, there is depicted a
schematic diagram of the cursor control circuitry of the
l video formatter of the present invention. Memory locations
1 within the image memory of the video formatter of the present
l invention are, as a matter of design choice, characterized
¦ by seventeen bit addresses. Since a typical microprocessor
type control device utilizes an eight bit bus, three sepal
rate write commands must be generated to load in seventeen
bits. The cursor address is loaded into multi vibrator 1201
and eight Kit registers 1204 and 1205. The additional
circuitry depicted is coupled to the video address bus and
-76-
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. 3~225~s~
! is utilized to compare the cursor address with each video
address and generate the cursor signal when the correct
. I address is reached. .
Logic gate 1207 is utilized to compare one bit of
cursor address with one bit of video address and to enable
eight bit comparators 1202 Ed 1203. If the comparator
! circuitry indicates a match, and the video display terminal
i is not in the image mode (no cursor.~eing utilized during
image mode) then logic gate 1206 is utilized to generate the
! cursor signal.
With reference now to Figures 12b and 12c, and the
joint figure Wormed thereby, there is depicted a schematic
diagram of the intro device addressing circuitry and run
, length counters of the video formatter of the present invent
! lion. As discussed with respect to the data compression
system, it is possible to have up to sixteen separate ad-
l dress able registers per system which may be directly ad-.
i¦ dressed by a control device.
if The address of a selected register is coupled from
'I a microprocessor type control device through buffers 1208
if and 1209, while various control signals are coupled through
,¦ buffer 1210. Wire strap option 1211 is utilized to specie
- ¦¦ focally identity a particular video formatter, and the
. Jo register address is applied to field programmable logic
1 arrays 1212 and 1213, where the actual address data is
decoded and utilized to access desired registers.
1, . . . . . .
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Also depicted in Figure 12c are the run length
counters and controllers. Recalling that the video image
data being generated by the data expansion circuitry may be
generated in either a ladder or scan mode, it is necessary
to keep track of the length of each "run" of data through
the image in order to accurately reconstruct an original
image as the data is loaded into display memory.
As in previous similar circuits, the run length is
loaded into counter control registers 1214 and 1/215, in
two's complement form. The contents of registers 1214 and
1215 are then loaded into four bit counters 1216-1219, and
counters 1216-1219 are incremented until they reach a carry
condition, thus indicating thinned of a run of data.
Referring now to the joint figures formed by
joining Figures 12d and eye and by joining Figures 12f and
12g, there 'is depicted the address generation circuitry
whereby image data coupled to the video formatter is stored
in image memory within the idea formatter. Recalling the
discussion of ladder format versus scan format for image
data, those skilled in the art will appreciate that coherent
storage of image data within the image memorial require
that each successive byte of image data, while in the ladder
format, will be stored at an address in memory which is
either greater than or less than the previous address by a
value equal to the width of the image. As counters 1216-
1219 enter the carry condition, indicating the end of a run,
the next Al lo of i-age data will be stored a an address -
. ' ,, ,,
I -78
f; ` (.
l I
which is either greater than or less than the previous
If starting address by one Conversely, while in the scan
¦ format, image data addresses will increment or decrement by
! one, until a carry condition in counters 1216-1219 indicates
the end of a run, at which lime the next byte of data will
be stored at an address greater Thor less than the pro-
I virus starting address by a value equal to the width of the
image. The determination in either case of whether to
I increment or decrement the address of the image data it
l¦ determined by the point in a document image at which the
¦ data begins.
Data bus transceiver 1220 is utilized to couple
I¦ the value of the width of the image to width registers 1221
; I and 1222. The two most significant bits in register 1222
, (pins 8Q and 7Q) are utilized for the sign bits for the
I¦ address increments. The outputs of width registers 1121 and
1222 are coupled to multiplexes 1223-1226. Multiplexes
1223-1226 are utilized to output either a plus or a minus
Al one, or a plus or minus width value, as determined by image
11 orientation.
¦ The output of multiplexes 1123-1126 is then
coupled to full adders 1227a-1227f (adders }eye and 1227f
are depicted in Figure 12g) where, the address increment or
I decrement is added to the previous address, or previous
starting address to determine the storage address for the
I next byte Or Image data. The result of this address
.
I
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incrementing is coupled to address registers awoke Greg- ¦
inter 1228c is depicted in Figure 12g~. ¦
¦ Bus transceivers 1229-1231 are utilized Jo couple
; the image data address to the control device. Registers
1 1232-1234 are utilized to temporarily store thy starting
address of each run of image data. The starting address is
¦¦ utilized when counters 1216-1219 inter a carry condition,
indicating the end of a run. The next data address is
l determined by incrementing the previous starting address, -
1 and registers 1232-1234 are therefore utilized to retain
each starting address of a run.
l Referring now to Figures 12h and 12i, and the
! joint figure formed thereby, there is depicted a schematic
representation of certain of the timing circuits of the
video formatter of the present invention. Four bit counter
I 1235 serves as the end of data timer for the video formatter,
¦ counting the number of clock signals after data reception on
the X bus ceases.
l As a matter of design choice t if the X bus clock
1 goes low for eight master clocks, the system will interpret
i it as an end of data, causing end of data multi vibrator 1236
to set. The output of multi vibrator 1236 is utilized to
clear multi vibrator 1237, but not until the completion of
any memory access in progress. Multivibratox 1237 also
US serves to generate the busy signal when date is being
received.
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i Dual four bit ripple counters 123.8 and 1239 are
. the refresh timers which are utilized to time the periods
between each successive refresh operation of the image
I memory. Refresh takes place every 1.6 milliseconds, and the
1 signal output from logic gate 1240 (XCMMIT) is utilized to .
cause the incoming data on the X bus to temporarily stop.
The refresh signal (RFRSH) is coupled to ripple
counter 1241 which is utilized to cycle through the row
I addresses of- the image memories to accomplish refresh. The
I refresh addresses thus generated are latched out therewith
three state outputs ox buffer 1242.
if Dual serial/para.lle:L latch 1243 is the receive .
I latch for image data input from the X bus. Latch. 1243
i accepts eight bits serially off. the X bus and then shifts
! the eight bits into an eight bit wide parallel output latch
where they are grated to the data bus and written into image
memory while the next eight bits are being shifted into
I¦ latch 1243. Four bit counter 1244 is utilized to count the
'I input bits from the X bus to determine when an eight bit
It byte has been input to the system. One output of counter
1244 is utilized to set first byte multi vibrator 1245.
¦ First byte multi vibrator 1245 is utilized to disable the
writing of data into the image memory. Recalling the open-
anion of latch 1243, those ordinarily skilled in the art
will asp: elate to at us a byte of data is accumulated, Ike
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i previous byte is being written into memory. Since during
accumulation of the first byte, no previous byte exists, the
memory write is disabled.
Second byte multi vibrator 1246 is cleared at the
S ; second byte of image data and is utilized to provide the
load pulse which causes the run length to be loaded into
l counter control registers 1214 and 1215. (see Figure 12c~
I Further, since the address incrementing circuitry will not
I be required for the starting address of image data, multi-
¦ vibrator 1246 also is utilized to disable multiplexes
1223-1226. (see Figure 12d)
, I Four bit counter 1247 is the memory timing goner-
¦ atop, which is utilized to operate the image memory in depend-
! entry of the X bus clock. Each time an eight bit byte is
if accumulated in latch 1243, multi vibrator 1248 is utilized to
initiate a memory timing cycle, through logic gate 1250 and
multi vibrator 1249.
', Referring Nat Figures 12j and 12k, and the
I¦ joint figure formed thereby, there is depicted a schematic
Ij,representation of the display memory timing and control
I circuitry of the video formatter of the present invention.
' 'I Multiplexes 1251 and 1252 are utilized to multi- ¦
Jo pled the video address into row and column addresses. The
¦ outputs of multiplexes 1251 and 1252 are coupled to buffers
1¦ 1253 and 1254, which are utilized to drive the image memory,
address 1 nest ,
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Data is written into the image memory via write
buffer 1255 and may be read out onto the data Gus via buffer
I 1256. One of eight decoder 1257 is utilized to decode the
: . I highest three bits of video address to select one of the
! eight banks of image memory. A bank of image memory it
selected by selecting the proper column address strobe
signal (CAY). The selected bank column address strobe
signal is driven by buffer 1258, which is disabled during
refresh by the output of logic gate 1260, acting as an
inventor.
suffer 1259 is utilized to drive the write and row
I¦ address strobe signals. shift registers 1261 and 1262 are
I driven by the 30.5 megahertz clock and are utilized to
I¦ generate timing signals for the image memory. Wire strap
lo I options 1264 and 1265 are utilized to vary the timing signals
¦ generated to accomodate.various types of integrated circuit
I memories which may be utilized in the image memory. Multi-
. ¦ vibrator 1263 is cleared by the output of logic gate 1266
during a read, write or refresh action, and serves to control
1 shift registers 1261 and 1262.
referring now to the joint figure formed by joining
Figures 121, 12mj 12n and OWE, there is depicted a schematic
if representation of the image memory of the video formatter of
I the present invention. Image memory integrated circuits
!¦ aye, aye, aye, aye, aye, aye, aye-
h and aye are each, in a preferred embodiment, a 16K bit
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dynamic random access memory, such as the TAMS 4116 menu-
¦Ifactured by Texas Instruments, Incorporated of Dallas,
I Texas. The eight banks of memory form a 128K byte image-
¦ memory which contains sufficient image data to accurately
' portray an entire display image. Further, in addition to
l image data, alphanumeric character codes may be stored
I within the image memory for character generation by means of
video generator 1173 tree Figure fin).
I, Finally now, reruns to the joint figures formed
by joining Figures 12p and 12q in the manner indicated in
the figures, there is depicted a schematic diagram of the
interface circuitry which couples the video formatter of the
present invention to the other subsystems in the document
processor by means of the X bus.
1 X bus control register 1274 is an internal video
I formatter register which is directly addressable by the
external control device in the manner described herein. The
data input to X bus control rester 1274 is utilized to
llselect a particular one of the eight X bus channels, and
lasso specifies whether the video formatter will receive data
or transmit data. :
j The upper four bits in X bus control register 1274
specify a receive condition and are applied to one of ten
decoder 1275. The output of one of ten decoder 1275 is
1! applied to inventor buffer 1276 and is then utilized to
select one of the eight X bus transceivers aye.
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In the transmit mode, the lower four bits of X bus
control register 1274 are utilized and specify a transmit
condition. The lower four bits are applied to one of ten
decoder 1277, the output of which is utilized to select one
S of eight X bus transceivers aye.
During transmission of data from the video for- f
matter, eight bit wide bytes of dotter coupled to parallel
in-out shift register 1279 for serialization and application
to X bus transceivers aye.
Multi vibrator 1280 is utilized to temporarily
pause transmission of data during the refresh cycle, and is
grated to ensure that the pause takes place at the end of a
clock pulse, to prevent possible split clocks. Multivibra-
ion 1281 is set and holds the clock low when the end of
image data is encountered. After the last bit of data in
the sixteen display zone has been transmitter, multi vibrator
1281 is set and remains set until cleared by the external
control device. This provides the end of data signal to the
receiving device.
LASER PRINTER SUBSYSTEM
An important feature of the document processing
¦ system of the present invention is the ability to produce a
facsimile image of the entire image of a processed document,
any portion thereof, or^m~ltiple portion thereof, for
inclusion in a statement, letter, or other document. With
reference again to Figure 1, the document images for a
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plurality of documents are stored, in one preferred embody-
mint, in magnetic disk storage. Digital computer 100
accesses a selected plurality of digital images via disk
controller 102 and channel selector 116.
¦ The selected digital images are transferred
; through multiplexed direct memory access 166, a sixteen
channel direct memory access designed to be compatible with
digital computer 100. The selected digital images are then
transferred to local X bus through multiplexed direct memory
access 164, a four channel direct memory access designed to
be compatible with the microprocessor utilized in the local
subsystems. If the image data selected is in compacted
fox, it is transferred via local X bus to digital image
expander 162 for expansion, The resultant expanded data is
; 15 transferred through X bus distributor 170 and X bus disk
tributary 132 into a video formatter 134 for formatting and
interfacing into the sequence required by the specific laser
printer system. Video formatter 134 utilizes identical
circuitry to that utilized in video formatters 1008, 1010,
1012 and 1014 of Figure 10, and that circuitry is explained
¦ in greater depth with reference to Figures Lyle and aye-
Jo 12q. The properly formatted image data is temporarily
stored in image memory 128, and selectively applied to laser
printer 130 by printer controller 1260
Video formatter 134 may also be utilized to gent
crate alphanumeric characters for use in addition to the
digital it e data, in those applicatlon3 wherein a singly
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document is required to have an image and alphanumeric
information. In such applications, the image and data
required for the alphanumeric characters are both stored in
, image memory 128.
Laser printer 130, in the embodiment disclosed, is
a Model ND2 high speed printer manufactured by the Simmons
Corporation of Cherry Hill, New Jersey. Laser printer 130
employs laser technology and electrophotogra~hic techniques.
The digital image data is utilized to control a Laser which
exposes selected portions of a rotating, photocond~ctor
surfaced drum. Toner will adhere to the exposed portions of
¦ the drum and will then be transferred to paper in the
manner well known in the art.
It should be appreciated by those skilled in the
¦ art that ink jet or other state of the art printing systems
¦ may be utilized with the document processing system of the
present invention. .
Although the invention has been described with
l reference to a specific embodiment, this description is not
meant to be construed in a limiting sense. Various modify-
I cations of the disclosed embodiment as well as alternative
embodiments of the invention will become apparent to persons
skilled in the art upon reference to the description of the
invention. It is therefore contemplated that the appended
claims will cover any such modifications or embodiments that
; fall within the true scope of the invention.
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